diff --git a/src/arch/aarch64/mm.c b/src/arch/aarch64/mm.c
index c34f404..b960ff5 100644
--- a/src/arch/aarch64/mm.c
+++ b/src/arch/aarch64/mm.c
@@ -83,12 +83,6 @@
 
 #define STAGE2_MEMATTR_NORMAL(outer, inner) ((((outer) << 2) | (inner)) << 2)
 
-/* The following stage-2 memory attributes for device memory. */
-#define STAGE2_MEMATTR_DEVICE_nGnRnE (UINT64_C(0) << 2)
-#define STAGE2_MEMATTR_DEVICE_nGnRE  (UINT64_C(1) << 2)
-#define STAGE2_MEMATTR_DEVICE_nGRE   (UINT64_C(2) << 2)
-#define STAGE2_MEMATTR_DEVICE_GRE    (UINT64_C(3) << 2)
-
 #define STAGE2_ACCESS_READ  UINT64_C(1)
 #define STAGE2_ACCESS_WRITE UINT64_C(2)
 
@@ -360,14 +354,11 @@
 
 		/*
 		 * Define the memory attribute bits, using the "neutral" values
-		 * for either device or normal memory.
+		 * which give the stage-1 attributes full control of the
+		 * attributes.
 		 */
-		if (mode & MM_MODE_D) {
-			attrs |= STAGE2_MEMATTR_DEVICE_GRE;
-		} else {
-			attrs |= STAGE2_MEMATTR_NORMAL(STAGE2_WRITEBACK,
-						       STAGE2_WRITEBACK);
-		}
+		attrs |= STAGE2_MEMATTR_NORMAL(STAGE2_WRITEBACK,
+					       STAGE2_WRITEBACK);
 
 		/* Define the ownership bit. */
 		if (!(mode & MM_MODE_UNOWNED)) {
diff --git a/src/arch/fake/mm.c b/src/arch/fake/mm.c
index 61e0414..f4d28c7 100644
--- a/src/arch/fake/mm.c
+++ b/src/arch/fake/mm.c
@@ -132,12 +132,17 @@
 
 uint8_t arch_mm_root_table_count(int mode)
 {
-	/* Stage 1 has no concatenated tables but stage 2 has 4 of them. */
+	/* Stage-1 has no concatenated tables but stage 2 has 4 of them. */
 	return (mode & MM_MODE_STAGE1) ? 1 : 4;
 }
 
 uint64_t arch_mm_mode_to_attrs(int mode)
 {
+	/* Stage-2 ignores the device mode. */
+	if (!(mode & MM_MODE_STAGE1)) {
+		mode &= ~MM_MODE_D;
+	}
+
 	return ((uint64_t)mode << PTE_ATTR_MODE_SHIFT) & PTE_ATTR_MODE_MASK;
 }
 
diff --git a/src/load.c b/src/load.c
index 3334726..4b0880c 100644
--- a/src/load.c
+++ b/src/load.c
@@ -329,8 +329,7 @@
 		/* Grant VM access to uart. */
 		mm_vm_identity_map(&vm->ptable, pa_init(PL011_BASE),
 				   pa_add(pa_init(PL011_BASE), PAGE_SIZE),
-				   MM_MODE_R | MM_MODE_W | MM_MODE_D |
-					   MM_MODE_NOINVALIDATE,
+				   MM_MODE_R | MM_MODE_W | MM_MODE_NOINVALIDATE,
 				   NULL, ppool);
 
 		/* Grant the VM access to the memory. */