| commit | d1d6798a7958de747dc67ebd26cf780ceb382319 | [log] [tgz] |
|---|---|---|
| author | Fuad Tabba <tabba@google.com> | Wed Jan 08 11:28:29 2020 +0000 |
| committer | Fuad Tabba <tabba@google.com> | Thu Jan 09 14:30:20 2020 +0000 |
| tree | b1ff0f61801aec178985c5246640a3a97e81b510 | |
| parent | 86808c205b7dec478c5d4e87d3408ff2956da73e [diff] |
Use implicit error sync barriers to isolate SError exceptions SError exceptions are asynchronous and can happen at an exception level or VM other than the one responsible for it. Armv8.2 mandates RAS support, which adds the option of having implicit error synchronization barriers on entry or exit from EL2. Error Synchronization Barriers allow the efficient isolation of errors and are lighter weight than other barriers, because they do not order accesses or flush the pipeline necessarily (see Arm Cortex-A76 Core Technical Reference Manual). Before this change a malicious VM could potentially trigger an SError that would cause Hafnium to either panic or to abort another VM. Bug: 147342742 Bug: 140916188 Change-Id: Ie74d58b1de476789fe0876655f28b38098b1c766
Hafnium is a hypervisor, initially supporting aarch64 (64-bit Armv8 CPUs).
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