diff --git a/src/arch/aarch64/inc/hf/arch/cpu.h b/src/arch/aarch64/inc/hf/arch/cpu.h
index 94bc2cb..f2fb4c8 100644
--- a/src/arch/aarch64/inc/hf/arch/cpu.h
+++ b/src/arch/aarch64/inc/hf/arch/cpu.h
@@ -44,18 +44,18 @@
 static inline struct cpu *cpu(void)
 {
 	struct cpu *p;
-	__asm volatile("mrs %0, tpidr_el2" : "=r"(p));
+	__asm__ volatile("mrs %0, tpidr_el2" : "=r"(p));
 	return p;
 }
 
 static inline void arch_irq_disable(void)
 {
-	__asm volatile("msr DAIFSet, #0xf");
+	__asm__ volatile("msr DAIFSet, #0xf");
 }
 
 static inline void arch_irq_enable(void)
 {
-	__asm volatile("msr DAIFClr, #0xf");
+	__asm__ volatile("msr DAIFClr, #0xf");
 }
 
 static inline void arch_cpu_update(bool is_primary)
diff --git a/src/arch/aarch64/mm.c b/src/arch/aarch64/mm.c
index 29bad76..212a56e 100644
--- a/src/arch/aarch64/mm.c
+++ b/src/arch/aarch64/mm.c
@@ -235,10 +235,10 @@
 	    (3 << 28) | /* RES1 bits. */
 	    0;
 
-	__asm volatile("dsb sy");
-	__asm volatile("isb");
+	__asm__ volatile("dsb sy");
+	__asm__ volatile("isb");
 	write_msr(sctlr_el2, v);
-	__asm volatile("isb");
+	__asm__ volatile("isb");
 
 	return true;
 }
diff --git a/src/arch/aarch64/msr.h b/src/arch/aarch64/msr.h
index b98125b..4df39dd 100644
--- a/src/arch/aarch64/msr.h
+++ b/src/arch/aarch64/msr.h
@@ -2,16 +2,16 @@
 
 #include <stddef.h>
 
-#define read_msr(name)                                        \
-	__extension__({                                       \
-		size_t __v;                                   \
-		__asm volatile("mrs %0, " #name : "=r"(__v)); \
-		__v;                                          \
+#define read_msr(name)                                          \
+	__extension__({                                         \
+		size_t __v;                                     \
+		__asm__ volatile("mrs %0, " #name : "=r"(__v)); \
+		__v;                                            \
 	})
 
-#define write_msr(name, value)                           \
-	do {                                             \
-		__asm volatile("msr " #name ", %x0"      \
-			       :                         \
-			       : "rZ"((size_t)(value))); \
+#define write_msr(name, value)                             \
+	do {                                               \
+		__asm__ volatile("msr " #name ", %x0"      \
+				 :                         \
+				 : "rZ"((size_t)(value))); \
 	} while (0)