commit d426b6cb6d2bdde5b7d6c140141f739378d2ca95
author Andrew Walbran <qwandor@google.com> Fri Sep 13 16:30:59 2019 +0100
committer Andrew Walbran <qwandor@google.com> Fri Sep 13 17:58:54 2019 +0100
tree e8e4b548e3a2cacc9dd2f9b8689c1c877448e13c
parent 474c4396e72c33692b0cd40eeb0f3ac7c76fe0f7

Implement SMCCC 1.1.

Change-Id: I6df8dfe9a0f764ee06c2e947bba569b6879b40ba

hf_call.c

diff --git a/hf_call.c b/hf_call.c
index 20e991d..32111ed 100644
--- a/hf_call.c
+++ b/hf_call.c
@@ -25,19 +25,10 @@
 	register uint64_t r2 __asm__("x2") = arg2;
 	register uint64_t r3 __asm__("x3") = arg3;
 
-	/*
-	 * We currently implement SMCCC 1.0, which specifies that the callee can
-	 * use x4–x17 as scratch registers. If we move to SMCCC 1.1 then this
-	 * will change.
-	 */
 	__asm__ volatile(
 		"hvc #0"
 		: /* Output registers, also used as inputs ('+' constraint). */
-		"+r"(r0), "+r"(r1), "+r"(r2), "+r"(r3)
-		:
-		: /* Clobber registers. */
-		"x4", "x5", "x6", "x7", "x8", "x9", "x10", "x11", "x12", "x13",
-		"x14", "x15", "x16", "x17");
+		"+r"(r0), "+r"(r1), "+r"(r2), "+r"(r3));
 
 	return r0;
 }