Update clang to r339409b.
Change-Id: Ied8a188bb072c40035320acedc86164b66d920af
diff --git a/linux-x64/clang/include/llvm/Target/CodeGenCWrappers.h b/linux-x64/clang/include/llvm/Target/CodeGenCWrappers.h
index e9a9905..3ad77c5 100644
--- a/linux-x64/clang/include/llvm/Target/CodeGenCWrappers.h
+++ b/linux-x64/clang/include/llvm/Target/CodeGenCWrappers.h
@@ -31,6 +31,8 @@
LLVM_FALLTHROUGH;
case LLVMCodeModelDefault:
return None;
+ case LLVMCodeModelTiny:
+ return CodeModel::Tiny;
case LLVMCodeModelSmall:
return CodeModel::Small;
case LLVMCodeModelKernel:
@@ -45,6 +47,8 @@
inline LLVMCodeModel wrap(CodeModel::Model Model) {
switch (Model) {
+ case CodeModel::Tiny:
+ return LLVMCodeModelTiny;
case CodeModel::Small:
return LLVMCodeModelSmall;
case CodeModel::Kernel:
diff --git a/linux-x64/clang/include/llvm/Target/GenericOpcodes.td b/linux-x64/clang/include/llvm/Target/GenericOpcodes.td
index 90c121d..399cea9 100644
--- a/linux-x64/clang/include/llvm/Target/GenericOpcodes.td
+++ b/linux-x64/clang/include/llvm/Target/GenericOpcodes.td
@@ -311,6 +311,14 @@
// Overflow ops
//------------------------------------------------------------------------------
+// Generic unsigned addition producing a carry flag.
+def G_UADDO : GenericInstruction {
+ let OutOperandList = (outs type0:$dst, type1:$carry_out);
+ let InOperandList = (ins type0:$src1, type0:$src2);
+ let hasSideEffects = 0;
+ let isCommutable = 1;
+}
+
// Generic unsigned addition consuming and producing a carry flag.
def G_UADDE : GenericInstruction {
let OutOperandList = (outs type0:$dst, type1:$carry_out);
@@ -326,6 +334,19 @@
let isCommutable = 1;
}
+// Generic signed addition consuming and producing a carry flag.
+def G_SADDE : GenericInstruction {
+ let OutOperandList = (outs type0:$dst, type1:$carry_out);
+ let InOperandList = (ins type0:$src1, type0:$src2, type1:$carry_in);
+ let hasSideEffects = 0;
+}
+
+// Generic unsigned subtraction producing a carry flag.
+def G_USUBO : GenericInstruction {
+ let OutOperandList = (outs type0:$dst, type1:$carry_out);
+ let InOperandList = (ins type0:$src1, type0:$src2);
+ let hasSideEffects = 0;
+}
// Generic unsigned subtraction consuming and producing a carry flag.
def G_USUBE : GenericInstruction {
let OutOperandList = (outs type0:$dst, type1:$carry_out);
@@ -333,13 +354,20 @@
let hasSideEffects = 0;
}
-// Generic unsigned subtraction producing a carry flag.
+// Generic signed subtraction producing a carry flag.
def G_SSUBO : GenericInstruction {
let OutOperandList = (outs type0:$dst, type1:$carry_out);
let InOperandList = (ins type0:$src1, type0:$src2);
let hasSideEffects = 0;
}
+// Generic signed subtraction consuming and producing a carry flag.
+def G_SSUBE : GenericInstruction {
+ let OutOperandList = (outs type0:$dst, type1:$carry_out);
+ let InOperandList = (ins type0:$src1, type0:$src2, type1:$carry_in);
+ let hasSideEffects = 0;
+}
+
// Generic unsigned multiplication producing a carry flag.
def G_UMULO : GenericInstruction {
let OutOperandList = (outs type0:$dst, type1:$carry_out);
@@ -513,6 +541,21 @@
}
//------------------------------------------------------------------------------
+// Opcodes for LLVM Intrinsics
+//------------------------------------------------------------------------------
+def G_INTRINSIC_TRUNC : GenericInstruction {
+ let OutOperandList = (outs type0:$dst);
+ let InOperandList = (ins type0:$src1);
+ let hasSideEffects = 0;
+}
+
+def G_INTRINSIC_ROUND : GenericInstruction {
+ let OutOperandList = (outs type0:$dst);
+ let InOperandList = (ins type0:$src1);
+ let hasSideEffects = 0;
+}
+
+//------------------------------------------------------------------------------
// Memory ops
//------------------------------------------------------------------------------
diff --git a/linux-x64/clang/include/llvm/Target/GlobalISel/SelectionDAGCompat.td b/linux-x64/clang/include/llvm/Target/GlobalISel/SelectionDAGCompat.td
index d487759..a3d310c 100644
--- a/linux-x64/clang/include/llvm/Target/GlobalISel/SelectionDAGCompat.td
+++ b/linux-x64/clang/include/llvm/Target/GlobalISel/SelectionDAGCompat.td
@@ -83,6 +83,11 @@
def : GINodeEquiv<G_INTRINSIC_W_SIDE_EFFECTS, intrinsic_w_chain>;
def : GINodeEquiv<G_BR, br>;
def : GINodeEquiv<G_BSWAP, bswap>;
+def : GINodeEquiv<G_CTLZ, ctlz>;
+def : GINodeEquiv<G_CTTZ, cttz>;
+def : GINodeEquiv<G_CTLZ_ZERO_UNDEF, ctlz_zero_undef>;
+def : GINodeEquiv<G_CTTZ_ZERO_UNDEF, cttz_zero_undef>;
+def : GINodeEquiv<G_CTPOP, ctpop>;
// Broadly speaking G_LOAD is equivalent to ISD::LOAD but there are some
// complications that tablegen must take care of. For example, Predicates such
diff --git a/linux-x64/clang/include/llvm/Target/Target.td b/linux-x64/clang/include/llvm/Target/Target.td
index b746505..538605a 100644
--- a/linux-x64/clang/include/llvm/Target/Target.td
+++ b/linux-x64/clang/include/llvm/Target/Target.td
@@ -439,6 +439,7 @@
// instruction.
bit isReturn = 0; // Is this instruction a return instruction?
bit isBranch = 0; // Is this instruction a branch instruction?
+ bit isEHScopeReturn = 0; // Does this instruction end an EH scope?
bit isIndirectBranch = 0; // Is this instruction an indirect branch?
bit isCompare = 0; // Is this instruction a comparison instruction?
bit isMoveImm = 0; // Is this instruction a move immediate instruction?
diff --git a/linux-x64/clang/include/llvm/Target/TargetInstrPredicate.td b/linux-x64/clang/include/llvm/Target/TargetInstrPredicate.td
index 8925e4b..c4b14eb 100644
--- a/linux-x64/clang/include/llvm/Target/TargetInstrPredicate.td
+++ b/linux-x64/clang/include/llvm/Target/TargetInstrPredicate.td
@@ -68,6 +68,7 @@
// Forward declarations.
class Instruction;
+class SchedMachineModel;
// A generic machine instruction predicate.
class MCInstPredicate;
@@ -198,19 +199,24 @@
MCStatement DefaultCase = default;
}
+// Base class for function predicates.
+class FunctionPredicateBase<string name, MCStatement body> {
+ string FunctionName = name;
+ MCStatement Body = body;
+}
+
// Check that a call to method `Name` in class "XXXGenInstrInfo" (where XXX is
-// the `Target` name) returns true.
+// the name of a target) returns true.
//
// TIIPredicate definitions are used to model calls to the target-specific
// InstrInfo. A TIIPredicate is treated specially by the InstrInfoEmitter
// tablegen backend, which will use it to automatically generate a definition in
// the target specific `GenInstrInfo` class.
-class TIIPredicate<string Target, string Name, MCStatement body>
- : MCInstPredicate {
- string TargetName = Target;
- string FunctionName = Name;
- MCStatement Body = body;
-}
+//
+// There cannot be multiple TIIPredicate definitions with the same name for the
+// same target.
+class TIIPredicate<string Name, MCStatement body>
+ : FunctionPredicateBase<Name, body>, MCInstPredicate;
// A function predicate that takes as input a machine instruction, and returns
// a boolean value.
@@ -225,3 +231,100 @@
string MCInstFnName = MCInstFn;
string MachineInstrFnName = MachineInstrFn;
}
+
+// Used to classify machine instructions based on a machine instruction
+// predicate.
+//
+// Let IC be an InstructionEquivalenceClass definition, and MI a machine
+// instruction. We say that MI belongs to the equivalence class described by IC
+// if and only if the following two conditions are met:
+// a) MI's opcode is in the `opcodes` set, and
+// b) `Predicate` evaluates to true when applied to MI.
+//
+// Instances of this class can be used by processor scheduling models to
+// describe instructions that have a property in common. For example,
+// InstructionEquivalenceClass definitions can be used to identify the set of
+// dependency breaking instructions for a processor model.
+//
+// An (optional) list of operand indices can be used to further describe
+// properties that apply to instruction operands. For example, it can be used to
+// identify register uses of a dependency breaking instructions that are not in
+// a RAW dependency.
+class InstructionEquivalenceClass<list<Instruction> opcodes,
+ MCInstPredicate pred,
+ list<int> operands = []> {
+ list<Instruction> Opcodes = opcodes;
+ MCInstPredicate Predicate = pred;
+ list<int> OperandIndices = operands;
+}
+
+// Used by processor models to describe dependency breaking instructions.
+//
+// This is mainly an alias for InstructionEquivalenceClass. Input operand
+// `BrokenDeps` identifies the set of "broken dependencies". There is one bit
+// per each implicit and explicit input operand. An empty set of broken
+// dependencies means: "explicit input register operands are independent."
+class DepBreakingClass<list<Instruction> opcodes, MCInstPredicate pred,
+ list<int> BrokenDeps = []>
+ : InstructionEquivalenceClass<opcodes, pred, BrokenDeps>;
+
+// A function descriptor used to describe the signature of a predicate methods
+// which will be expanded by the STIPredicateExpander into a tablegen'd
+// XXXGenSubtargetInfo class member definition (here, XXX is a target name).
+//
+// It describes the signature of a TargetSubtarget hook, as well as a few extra
+// properties. Examples of extra properties are:
+// - The default return value for the auto-generate function hook.
+// - A list of subtarget hooks (Delegates) that are called from this function.
+//
+class STIPredicateDecl<string name, MCInstPredicate default = FalsePred,
+ bit overrides = 1, bit expandForMC = 1,
+ bit updatesOpcodeMask = 0,
+ list<STIPredicateDecl> delegates = []> {
+ string Name = name;
+
+ MCInstPredicate DefaultReturnValue = default;
+
+ // True if this method is declared as virtual in class TargetSubtargetInfo.
+ bit OverridesBaseClassMember = overrides;
+
+ // True if we need an equivalent predicate function in the MC layer.
+ bit ExpandForMC = expandForMC;
+
+ // True if the autogenerated method has a extra in/out APInt param used as a
+ // mask of operands.
+ bit UpdatesOpcodeMask = updatesOpcodeMask;
+
+ // A list of STIPredicates used by this definition to delegate part of the
+ // computation. For example, STIPredicateFunction `isDependencyBreaking()`
+ // delegates to `isZeroIdiom()` part of its computation.
+ list<STIPredicateDecl> Delegates = delegates;
+}
+
+// A predicate function definition member of class `XXXGenSubtargetInfo`.
+//
+// If `Declaration.ExpandForMC` is true, then SubtargetEmitter
+// will also expand another definition of this method that accepts a MCInst.
+class STIPredicate<STIPredicateDecl declaration,
+ list<InstructionEquivalenceClass> classes> {
+ STIPredicateDecl Declaration = declaration;
+ list<InstructionEquivalenceClass> Classes = classes;
+ SchedMachineModel SchedModel = ?;
+}
+
+// Convenience classes and definitions used by processor scheduling models to
+// describe dependency breaking instructions.
+let UpdatesOpcodeMask = 1 in {
+
+def IsZeroIdiomDecl : STIPredicateDecl<"isZeroIdiom">;
+
+let Delegates = [IsZeroIdiomDecl] in
+def IsDepBreakingDecl : STIPredicateDecl<"isDependencyBreaking">;
+
+} // UpdatesOpcodeMask
+
+class IsZeroIdiomFunction<list<DepBreakingClass> classes>
+ : STIPredicate<IsZeroIdiomDecl, classes>;
+
+class IsDepBreakingFunction<list<DepBreakingClass> classes>
+ : STIPredicate<IsDepBreakingDecl, classes>;
diff --git a/linux-x64/clang/include/llvm/Target/TargetMachine.h b/linux-x64/clang/include/llvm/Target/TargetMachine.h
index 1ca68c8..e743e9f 100644
--- a/linux-x64/clang/include/llvm/Target/TargetMachine.h
+++ b/linux-x64/clang/include/llvm/Target/TargetMachine.h
@@ -84,11 +84,10 @@
CodeGenOpt::Level OptLevel = CodeGenOpt::Default;
/// Contains target specific asm information.
- const MCAsmInfo *AsmInfo;
-
- const MCRegisterInfo *MRI;
- const MCInstrInfo *MII;
- const MCSubtargetInfo *STI;
+ std::unique_ptr<const MCAsmInfo> AsmInfo;
+ std::unique_ptr<const MCRegisterInfo> MRI;
+ std::unique_ptr<const MCInstrInfo> MII;
+ std::unique_ptr<const MCSubtargetInfo> STI;
unsigned RequireStructuredCFG : 1;
unsigned O0WantsFastISel : 1;
@@ -160,11 +159,11 @@
void resetTargetOptions(const Function &F) const;
/// Return target specific asm information.
- const MCAsmInfo *getMCAsmInfo() const { return AsmInfo; }
+ const MCAsmInfo *getMCAsmInfo() const { return AsmInfo.get(); }
- const MCRegisterInfo *getMCRegisterInfo() const { return MRI; }
- const MCInstrInfo *getMCInstrInfo() const { return MII; }
- const MCSubtargetInfo *getMCSubtargetInfo() const { return STI; }
+ const MCRegisterInfo *getMCRegisterInfo() const { return MRI.get(); }
+ const MCInstrInfo *getMCInstrInfo() const { return MII.get(); }
+ const MCSubtargetInfo *getMCSubtargetInfo() const { return STI.get(); }
/// If intrinsic information is available, return it. If not, return null.
virtual const TargetIntrinsicInfo *getIntrinsicInfo() const {
diff --git a/linux-x64/clang/include/llvm/Target/TargetSchedule.td b/linux-x64/clang/include/llvm/Target/TargetSchedule.td
index 6858084..7d7ce2d 100644
--- a/linux-x64/clang/include/llvm/Target/TargetSchedule.td
+++ b/linux-x64/clang/include/llvm/Target/TargetSchedule.td
@@ -373,7 +373,7 @@
SchedMachineModel SchedModel = ?;
code Predicate = pred;
}
-def NoSchedPred : SchedPredicate<[{true}]>;
+def NoSchedPred : MCSchedPredicate<TruePred>;
// Associate a predicate with a list of SchedReadWrites. By default,
// the selected SchedReadWrites are still associated with a single
@@ -550,3 +550,10 @@
// The list of counters that measure issue events.
list<string> Counters = counters;
}
+
+// Each processor can define how to measure NumMicroOps by defining a
+// PfmUopsCounter.
+class PfmUopsCounter<string counter> : PfmCounter {
+ string Counter = counter;
+}
+
diff --git a/linux-x64/clang/include/llvm/Target/TargetSelectionDAG.td b/linux-x64/clang/include/llvm/Target/TargetSelectionDAG.td
index b4debef..4e463b9 100644
--- a/linux-x64/clang/include/llvm/Target/TargetSelectionDAG.td
+++ b/linux-x64/clang/include/llvm/Target/TargetSelectionDAG.td
@@ -217,7 +217,7 @@
]>;
def SDTMaskedStore: SDTypeProfile<0, 3, [ // masked store
- SDTCisPtrTy<0>, SDTCisVec<1>, SDTCisVec<2>, SDTCisSameNumEltsAs<1, 2>
+ SDTCisVec<0>, SDTCisPtrTy<1>, SDTCisVec<2>, SDTCisSameNumEltsAs<0, 2>
]>;
def SDTMaskedLoad: SDTypeProfile<1, 3, [ // masked load
@@ -225,16 +225,6 @@
SDTCisSameNumEltsAs<0, 2>
]>;
-def SDTMaskedGather: SDTypeProfile<2, 3, [ // masked gather
- SDTCisVec<0>, SDTCisVec<1>, SDTCisSameAs<0, 2>, SDTCisSameAs<1, 3>,
- SDTCisPtrTy<4>, SDTCVecEltisVT<1, i1>, SDTCisSameNumEltsAs<0, 1>
-]>;
-
-def SDTMaskedScatter: SDTypeProfile<1, 3, [ // masked scatter
- SDTCisVec<0>, SDTCisVec<1>, SDTCisSameAs<0, 2>, SDTCisSameNumEltsAs<0, 1>,
- SDTCVecEltisVT<0, i1>, SDTCisPtrTy<3>
-]>;
-
def SDTVecShuffle : SDTypeProfile<1, 2, [
SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>
]>;
@@ -510,10 +500,6 @@
[SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
def masked_load : SDNode<"ISD::MLOAD", SDTMaskedLoad,
[SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
-def masked_scatter : SDNode<"ISD::MSCATTER", SDTMaskedScatter,
- [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
-def masked_gather : SDNode<"ISD::MGATHER", SDTMaskedGather,
- [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
// Do not use ld, st directly. Use load, extload, sextload, zextload, store,
// and truncst (see below).
