| # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) |
| # Copyright 2019 BayLibre, SAS |
| %YAML 1.2 |
| --- |
| $id: "http://devicetree.org/schemas/display/amlogic,meson-vpu.yaml#" |
| $schema: "http://devicetree.org/meta-schemas/core.yaml#" |
| |
| title: Amlogic Meson Display Controller |
| |
| maintainers: |
| - Neil Armstrong <narmstrong@baylibre.com> |
| |
| description: | |
| The Amlogic Meson Display controller is composed of several components |
| that are going to be documented below |
| |
| DMC|---------------VPU (Video Processing Unit)----------------|------HHI------| |
| | vd1 _______ _____________ _________________ | | |
| D |-------| |----| | | | | HDMI PLL | |
| D | vd2 | VIU | | Video Post | | Video Encoders |<---|-----VCLK | |
| R |-------| |----| Processing | | | | | |
| | osd2 | | | |---| Enci ----------|----|-----VDAC------| |
| R |-------| CSC |----| Scalers | | Encp ----------|----|----HDMI-TX----| |
| A | osd1 | | | Blenders | | Encl ----------|----|---------------| |
| M |-------|______|----|____________| |________________| | | |
| ___|__________________________________________________________|_______________| |
| |
| |
| VIU: Video Input Unit |
| --------------------- |
| |
| The Video Input Unit is in charge of the pixel scanout from the DDR memory. |
| It fetches the frames addresses, stride and parameters from the "Canvas" memory. |
| This part is also in charge of the CSC (Colorspace Conversion). |
| It can handle 2 OSD Planes and 2 Video Planes. |
| |
| VPP: Video Post Processing |
| -------------------------- |
| |
| The Video Post Processing is in charge of the scaling and blending of the |
| various planes into a single pixel stream. |
| There is a special "pre-blending" used by the video planes with a dedicated |
| scaler and a "post-blending" to merge with the OSD Planes. |
| The OSD planes also have a dedicated scaler for one of the OSD. |
| |
| VENC: Video Encoders |
| -------------------- |
| |
| The VENC is composed of the multiple pixel encoders |
| - ENCI : Interlace Video encoder for CVBS and Interlace HDMI |
| - ENCP : Progressive Video Encoder for HDMI |
| - ENCL : LCD LVDS Encoder |
| The VENC Unit gets a Pixel Clocks (VCLK) from a dedicated HDMI PLL and clock |
| tree and provides the scanout clock to the VPP and VIU. |
| The ENCI is connected to a single VDAC for Composite Output. |
| The ENCI and ENCP are connected to an on-chip HDMI Transceiver. |
| |
| properties: |
| compatible: |
| oneOf: |
| - items: |
| - enum: |
| - amlogic,meson-gxbb-vpu # GXBB (S905) |
| - amlogic,meson-gxl-vpu # GXL (S905X, S905D) |
| - amlogic,meson-gxm-vpu # GXM (S912) |
| - const: amlogic,meson-gx-vpu |
| - enum: |
| - amlogic,meson-g12a-vpu # G12A (S905X2, S905Y2, S905D2) |
| |
| reg: |
| maxItems: 2 |
| |
| reg-names: |
| items: |
| - const: vpu |
| - const: hhi |
| |
| interrupts: |
| maxItems: 1 |
| |
| power-domains: |
| maxItems: 1 |
| description: phandle to the associated power domain |
| |
| port@0: |
| type: object |
| description: |
| A port node pointing to the CVBS VDAC port node. |
| |
| port@1: |
| type: object |
| description: |
| A port node pointing to the HDMI-TX port node. |
| |
| "#address-cells": |
| const: 1 |
| |
| "#size-cells": |
| const: 0 |
| |
| required: |
| - compatible |
| - reg |
| - interrupts |
| - port@0 |
| - port@1 |
| - "#address-cells" |
| - "#size-cells" |
| |
| examples: |
| - | |
| vpu: vpu@d0100000 { |
| compatible = "amlogic,meson-gxbb-vpu", "amlogic,meson-gx-vpu"; |
| reg = <0xd0100000 0x100000>, <0xc883c000 0x1000>; |
| reg-names = "vpu", "hhi"; |
| interrupts = <3>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| |
| /* CVBS VDAC output port */ |
| port@0 { |
| reg = <0>; |
| |
| cvbs_vdac_out: endpoint { |
| remote-endpoint = <&tv_connector_in>; |
| }; |
| }; |
| |
| /* HDMI TX output port */ |
| port@1 { |
| reg = <1>; |
| |
| hdmi_tx_out: endpoint { |
| remote-endpoint = <&hdmi_tx_in>; |
| }; |
| }; |
| }; |
