* Renesas SDHI SD/MMC controller

Required properties:
- compatible: should contain one or more of the following:
		"renesas,sdhi-sh73a0" - SDHI IP on SH73A0 SoC
		"renesas,sdhi-r7s72100" - SDHI IP on R7S72100 SoC
		"renesas,sdhi-r7s9210" - SDHI IP on R7S9210 SoC
		"renesas,sdhi-r8a73a4" - SDHI IP on R8A73A4 SoC
		"renesas,sdhi-r8a7740" - SDHI IP on R8A7740 SoC
		"renesas,sdhi-r8a7743" - SDHI IP on R8A7743 SoC
		"renesas,sdhi-r8a7744" - SDHI IP on R8A7744 SoC
		"renesas,sdhi-r8a7745" - SDHI IP on R8A7745 SoC
		"renesas,sdhi-r8a774a1" - SDHI IP on R8A774A1 SoC
		"renesas,sdhi-r8a774c0" - SDHI IP on R8A774C0 SoC
		"renesas,sdhi-r8a77470" - SDHI IP on R8A77470 SoC
		"renesas,sdhi-mmc-r8a77470" - SDHI/MMC IP on R8A77470 SoC
		"renesas,sdhi-r8a7778" - SDHI IP on R8A7778 SoC
		"renesas,sdhi-r8a7779" - SDHI IP on R8A7779 SoC
		"renesas,sdhi-r8a7790" - SDHI IP on R8A7790 SoC
		"renesas,sdhi-r8a7791" - SDHI IP on R8A7791 SoC
		"renesas,sdhi-r8a7792" - SDHI IP on R8A7792 SoC
		"renesas,sdhi-r8a7793" - SDHI IP on R8A7793 SoC
		"renesas,sdhi-r8a7794" - SDHI IP on R8A7794 SoC
		"renesas,sdhi-r8a7795" - SDHI IP on R8A7795 SoC
		"renesas,sdhi-r8a7796" - SDHI IP on R8A7796 SoC
		"renesas,sdhi-r8a77965" - SDHI IP on R8A77965 SoC
		"renesas,sdhi-r8a77970" - SDHI IP on R8A77970 SoC
		"renesas,sdhi-r8a77980" - SDHI IP on R8A77980 SoC
		"renesas,sdhi-r8a77990" - SDHI IP on R8A77990 SoC
		"renesas,sdhi-r8a77995" - SDHI IP on R8A77995 SoC
		"renesas,sdhi-shmobile" - a generic sh-mobile SDHI controller
		"renesas,rcar-gen1-sdhi" - a generic R-Car Gen1 SDHI controller
		"renesas,rcar-gen2-sdhi" - a generic R-Car Gen2 and RZ/G1 SDHI
					   (not SDHI/MMC) controller
		"renesas,rcar-gen3-sdhi" - a generic R-Car Gen3 or RZ/G2
					   SDHI controller


		When compatible with the generic version, nodes must list
		the SoC-specific version corresponding to the platform
		first followed by the generic version.

- clocks: Most controllers only have 1 clock source per channel. However, on
	  some variations of this controller, the internal card detection
	  logic that exists in this controller is sectioned off to be run by a
	  separate second clock source to allow the main core clock to be turned
	  off to save power.
	  If 2 clocks are specified by the hardware, you must name them as
	  "core" and "cd". If the controller only has 1 clock, naming is not
	  required.
	  Devices which have more than 1 clock are listed below:
	  2: R7S72100, R7S9210

Optional properties:
- pinctrl-names: should be "default", "state_uhs"
- pinctrl-0: should contain default/high speed pin ctrl
- pinctrl-1: should contain uhs mode pin ctrl

Example: R8A7790 (R-Car H2) SDHI controller nodes

	sdhi0: sd@ee100000 {
		compatible = "renesas,sdhi-r8a7790", "renesas,rcar-gen2-sdhi";
		reg = <0 0xee100000 0 0x328>;
		interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&cpg CPG_MOD 314>;
		dmas = <&dmac0 0xcd>, <&dmac0 0xce>,
		       <&dmac1 0xcd>, <&dmac1 0xce>;
		dma-names = "tx", "rx", "tx", "rx";
		max-frequency = <195000000>;
		power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
		resets = <&cpg 314>;
	};

	sdhi1: sd@ee120000 {
		compatible = "renesas,sdhi-r8a7790", "renesas,rcar-gen2-sdhi";
		reg = <0 0xee120000 0 0x328>;
		interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&cpg CPG_MOD 313>;
		dmas = <&dmac0 0xc9>, <&dmac0 0xca>,
		       <&dmac1 0xc9>, <&dmac1 0xca>;
		dma-names = "tx", "rx", "tx", "rx";
		max-frequency = <195000000>;
		power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
		resets = <&cpg 313>;
	};

	sdhi2: sd@ee140000 {
		compatible = "renesas,sdhi-r8a7790", "renesas,rcar-gen2-sdhi";
		reg = <0 0xee140000 0 0x100>;
		interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&cpg CPG_MOD 312>;
		dmas = <&dmac0 0xc1>, <&dmac0 0xc2>,
		       <&dmac1 0xc1>, <&dmac1 0xc2>;
		dma-names = "tx", "rx", "tx", "rx";
		max-frequency = <97500000>;
		power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
		resets = <&cpg 312>;
	};

	sdhi3: sd@ee160000 {
		compatible = "renesas,sdhi-r8a7790", "renesas,rcar-gen2-sdhi";
		reg = <0 0xee160000 0 0x100>;
		interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&cpg CPG_MOD 311>;
		dmas = <&dmac0 0xd3>, <&dmac0 0xd4>,
		       <&dmac1 0xd3>, <&dmac1 0xd4>;
		dma-names = "tx", "rx", "tx", "rx";
		max-frequency = <97500000>;
		power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
		resets = <&cpg 311>;
	};