Qualcomm QMP PHY controller
===========================

QMP phy controller supports physical layer functionality for a number of
controllers on Qualcomm chipsets, such as, PCIe, UFS, and USB.

Required properties:
 - compatible: compatible list, contains:
	       "qcom,ipq8074-qmp-pcie-phy" for PCIe phy on IPQ8074
	       "qcom,msm8996-qmp-pcie-phy" for 14nm PCIe phy on msm8996,
	       "qcom,msm8996-qmp-usb3-phy" for 14nm USB3 phy on msm8996,
	       "qcom,msm8998-qmp-usb3-phy" for USB3 QMP V3 phy on msm8998,
	       "qcom,msm8998-qmp-ufs-phy" for UFS QMP phy on msm8998,
	       "qcom,msm8998-qmp-pcie-phy" for PCIe QMP phy on msm8998,
	       "qcom,sdm845-qmp-usb3-phy" for USB3 QMP V3 phy on sdm845,
	       "qcom,sdm845-qmp-usb3-uni-phy" for USB3 QMP V3 UNI phy on sdm845,
	       "qcom,sdm845-qmp-ufs-phy" for UFS QMP phy on sdm845.

- reg:
  - index 0: address and length of register set for PHY's common
             serdes block.
  - index 1: address and length of the DP_COM control block (for
             "qcom,sdm845-qmp-usb3-phy" only).

- reg-names:
  - For "qcom,sdm845-qmp-usb3-phy":
    - Should be: "reg-base", "dp_com"
  - For all others:
    - The reg-names property shouldn't be defined.

 - #address-cells: must be 1
 - #size-cells: must be 1
 - ranges: must be present

 - clocks: a list of phandles and clock-specifier pairs,
	   one for each entry in clock-names.
 - clock-names: "cfg_ahb" for phy config clock,
		"aux" for phy aux clock,
		"ref" for 19.2 MHz ref clk,
		"com_aux" for phy common block aux clock,
		"ref_aux" for phy reference aux clock,

		For "qcom,ipq8074-qmp-pcie-phy": no clocks are listed.
		For "qcom,msm8996-qmp-pcie-phy" must contain:
			"aux", "cfg_ahb", "ref".
		For "qcom,msm8996-qmp-usb3-phy" must contain:
			"aux", "cfg_ahb", "ref".
		For "qcom,msm8998-qmp-usb3-phy" must contain:
			"aux", "cfg_ahb", "ref".
		For "qcom,msm8998-qmp-ufs-phy" must contain:
			"ref", "ref_aux".
		For "qcom,msm8998-qmp-pcie-phy" must contain:
			"aux", "cfg_ahb", "ref".
		For "qcom,sdm845-qmp-usb3-phy" must contain:
			"aux", "cfg_ahb", "ref", "com_aux".
		For "qcom,sdm845-qmp-usb3-uni-phy" must contain:
			"aux", "cfg_ahb", "ref", "com_aux".
		For "qcom,sdm845-qmp-ufs-phy" must contain:
			"ref", "ref_aux".

 - resets: a list of phandles and reset controller specifier pairs,
	   one for each entry in reset-names.
 - reset-names: "phy" for reset of phy block,
		"common" for phy common block reset,
		"cfg" for phy's ahb cfg block reset,
		"ufsphy" for the PHY reset in the UFS controller.

		For "qcom,ipq8074-qmp-pcie-phy" must contain:
			"phy", "common".
		For "qcom,msm8996-qmp-pcie-phy" must contain:
			"phy", "common", "cfg".
		For "qcom,msm8996-qmp-usb3-phy" must contain
			"phy", "common".
		For "qcom,msm8998-qmp-usb3-phy" must contain
			"phy", "common".
		For "qcom,msm8998-qmp-ufs-phy": must contain:
			"ufsphy".
		For "qcom,msm8998-qmp-pcie-phy" must contain:
			"phy", "common".
		For "qcom,sdm845-qmp-usb3-phy" must contain:
			"phy", "common".
		For "qcom,sdm845-qmp-usb3-uni-phy" must contain:
			"phy", "common".
		For "qcom,sdm845-qmp-ufs-phy": must contain:
			"ufsphy".

 - vdda-phy-supply: Phandle to a regulator supply to PHY core block.
 - vdda-pll-supply: Phandle to 1.8V regulator supply to PHY refclk pll block.

Optional properties:
 - vddp-ref-clk-supply: Phandle to a regulator supply to any specific refclk
			pll block.

Required nodes:
 - Each device node of QMP phy is required to have as many child nodes as
   the number of lanes the PHY has.

Required properties for child nodes of PCIe PHYs (one child per lane):
 - reg: list of offset and length pairs of register sets for PHY blocks -
	tx, rx, pcs, and pcs_misc (optional).
 - #phy-cells: must be 0

Required properties for a single "lanes" child node of non-PCIe PHYs:
 - reg: list of offset and length pairs of register sets for PHY blocks
	For 1-lane devices:
		tx, rx, pcs, and (optionally) pcs_misc
	For 2-lane devices:
		tx0, rx0, pcs, tx1, rx1, and (optionally) pcs_misc
 - #phy-cells: must be 0

Required properties for child node of PCIe and USB3 qmp phys:
 - clocks: a list of phandles and clock-specifier pairs,
	   one for each entry in clock-names.
 - clock-names: Must contain following:
		 "pipe<lane-number>" for pipe clock specific to each lane.
 - clock-output-names: Name of the PHY clock that will be the parent for
		       the above pipe clock.
	For "qcom,ipq8074-qmp-pcie-phy":
		- "pcie20_phy0_pipe_clk"	Pipe Clock parent
			(or)
		  "pcie20_phy1_pipe_clk"
 - #clock-cells: must be 0
    - Phy pll outputs pipe clocks for pipe based PHYs. These clocks are then
      gate-controlled by the gcc.

Required properties for child node of PHYs with lane reset, AKA:
	"qcom,msm8996-qmp-pcie-phy"
 - resets: a list of phandles and reset controller specifier pairs,
	   one for each entry in reset-names.
 - reset-names: Must contain following:
		 "lane<lane-number>" for reset specific to each lane.

Example:
	phy@34000 {
		compatible = "qcom,msm8996-qmp-pcie-phy";
		reg = <0x34000 0x488>;
		#address-cells = <1>;
		#size-cells = <1>;
		ranges;

		clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>,
			<&gcc GCC_PCIE_PHY_CFG_AHB_CLK>,
			<&gcc GCC_PCIE_CLKREF_CLK>;
		clock-names = "aux", "cfg_ahb", "ref";

		vdda-phy-supply = <&pm8994_l28>;
		vdda-pll-supply = <&pm8994_l12>;

		resets = <&gcc GCC_PCIE_PHY_BCR>,
			<&gcc GCC_PCIE_PHY_COM_BCR>,
			<&gcc GCC_PCIE_PHY_COM_NOCSR_BCR>;
		reset-names = "phy", "common", "cfg";

		pciephy_0: lane@35000 {
			reg = <0x35000 0x130>,
				<0x35200 0x200>,
				<0x35400 0x1dc>;
			#clock-cells = <0>;
			#phy-cells = <0>;

			clocks = <&gcc GCC_PCIE_0_PIPE_CLK>;
			clock-names = "pipe0";
			clock-output-names = "pcie_0_pipe_clk_src";
			resets = <&gcc GCC_PCIE_0_PHY_BCR>;
			reset-names = "lane0";
		};

		pciephy_1: lane@36000 {
		...
		...
	};

	phy@88eb000 {
		compatible = "qcom,sdm845-qmp-usb3-uni-phy";
		reg = <0x88eb000 0x18c>;
		#address-cells = <1>;
		#size-cells = <1>;
		ranges;

		clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK>,
			 <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
			 <&gcc GCC_USB3_SEC_CLKREF_CLK>,
			 <&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>;
		clock-names = "aux", "cfg_ahb", "ref", "com_aux";

		resets = <&gcc GCC_USB3PHY_PHY_SEC_BCR>,
			 <&gcc GCC_USB3_PHY_SEC_BCR>;
		reset-names = "phy", "common";

		lane@88eb200 {
			reg = <0x88eb200 0x128>,
			      <0x88eb400 0x1fc>,
			      <0x88eb800 0x218>,
			      <0x88eb600 0x70>;
			#clock-cells = <0>;
			#phy-cells = <0>;
			clocks = <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>;
			clock-names = "pipe0";
			clock-output-names = "usb3_uni_phy_pipe_clk_src";
		};
	};

	phy@1d87000 {
		compatible = "qcom,sdm845-qmp-ufs-phy";
		reg = <0x1d87000 0x18c>;
		#address-cells = <1>;
		#size-cells = <1>;
		ranges;
		clock-names = "ref",
			      "ref_aux";
		clocks = <&gcc GCC_UFS_MEM_CLKREF_CLK>,
			 <&gcc GCC_UFS_PHY_PHY_AUX_CLK>;

		lanes@1d87400 {
			reg = <0x1d87400 0x108>,
			      <0x1d87600 0x1e0>,
			      <0x1d87c00 0x1dc>,
			      <0x1d87800 0x108>,
			      <0x1d87a00 0x1e0>;
			#phy-cells = <0>;
		};
	};