Documentation/devicetree/bindings/arm/pmu.txt

* ARM Performance Monitor Units

ARM cores often have a PMU for counting cpu and cache events like cache misses
and hits. The interface to the PMU is part of the ARM ARM. The ARM PMU
representation in the device tree should be done as under:-

Required properties:

- compatible : should be one of
	"apm,potenza-pmu"
	"arm,armv8-pmuv3"
	"arm,cortex-a73-pmu"
	"arm,cortex-a72-pmu"
	"arm,cortex-a57-pmu"
	"arm,cortex-a53-pmu"
	"arm,cortex-a35-pmu"
	"arm,cortex-a17-pmu"
	"arm,cortex-a15-pmu"
	"arm,cortex-a12-pmu"
	"arm,cortex-a9-pmu"
	"arm,cortex-a8-pmu"
	"arm,cortex-a7-pmu"
	"arm,cortex-a5-pmu"
	"arm,arm11mpcore-pmu"
	"arm,arm1176-pmu"
	"arm,arm1136-pmu"
	"brcm,vulcan-pmu"
	"cavium,thunder-pmu"
	"qcom,scorpion-pmu"
	"qcom,scorpion-mp-pmu"
	"qcom,krait-pmu"
- interrupts : 1 combined interrupt or 1 per core. If the interrupt is a per-cpu
               interrupt (PPI) then 1 interrupt should be specified.

Optional properties:

- interrupt-affinity : When using SPIs, specifies a list of phandles to CPU
                       nodes corresponding directly to the affinity of
		       the SPIs listed in the interrupts property.

                       When using a PPI, specifies a list of phandles to CPU
		       nodes corresponding to the set of CPUs which have
		       a PMU of this type signalling the PPI listed in the
		       interrupts property, unless this is already specified
		       by the PPI interrupt specifier itself (in which case
		       the interrupt-affinity property shouldn't be present).

                       This property should be present when there is more than
		       a single SPI.


- qcom,no-pc-write : Indicates that this PMU doesn't support the 0xc and 0xd
                     events.

- secure-reg-access : Indicates that the ARMv7 Secure Debug Enable Register
		      (SDER) is accessible. This will cause the driver to do
		      any setup required that is only possible in ARMv7 secure
		      state. If not present the ARMv7 SDER will not be touched,
		      which means the PMU may fail to operate unless external
		      code (bootloader or security monitor) has performed the
		      appropriate initialisation. Note that this property is
		      not valid for non-ARMv7 CPUs or ARMv7 CPUs booting Linux
		      in Non-secure state.

Example:

pmu {
        compatible = "arm,cortex-a9-pmu";
        interrupts = <100 101>;
};