Documentation/devicetree/bindings/display/sunxi/sun6i-dsi.txt

Allwinner A31 DSI Encoder
=========================

The DSI pipeline consists of two separate blocks: the DSI controller
itself, and its associated D-PHY.

DSI Encoder
-----------

The DSI Encoder generates the DSI signal from the TCON's.

Required properties:
  - compatible: value must be one of:
    * allwinner,sun6i-a31-mipi-dsi
  - reg: base address and size of memory-mapped region
  - interrupts: interrupt associated to this IP
  - clocks: phandles to the clocks feeding the DSI encoder
    * bus: the DSI interface clock
    * mod: the DSI module clock
  - clock-names: the clock names mentioned above
  - phys: phandle to the D-PHY
  - phy-names: must be "dphy"
  - resets: phandle to the reset controller driving the encoder

  - ports: A ports node with endpoint definitions as defined in
    Documentation/devicetree/bindings/media/video-interfaces.txt. The
    first port should be the input endpoint, usually coming from the
    associated TCON.

Any MIPI-DSI device attached to this should be described according to
the bindings defined in ../mipi-dsi-bus.txt

D-PHY
-----

Required properties:
  - compatible: value must be one of:
    * allwinner,sun6i-a31-mipi-dphy
  - reg: base address and size of memory-mapped region
  - clocks: phandles to the clocks feeding the DSI encoder
    * bus: the DSI interface clock
    * mod: the DSI module clock
  - clock-names: the clock names mentioned above
  - resets: phandle to the reset controller driving the encoder

Example:

dsi0: dsi@1ca0000 {
	compatible = "allwinner,sun6i-a31-mipi-dsi";
	reg = <0x01ca0000 0x1000>;
	interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&ccu CLK_BUS_MIPI_DSI>,
		 <&ccu CLK_DSI_SCLK>;
	clock-names = "bus", "mod";
	resets = <&ccu RST_BUS_MIPI_DSI>;
	phys = <&dphy0>;
	phy-names = "dphy";
	#address-cells = <1>;
	#size-cells = <0>;

	panel@0 {
		compatible = "bananapi,lhr050h41", "ilitek,ili9881c";
		reg = <0>;
		power-gpios = <&pio 1 7 GPIO_ACTIVE_HIGH>; /* PB07 */
		reset-gpios = <&r_pio 0 5 GPIO_ACTIVE_LOW>; /* PL05 */
		backlight = <&pwm_bl>;
	};

	ports {
		#address-cells = <1>;
		#size-cells = <0>;

		port@0 {
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <0>;

			dsi0_in_tcon0: endpoint {
				remote-endpoint = <&tcon0_out_dsi0>;
			};
		};
	};
};

dphy0: d-phy@1ca1000 {
	compatible = "allwinner,sun6i-a31-mipi-dphy";
	reg = <0x01ca1000 0x1000>;
	clocks = <&ccu CLK_BUS_MIPI_DSI>,
		 <&ccu CLK_DSI_DPHY>;
	clock-names = "bus", "mod";
	resets = <&ccu RST_BUS_MIPI_DSI>;
	#phy-cells = <0>;
};