// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/*
 * Copyright (C) 2015 Marvell Technology Group Ltd.
 *
 * Author: Jisheng Zhang <jszhang@marvell.com>
 */

#include <dt-bindings/interrupt-controller/arm-gic.h>

/ {
	compatible = "marvell,berlin4ct", "marvell,berlin";
	interrupt-parent = <&gic>;
	#address-cells = <2>;
	#size-cells = <2>;

	aliases {
		serial0 = &uart0;
	};

	psci {
		compatible = "arm,psci-1.0", "arm,psci-0.2";
		method = "smc";
	};

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu0: cpu@0 {
			compatible = "arm,cortex-a53", "arm,armv8";
			device_type = "cpu";
			reg = <0x0>;
			enable-method = "psci";
			next-level-cache = <&l2>;
			cpu-idle-states = <&CPU_SLEEP_0>;
		};

		cpu1: cpu@1 {
			compatible = "arm,cortex-a53", "arm,armv8";
			device_type = "cpu";
			reg = <0x1>;
			enable-method = "psci";
			next-level-cache = <&l2>;
			cpu-idle-states = <&CPU_SLEEP_0>;
		};

		cpu2: cpu@2 {
			compatible = "arm,cortex-a53", "arm,armv8";
			device_type = "cpu";
			reg = <0x2>;
			enable-method = "psci";
			next-level-cache = <&l2>;
			cpu-idle-states = <&CPU_SLEEP_0>;
		};

		cpu3: cpu@3 {
			compatible = "arm,cortex-a53", "arm,armv8";
			device_type = "cpu";
			reg = <0x3>;
			enable-method = "psci";
			next-level-cache = <&l2>;
			cpu-idle-states = <&CPU_SLEEP_0>;
		};

		l2: cache {
			compatible = "cache";
		};

		idle-states {
			entry-method = "psci";
			CPU_SLEEP_0: cpu-sleep-0 {
				compatible = "arm,idle-state";
				local-timer-stop;
				arm,psci-suspend-param = <0x0010000>;
				entry-latency-us = <75>;
				exit-latency-us = <155>;
				min-residency-us = <1000>;
			};
		};
	};

	osc: osc {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <25000000>;
	};

	pmu {
		compatible = "arm,cortex-a53-pmu", "arm,armv8-pmuv3";
		interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-affinity = <&cpu0>,
				     <&cpu1>,
				     <&cpu2>,
				     <&cpu3>;
	};

	timer {
		compatible = "arm,armv8-timer";
		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
			     <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
			     <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
			     <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
	};

	soc@f7000000 {
		compatible = "simple-bus";
		#address-cells = <1>;
		#size-cells = <1>;
		ranges = <0 0 0xf7000000 0x1000000>;

		gic: interrupt-controller@901000 {
			compatible = "arm,gic-400";
			#interrupt-cells = <3>;
			interrupt-controller;
			reg = <0x901000 0x1000>,
			      <0x902000 0x2000>,
			      <0x904000 0x2000>,
			      <0x906000 0x2000>;
			interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
		};

		apb@e80000 {
			compatible = "simple-bus";
			#address-cells = <1>;
			#size-cells = <1>;

			ranges = <0 0xe80000 0x10000>;
			interrupt-parent = <&aic>;

			gpio0: gpio@400 {
				compatible = "snps,dw-apb-gpio";
				reg = <0x0400 0x400>;
				#address-cells = <1>;
				#size-cells = <0>;

				porta: gpio-port@0 {
					compatible = "snps,dw-apb-gpio-port";
					gpio-controller;
					#gpio-cells = <2>;
					snps,nr-gpios = <32>;
					reg = <0>;
					interrupt-controller;
					#interrupt-cells = <2>;
					interrupts = <0>;
				};
			};

			gpio1: gpio@800 {
				compatible = "snps,dw-apb-gpio";
				reg = <0x0800 0x400>;
				#address-cells = <1>;
				#size-cells = <0>;

				portb: gpio-port@1 {
					compatible = "snps,dw-apb-gpio-port";
					gpio-controller;
					#gpio-cells = <2>;
					snps,nr-gpios = <32>;
					reg = <0>;
					interrupt-controller;
					#interrupt-cells = <2>;
					interrupts = <1>;
				};
			};

			gpio2: gpio@c00 {
				compatible = "snps,dw-apb-gpio";
				reg = <0x0c00 0x400>;
				#address-cells = <1>;
				#size-cells = <0>;

				portc: gpio-port@2 {
					compatible = "snps,dw-apb-gpio-port";
					gpio-controller;
					#gpio-cells = <2>;
					snps,nr-gpios = <32>;
					reg = <0>;
					interrupt-controller;
					#interrupt-cells = <2>;
					interrupts = <2>;
				};
			};

			gpio3: gpio@1000 {
				compatible = "snps,dw-apb-gpio";
				reg = <0x1000 0x400>;
				#address-cells = <1>;
				#size-cells = <0>;

				portd: gpio-port@3 {
					compatible = "snps,dw-apb-gpio-port";
					gpio-controller;
					#gpio-cells = <2>;
					snps,nr-gpios = <32>;
					reg = <0>;
					interrupt-controller;
					#interrupt-cells = <2>;
					interrupts = <3>;
				};
			};

			aic: interrupt-controller@3800 {
				compatible = "snps,dw-apb-ictl";
				reg = <0x3800 0x30>;
				interrupt-controller;
				#interrupt-cells = <1>;
				interrupt-parent = <&gic>;
				interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
			};
		};

		soc_pinctrl: pin-controller@ea8000 {
			compatible = "marvell,berlin4ct-soc-pinctrl";
			reg = <0xea8000 0x14>;
		};

		avio_pinctrl: pin-controller@ea8400 {
			compatible = "marvell,berlin4ct-avio-pinctrl";
			reg = <0xea8400 0x8>;
		};

		apb@fc0000 {
			compatible = "simple-bus";
			#address-cells = <1>;
			#size-cells = <1>;
			ranges = <0 0xfc0000 0x10000>;
			interrupt-parent = <&sic>;

			sic: interrupt-controller@1000 {
				compatible = "snps,dw-apb-ictl";
				reg = <0x1000 0x30>;
				interrupt-controller;
				#interrupt-cells = <1>;
				interrupt-parent = <&gic>;
				interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
			};

			wdt0: watchdog@3000 {
				compatible = "snps,dw-wdt";
				reg = <0x3000 0x100>;
				clocks = <&osc>;
				interrupts = <0>;
			};

			wdt1: watchdog@4000 {
				compatible = "snps,dw-wdt";
				reg = <0x4000 0x100>;
				clocks = <&osc>;
				interrupts = <1>;
			};

			wdt2: watchdog@5000 {
				compatible = "snps,dw-wdt";
				reg = <0x5000 0x100>;
				clocks = <&osc>;
				interrupts = <2>;
			};

			sm_gpio0: gpio@8000 {
				compatible = "snps,dw-apb-gpio";
				reg = <0x8000 0x400>;
				#address-cells = <1>;
				#size-cells = <0>;

				porte: gpio-port@4 {
					compatible = "snps,dw-apb-gpio-port";
					gpio-controller;
					#gpio-cells = <2>;
					snps,nr-gpios = <32>;
					reg = <0>;
				};
			};

			sm_gpio1: gpio@9000 {
				compatible = "snps,dw-apb-gpio";
				reg = <0x9000 0x400>;
				#address-cells = <1>;
				#size-cells = <0>;

				portf: gpio-port@5 {
					compatible = "snps,dw-apb-gpio-port";
					gpio-controller;
					#gpio-cells = <2>;
					snps,nr-gpios = <32>;
					reg = <0>;
				};
			};

			uart0: uart@d000 {
				compatible = "snps,dw-apb-uart";
				reg = <0xd000 0x100>;
				interrupts = <8>;
				clocks = <&osc>;
				reg-shift = <2>;
				status = "disabled";
				pinctrl-0 = <&uart0_pmux>;
				pinctrl-names = "default";
			};
		};

		system_pinctrl: pin-controller@fe2200 {
			compatible = "marvell,berlin4ct-system-pinctrl";
			reg = <0xfe2200 0xc>;

			uart0_pmux: uart0-pmux {
				groups = "SM_URT0_TXD", "SM_URT0_RXD";
				function = "uart0";
			};
		};
	};
};