[
    {
        "PublicDescription": "Demand data read requests that missed L2, no rejects.",
        "EventCode": "0x24",
        "Counter": "0,1,2,3",
        "UMask": "0x21",
        "Errata": "HSD78",
        "EventName": "L2_RQSTS.DEMAND_DATA_RD_MISS",
        "SampleAfterValue": "200003",
        "BriefDescription": "Demand Data Read miss L2, no rejects",
        "CounterHTOff": "0,1,2,3,4,5,6,7"
    },
    {
        "PublicDescription": "Counts the number of store RFO requests that miss the L2 cache.",
        "EventCode": "0x24",
        "Counter": "0,1,2,3",
        "UMask": "0x22",
        "EventName": "L2_RQSTS.RFO_MISS",
        "SampleAfterValue": "200003",
        "BriefDescription": "RFO requests that miss L2 cache",
        "CounterHTOff": "0,1,2,3,4,5,6,7"
    },
    {
        "PublicDescription": "Number of instruction fetches that missed the L2 cache.",
        "EventCode": "0x24",
        "Counter": "0,1,2,3",
        "UMask": "0x24",
        "EventName": "L2_RQSTS.CODE_RD_MISS",
        "SampleAfterValue": "200003",
        "BriefDescription": "L2 cache misses when fetching instructions",
        "CounterHTOff": "0,1,2,3,4,5,6,7"
    },
    {
        "PublicDescription": "Demand requests that miss L2 cache.",
        "EventCode": "0x24",
        "Counter": "0,1,2,3",
        "UMask": "0x27",
        "Errata": "HSD78",
        "EventName": "L2_RQSTS.ALL_DEMAND_MISS",
        "SampleAfterValue": "200003",
        "BriefDescription": "Demand requests that miss L2 cache",
        "CounterHTOff": "0,1,2,3,4,5,6,7"
    },
    {
        "PublicDescription": "Counts all L2 HW prefetcher requests that missed L2.",
        "EventCode": "0x24",
        "Counter": "0,1,2,3",
        "UMask": "0x30",
        "EventName": "L2_RQSTS.L2_PF_MISS",
        "SampleAfterValue": "200003",
        "BriefDescription": "L2 prefetch requests that miss L2 cache",
        "CounterHTOff": "0,1,2,3,4,5,6,7"
    },
    {
        "PublicDescription": "All requests that missed L2.",
        "EventCode": "0x24",
        "Counter": "0,1,2,3",
        "UMask": "0x3f",
        "Errata": "HSD78",
        "EventName": "L2_RQSTS.MISS",
        "SampleAfterValue": "200003",
        "BriefDescription": "All requests that miss L2 cache",
        "CounterHTOff": "0,1,2,3,4,5,6,7"
    },
    {
        "PublicDescription": "Demand data read requests that hit L2 cache.",
        "EventCode": "0x24",
        "Counter": "0,1,2,3",
        "UMask": "0x41",
        "Errata": "HSD78",
        "EventName": "L2_RQSTS.DEMAND_DATA_RD_HIT",
        "SampleAfterValue": "200003",
        "BriefDescription": "Demand Data Read requests that hit L2 cache",
        "CounterHTOff": "0,1,2,3,4,5,6,7"
    },
    {
        "PublicDescription": "Counts the number of store RFO requests that hit the L2 cache.",
        "EventCode": "0x24",
        "Counter": "0,1,2,3",
        "UMask": "0x42",
        "EventName": "L2_RQSTS.RFO_HIT",
        "SampleAfterValue": "200003",
        "BriefDescription": "RFO requests that hit L2 cache",
        "CounterHTOff": "0,1,2,3,4,5,6,7"
    },
    {
        "PublicDescription": "Number of instruction fetches that hit the L2 cache.",
        "EventCode": "0x24",
        "Counter": "0,1,2,3",
        "UMask": "0x44",
        "EventName": "L2_RQSTS.CODE_RD_HIT",
        "SampleAfterValue": "200003",
        "BriefDescription": "L2 cache hits when fetching instructions, code reads.",
        "CounterHTOff": "0,1,2,3,4,5,6,7"
    },
    {
        "PublicDescription": "Counts all L2 HW prefetcher requests that hit L2.",
        "EventCode": "0x24",
        "Counter": "0,1,2,3",
        "UMask": "0x50",
        "EventName": "L2_RQSTS.L2_PF_HIT",
        "SampleAfterValue": "200003",
        "BriefDescription": "L2 prefetch requests that hit L2 cache",
        "CounterHTOff": "0,1,2,3,4,5,6,7"
    },
    {
        "PublicDescription": "Counts any demand and L1 HW prefetch data load requests to L2.",
        "EventCode": "0x24",
        "Counter": "0,1,2,3",
        "UMask": "0xe1",
        "Errata": "HSD78",
        "EventName": "L2_RQSTS.ALL_DEMAND_DATA_RD",
        "SampleAfterValue": "200003",
        "BriefDescription": "Demand Data Read requests",
        "CounterHTOff": "0,1,2,3,4,5,6,7"
    },
    {
        "PublicDescription": "Counts all L2 store RFO requests.",
        "EventCode": "0x24",
        "Counter": "0,1,2,3",
        "UMask": "0xe2",
        "EventName": "L2_RQSTS.ALL_RFO",
        "SampleAfterValue": "200003",
        "BriefDescription": "RFO requests to L2 cache",
        "CounterHTOff": "0,1,2,3,4,5,6,7"
    },
    {
        "PublicDescription": "Counts all L2 code requests.",
        "EventCode": "0x24",
        "Counter": "0,1,2,3",
        "UMask": "0xe4",
        "EventName": "L2_RQSTS.ALL_CODE_RD",
        "SampleAfterValue": "200003",
        "BriefDescription": "L2 code requests",
        "CounterHTOff": "0,1,2,3,4,5,6,7"
    },
    {
        "PublicDescription": "Demand requests to L2 cache.",
        "EventCode": "0x24",
        "Counter": "0,1,2,3",
        "UMask": "0xe7",
        "Errata": "HSD78",
        "EventName": "L2_RQSTS.ALL_DEMAND_REFERENCES",
        "SampleAfterValue": "200003",
        "BriefDescription": "Demand requests to L2 cache",
        "CounterHTOff": "0,1,2,3,4,5,6,7"
    },
    {
        "PublicDescription": "Counts all L2 HW prefetcher requests.",
        "EventCode": "0x24",
        "Counter": "0,1,2,3",
        "UMask": "0xf8",
        "EventName": "L2_RQSTS.ALL_PF",
        "SampleAfterValue": "200003",
        "BriefDescription": "Requests from L2 hardware prefetchers",
        "CounterHTOff": "0,1,2,3,4,5,6,7"
    },
    {
        "PublicDescription": "All requests to L2 cache.",
        "EventCode": "0x24",
        "Counter": "0,1,2,3",
        "UMask": "0xff",
        "Errata": "HSD78",
        "EventName": "L2_RQSTS.REFERENCES",
        "SampleAfterValue": "200003",
        "BriefDescription": "All L2 requests",
        "CounterHTOff": "0,1,2,3,4,5,6,7"
    },
    {
        "PublicDescription": "Not rejected writebacks that hit L2 cache.",
        "EventCode": "0x27",
        "Counter": "0,1,2,3",
        "UMask": "0x50",
        "EventName": "L2_DEMAND_RQSTS.WB_HIT",
        "SampleAfterValue": "200003",
        "BriefDescription": "Not rejected writebacks that hit L2 cache",
        "CounterHTOff": "0,1,2,3,4,5,6,7"
    },
    {
        "PublicDescription": "This event counts each cache miss condition for references to the last level cache.",
        "EventCode": "0x2E",
        "Counter": "0,1,2,3",
        "UMask": "0x41",
        "EventName": "LONGEST_LAT_CACHE.MISS",
        "SampleAfterValue": "100003",
        "BriefDescription": "Core-originated cacheable demand requests missed L3",
        "CounterHTOff": "0,1,2,3,4,5,6,7"
    },
    {
        "PublicDescription": "This event counts requests originating from the core that reference a cache line in the last level cache.",
        "EventCode": "0x2E",
        "Counter": "0,1,2,3",
        "UMask": "0x4f",
        "EventName": "LONGEST_LAT_CACHE.REFERENCE",
        "SampleAfterValue": "100003",
        "BriefDescription": "Core-originated cacheable demand requests that refer to L3",
        "CounterHTOff": "0,1,2,3,4,5,6,7"
    },
    {
        "PublicDescription": "Increments the number of outstanding L1D misses every cycle. Set Cmask = 1 and Edge =1 to count occurrences.",
        "EventCode": "0x48",
        "Counter": "2",
        "UMask": "0x1",
        "EventName": "L1D_PEND_MISS.PENDING",
        "SampleAfterValue": "2000003",
        "BriefDescription": "L1D miss oustandings duration in cycles",
        "CounterHTOff": "2"
    },
    {
        "EventCode": "0x48",
        "Counter": "2",
        "UMask": "0x1",
        "EventName": "L1D_PEND_MISS.PENDING_CYCLES",
        "SampleAfterValue": "2000003",
        "BriefDescription": "Cycles with L1D load Misses outstanding.",
        "CounterMask": "1",
        "CounterHTOff": "2"
    },
    {
        "EventCode": "0x48",
        "Counter": "2",
        "UMask": "0x1",
        "AnyThread": "1",
        "EventName": "L1D_PEND_MISS.PENDING_CYCLES_ANY",
        "SampleAfterValue": "2000003",
        "BriefDescription": "Cycles with L1D load Misses outstanding from any thread on physical core.",
        "CounterMask": "1",
        "CounterHTOff": "2"
    },
    {
        "EventCode": "0x48",
        "Counter": "0,1,2,3",
        "UMask": "0x2",
        "EventName": "L1D_PEND_MISS.REQUEST_FB_FULL",
        "SampleAfterValue": "2000003",
        "BriefDescription": "Number of times a request needed a FB entry but there was no entry available for it. That is the FB unavailability was dominant reason for blocking the request. A request includes cacheable/uncacheable demands that is load, store or SW prefetch. HWP are e.",
        "CounterHTOff": "0,1,2,3,4,5,6,7"
    },
    {
        "EventCode": "0x48",
        "Counter": "0,1,2,3",
        "UMask": "0x2",
        "EventName": "L1D_PEND_MISS.FB_FULL",
        "SampleAfterValue": "2000003",
        "BriefDescription": "Cycles a demand request was blocked due to Fill Buffers inavailability.",
        "CounterMask": "1",
        "CounterHTOff": "0,1,2,3,4,5,6,7"
    },
    {
        "PublicDescription": "This event counts when new data lines are brought into the L1 Data cache, which cause other lines to be evicted from the cache.",
        "EventCode": "0x51",
        "Counter": "0,1,2,3",
        "UMask": "0x1",
        "EventName": "L1D.REPLACEMENT",
        "SampleAfterValue": "2000003",
        "BriefDescription": "L1D data line replacements",
        "CounterHTOff": "0,1,2,3,4,5,6,7"
    },
    {
        "PublicDescription": "Offcore outstanding demand data read transactions in SQ to uncore. Set Cmask=1 to count cycles.",
        "EventCode": "0x60",
        "Counter": "0,1,2,3",
        "UMask": "0x1",
        "Errata": "HSD78, HSD62, HSD61",
        "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD",
        "SampleAfterValue": "2000003",
        "BriefDescription": "Offcore outstanding Demand Data Read transactions in uncore queue.",
        "CounterHTOff": "0,1,2,3,4,5,6,7"
    },
    {
        "EventCode": "0x60",
        "Counter": "0,1,2,3",
        "UMask": "0x1",
        "Errata": "HSD78, HSD62, HSD61",
        "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_DATA_RD",
        "SampleAfterValue": "2000003",
        "BriefDescription": "Cycles when offcore outstanding Demand Data Read transactions are present in SuperQueue (SQ), queue to uncore.",
        "CounterMask": "1",
        "CounterHTOff": "0,1,2,3,4,5,6,7"
    },
    {
        "EventCode": "0x60",
        "Counter": "0,1,2,3",
        "UMask": "0x1",
        "Errata": "HSD78, HSD62, HSD61",
        "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD_GE_6",
        "SampleAfterValue": "2000003",
        "BriefDescription": "Cycles with at least 6 offcore outstanding Demand Data Read transactions in uncore queue.",
        "CounterMask": "6",
        "CounterHTOff": "0,1,2,3,4,5,6,7"
    },
    {
        "PublicDescription": "Offcore outstanding Demand code Read transactions in SQ to uncore. Set Cmask=1 to count cycles.",
        "EventCode": "0x60",
        "Counter": "0,1,2,3",
        "UMask": "0x2",
        "Errata": "HSD62, HSD61",
        "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_CODE_RD",
        "SampleAfterValue": "2000003",
        "BriefDescription": "Offcore outstanding code reads transactions in SuperQueue (SQ), queue to uncore, every cycle",
        "CounterHTOff": "0,1,2,3,4,5,6,7"
    },
    {
        "PublicDescription": "Offcore outstanding RFO store transactions in SQ to uncore. Set Cmask=1 to count cycles.",
        "EventCode": "0x60",
        "Counter": "0,1,2,3",
        "UMask": "0x4",
        "Errata": "HSD62, HSD61",
        "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_RFO",
        "SampleAfterValue": "2000003",
        "BriefDescription": "Offcore outstanding RFO store transactions in SuperQueue (SQ), queue to uncore",
        "CounterHTOff": "0,1,2,3,4,5,6,7"
    },
    {
        "EventCode": "0x60",
        "Counter": "0,1,2,3",
        "UMask": "0x4",
        "Errata": "HSD62, HSD61",
        "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO",
        "SampleAfterValue": "2000003",
        "BriefDescription": "Offcore outstanding demand rfo reads transactions in SuperQueue (SQ), queue to uncore, every cycle.",
        "CounterMask": "1",
        "CounterHTOff": "0,1,2,3,4,5,6,7"
    },
    {
        "PublicDescription": "Offcore outstanding cacheable data read transactions in SQ to uncore. Set Cmask=1 to count cycles.",
        "EventCode": "0x60",
        "Counter": "0,1,2,3",
        "UMask": "0x8",
        "Errata": "HSD62, HSD61",
        "EventName": "OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD",
        "SampleAfterValue": "2000003",
        "BriefDescription": "Offcore outstanding cacheable Core Data Read transactions in SuperQueue (SQ), queue to uncore",
        "CounterHTOff": "0,1,2,3,4,5,6,7"
    },
    {
        "EventCode": "0x60",
        "Counter": "0,1,2,3",
        "UMask": "0x8",
        "Errata": "HSD62, HSD61",
        "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD",
        "SampleAfterValue": "2000003",
        "BriefDescription": "Cycles when offcore outstanding cacheable Core Data Read transactions are present in SuperQueue (SQ), queue to uncore.",
        "CounterMask": "1",
        "CounterHTOff": "0,1,2,3,4,5,6,7"
    },
    {
        "PublicDescription": "Cycles in which the L1D is locked.",
        "EventCode": "0x63",
        "Counter": "0,1,2,3",
        "UMask": "0x2",
        "EventName": "LOCK_CYCLES.CACHE_LOCK_DURATION",
        "SampleAfterValue": "2000003",
        "BriefDescription": "Cycles when L1D is locked",
        "CounterHTOff": "0,1,2,3,4,5,6,7"
    },
    {
        "PublicDescription": "Demand data read requests sent to uncore.",
        "EventCode": "0xB0",
        "Counter": "0,1,2,3",
        "UMask": "0x1",
        "Errata": "HSD78",
        "EventName": "OFFCORE_REQUESTS.DEMAND_DATA_RD",
        "SampleAfterValue": "100003",
        "BriefDescription": "Demand Data Read requests sent to uncore",
        "CounterHTOff": "0,1,2,3,4,5,6,7"
    },
    {
        "PublicDescription": "Demand code read requests sent to uncore.",
        "EventCode": "0xB0",
        "Counter": "0,1,2,3",
        "UMask": "0x2",
        "EventName": "OFFCORE_REQUESTS.DEMAND_CODE_RD",
        "SampleAfterValue": "100003",
        "BriefDescription": "Cacheable and noncachaeble code read requests",
        "CounterHTOff": "0,1,2,3,4,5,6,7"
    },
    {
        "PublicDescription": "Demand RFO read requests sent to uncore, including regular RFOs, locks, ItoM.",
        "EventCode": "0xB0",
        "Counter": "0,1,2,3",
        "UMask": "0x4",
        "EventName": "OFFCORE_REQUESTS.DEMAND_RFO",
        "SampleAfterValue": "100003",
        "BriefDescription": "Demand RFO requests including regular RFOs, locks, ItoM",
        "CounterHTOff": "0,1,2,3,4,5,6,7"
    },
    {
        "PublicDescription": "Data read requests sent to uncore (demand and prefetch).",
        "EventCode": "0xB0",
        "Counter": "0,1,2,3",
        "UMask": "0x8",
        "EventName": "OFFCORE_REQUESTS.ALL_DATA_RD",
        "SampleAfterValue": "100003",
        "BriefDescription": "Demand and prefetch data reads",
        "CounterHTOff": "0,1,2,3,4,5,6,7"
    },
    {
        "EventCode": "0xb2",
        "Counter": "0,1,2,3",
        "UMask": "0x1",
        "EventName": "OFFCORE_REQUESTS_BUFFER.SQ_FULL",
        "SampleAfterValue": "2000003",
        "BriefDescription": "Offcore requests buffer cannot take more entries for this thread core.",
        "CounterHTOff": "0,1,2,3,4,5,6,7"
    },
    {
        "EventCode": "0xB7, 0xBB",
        "Counter": "0,1,2,3",
        "UMask": "0x1",
        "EventName": "OFFCORE_RESPONSE",
        "SampleAfterValue": "100003",
        "BriefDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
        "CounterHTOff": "0,1,2,3"
    },
    {
        "PEBS": "1",
        "EventCode": "0xD0",
        "Counter": "0,1,2,3",
        "UMask": "0x11",
        "Errata": "HSD29, HSM30",
        "EventName": "MEM_UOPS_RETIRED.STLB_MISS_LOADS",
        "SampleAfterValue": "100003",
        "BriefDescription": "Retired load uops that miss the STLB. (precise Event)",
        "CounterHTOff": "0,1,2,3",
        "Data_LA": "1"
    },
    {
        "PEBS": "1",
        "EventCode": "0xD0",
        "Counter": "0,1,2,3",
        "UMask": "0x12",
        "Errata": "HSD29, HSM30",
        "EventName": "MEM_UOPS_RETIRED.STLB_MISS_STORES",
        "SampleAfterValue": "100003",
        "BriefDescription": "Retired store uops that miss the STLB. (precise Event)",
        "CounterHTOff": "0,1,2,3",
        "Data_LA": "1",
        "L1_Hit_Indication": "1"
    },
    {
        "PEBS": "1",
        "EventCode": "0xD0",
        "Counter": "0,1,2,3",
        "UMask": "0x21",
        "Errata": "HSD76, HSD29, HSM30",
        "EventName": "MEM_UOPS_RETIRED.LOCK_LOADS",
        "SampleAfterValue": "100003",
        "BriefDescription": "Retired load uops with locked access. (precise Event)",
        "CounterHTOff": "0,1,2,3",
        "Data_LA": "1"
    },
    {
        "PEBS": "1",
        "PublicDescription": "This event counts load uops retired which had memory addresses spilt across 2 cache lines. A line split is across 64B cache-lines which may include a page split (4K). This is a precise event.",
        "EventCode": "0xD0",
        "Counter": "0,1,2,3",
        "UMask": "0x41",
        "Errata": "HSD29, HSM30",
        "EventName": "MEM_UOPS_RETIRED.SPLIT_LOADS",
        "SampleAfterValue": "100003",
        "BriefDescription": "Retired load uops that split across a cacheline boundary. (precise Event)",
        "CounterHTOff": "0,1,2,3",
        "Data_LA": "1"
    },
    {
        "PEBS": "1",
        "PublicDescription": "This event counts store uops retired which had memory addresses spilt across 2 cache lines. A line split is across 64B cache-lines which may include a page split (4K). This is a precise event.",
        "EventCode": "0xD0",
        "Counter": "0,1,2,3",
        "UMask": "0x42",
        "Errata": "HSD29, HSM30",
        "EventName": "MEM_UOPS_RETIRED.SPLIT_STORES",
        "SampleAfterValue": "100003",
        "BriefDescription": "Retired store uops that split across a cacheline boundary. (precise Event)",
        "CounterHTOff": "0,1,2,3",
        "Data_LA": "1",
        "L1_Hit_Indication": "1"
    },
    {
        "PEBS": "1",
        "EventCode": "0xD0",
        "Counter": "0,1,2,3",
        "UMask": "0x81",
        "Errata": "HSD29, HSM30",
        "EventName": "MEM_UOPS_RETIRED.ALL_LOADS",
        "SampleAfterValue": "2000003",
        "BriefDescription": "All retired load uops. (precise Event)",
        "CounterHTOff": "0,1,2,3",
        "Data_LA": "1"
    },
    {
        "PEBS": "1",
        "PublicDescription": "This event counts all store uops retired. This is a precise event.",
        "EventCode": "0xD0",
        "Counter": "0,1,2,3",
        "UMask": "0x82",
        "Errata": "HSD29, HSM30",
        "EventName": "MEM_UOPS_RETIRED.ALL_STORES",
        "SampleAfterValue": "2000003",
        "BriefDescription": "All retired store uops. (precise Event)",
        "CounterHTOff": "0,1,2,3",
        "Data_LA": "1",
        "L1_Hit_Indication": "1"
    },
    {
        "PEBS": "1",
        "EventCode": "0xD1",
        "Counter": "0,1,2,3",
        "UMask": "0x1",
        "Errata": "HSD29, HSM30",
        "EventName": "MEM_LOAD_UOPS_RETIRED.L1_HIT",
        "SampleAfterValue": "2000003",
        "BriefDescription": "Retired load uops with L1 cache hits as data sources.",
        "CounterHTOff": "0,1,2,3",
        "Data_LA": "1"
    },
    {
        "PEBS": "1",
        "EventCode": "0xD1",
        "Counter": "0,1,2,3",
        "UMask": "0x2",
        "Errata": "HSD76, HSD29, HSM30",
        "EventName": "MEM_LOAD_UOPS_RETIRED.L2_HIT",
        "SampleAfterValue": "100003",
        "BriefDescription": "Retired load uops with L2 cache hits as data sources.",
        "CounterHTOff": "0,1,2,3",
        "Data_LA": "1"
    },
    {
        "PEBS": "1",
        "PublicDescription": "This event counts retired load uops in which data sources were data hits in the L3 cache without snoops required. This does not include hardware prefetches. This is a precise event.",
        "EventCode": "0xD1",
        "Counter": "0,1,2,3",
        "UMask": "0x4",
        "Errata": "HSD74, HSD29, HSD25, HSM26, HSM30",
        "EventName": "MEM_LOAD_UOPS_RETIRED.L3_HIT",
        "SampleAfterValue": "50021",
        "BriefDescription": "Miss in last-level (L3) cache. Excludes Unknown data-source.",
        "CounterHTOff": "0,1,2,3",
        "Data_LA": "1"
    },
    {
        "PEBS": "1",
        "PublicDescription": "This event counts retired load uops in which data sources missed in the L1 cache. This does not include hardware prefetches. This is a precise event.",
        "EventCode": "0xD1",
        "Counter": "0,1,2,3",
        "UMask": "0x8",
        "Errata": "HSM30",
        "EventName": "MEM_LOAD_UOPS_RETIRED.L1_MISS",
        "SampleAfterValue": "100003",
        "BriefDescription": "Retired load uops misses in L1 cache as data sources.",
        "CounterHTOff": "0,1,2,3",
        "Data_LA": "1"
    },
    {
        "PEBS": "1",
        "EventCode": "0xD1",
        "Counter": "0,1,2,3",
        "UMask": "0x10",
        "Errata": "HSD29, HSM30",
        "EventName": "MEM_LOAD_UOPS_RETIRED.L2_MISS",
        "SampleAfterValue": "50021",
        "BriefDescription": "Retired load uops with L2 cache misses as data sources.",
        "CounterHTOff": "0,1,2,3",
        "Data_LA": "1"
    },
    {
        "PEBS": "1",
        "EventCode": "0xD1",
        "Counter": "0,1,2,3",
        "UMask": "0x20",
        "Errata": "HSD74, HSD29, HSD25, HSM26, HSM30",
        "EventName": "MEM_LOAD_UOPS_RETIRED.L3_MISS",
        "SampleAfterValue": "100003",
        "BriefDescription": "Miss in last-level (L3) cache. Excludes Unknown data-source.",
        "CounterHTOff": "0,1,2,3",
        "Data_LA": "1"
    },
    {
        "PEBS": "1",
        "EventCode": "0xD1",
        "Counter": "0,1,2,3",
        "UMask": "0x40",
        "Errata": "HSM30",
        "EventName": "MEM_LOAD_UOPS_RETIRED.HIT_LFB",
        "SampleAfterValue": "100003",
        "BriefDescription": "Retired load uops which data sources were load uops missed L1 but hit FB due to preceding miss to the same cache line with data not ready.",
        "CounterHTOff": "0,1,2,3",
        "Data_LA": "1"
    },
    {
        "PEBS": "1",
        "EventCode": "0xD2",
        "Counter": "0,1,2,3",
        "UMask": "0x1",
        "Errata": "HSD29, HSD25, HSM26, HSM30",
        "EventName": "MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_MISS",
        "SampleAfterValue": "20011",
        "BriefDescription": "Retired load uops which data sources were L3 hit and cross-core snoop missed in on-pkg core cache.",
        "CounterHTOff": "0,1,2,3",
        "Data_LA": "1"
    },
    {
        "PEBS": "1",
        "PublicDescription": "This event counts retired load uops that hit in the L3 cache, but required a cross-core snoop which resulted in a HIT in an on-pkg core cache. This does not include hardware prefetches. This is a precise event.",
        "EventCode": "0xD2",
        "Counter": "0,1,2,3",
        "UMask": "0x2",
        "Errata": "HSD29, HSD25, HSM26, HSM30",
        "EventName": "MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HIT",
        "SampleAfterValue": "20011",
        "BriefDescription": "Retired load uops which data sources were L3 and cross-core snoop hits in on-pkg core cache. ",
        "CounterHTOff": "0,1,2,3",
        "Data_LA": "1"
    },
    {
        "PEBS": "1",
        "PublicDescription": "This event counts retired load uops that hit in the L3 cache, but required a cross-core snoop which resulted in a HITM (hit modified) in an on-pkg core cache. This does not include hardware prefetches. This is a precise event.",
        "EventCode": "0xD2",
        "Counter": "0,1,2,3",
        "UMask": "0x4",
        "Errata": "HSD29, HSD25, HSM26, HSM30",
        "EventName": "MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HITM",
        "SampleAfterValue": "20011",
        "BriefDescription": "Retired load uops which data sources were HitM responses from shared L3. ",
        "CounterHTOff": "0,1,2,3",
        "Data_LA": "1"
    },
    {
        "PEBS": "1",
        "EventCode": "0xD2",
        "Counter": "0,1,2,3",
        "UMask": "0x8",
        "Errata": "HSD74, HSD29, HSD25, HSM26, HSM30",
        "EventName": "MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_NONE",
        "SampleAfterValue": "100003",
        "BriefDescription": "Retired load uops which data sources were hits in L3 without snoops required.",
        "CounterHTOff": "0,1,2,3",
        "Data_LA": "1"
    },
    {
        "PEBS": "1",
        "PublicDescription": "This event counts retired load uops where the data came from local DRAM. This does not include hardware prefetches. This is a precise event.",
        "EventCode": "0xD3",
        "Counter": "0,1,2,3",
        "UMask": "0x1",
        "Errata": "HSD74, HSD29, HSD25, HSM30",
        "EventName": "MEM_LOAD_UOPS_L3_MISS_RETIRED.LOCAL_DRAM",
        "SampleAfterValue": "100003",
        "CounterHTOff": "0,1,2,3",
        "Data_LA": "1"
    },
    {
        "PublicDescription": "Demand data read requests that access L2 cache.",
        "EventCode": "0xf0",
        "Counter": "0,1,2,3",
        "UMask": "0x1",
        "EventName": "L2_TRANS.DEMAND_DATA_RD",
        "SampleAfterValue": "200003",
        "BriefDescription": "Demand Data Read requests that access L2 cache",
        "CounterHTOff": "0,1,2,3,4,5,6,7"
    },
    {
        "PublicDescription": "RFO requests that access L2 cache.",
        "EventCode": "0xf0",
        "Counter": "0,1,2,3",
        "UMask": "0x2",
        "EventName": "L2_TRANS.RFO",
        "SampleAfterValue": "200003",
        "BriefDescription": "RFO requests that access L2 cache",
        "CounterHTOff": "0,1,2,3,4,5,6,7"
    },
    {
        "PublicDescription": "L2 cache accesses when fetching instructions.",
        "EventCode": "0xf0",
        "Counter": "0,1,2,3",
        "UMask": "0x4",
        "EventName": "L2_TRANS.CODE_RD",
        "SampleAfterValue": "200003",
        "BriefDescription": "L2 cache accesses when fetching instructions",
        "CounterHTOff": "0,1,2,3,4,5,6,7"
    },
    {
        "PublicDescription": "Any MLC or L3 HW prefetch accessing L2, including rejects.",
        "EventCode": "0xf0",
        "Counter": "0,1,2,3",
        "UMask": "0x8",
        "EventName": "L2_TRANS.ALL_PF",
        "SampleAfterValue": "200003",
        "BriefDescription": "L2 or L3 HW prefetches that access L2 cache",
        "CounterHTOff": "0,1,2,3,4,5,6,7"
    },
    {
        "PublicDescription": "L1D writebacks that access L2 cache.",
        "EventCode": "0xf0",
        "Counter": "0,1,2,3",
        "UMask": "0x10",
        "EventName": "L2_TRANS.L1D_WB",
        "SampleAfterValue": "200003",
        "BriefDescription": "L1D writebacks that access L2 cache",
        "CounterHTOff": "0,1,2,3,4,5,6,7"
    },
    {
        "PublicDescription": "L2 fill requests that access L2 cache.",
        "EventCode": "0xf0",
        "Counter": "0,1,2,3",
        "UMask": "0x20",
        "EventName": "L2_TRANS.L2_FILL",
        "SampleAfterValue": "200003",
        "BriefDescription": "L2 fill requests that access L2 cache",
        "CounterHTOff": "0,1,2,3,4,5,6,7"
    },
    {
        "PublicDescription": "L2 writebacks that access L2 cache.",
        "EventCode": "0xf0",
        "Counter": "0,1,2,3",
        "UMask": "0x40",
        "EventName": "L2_TRANS.L2_WB",
        "SampleAfterValue": "200003",
        "BriefDescription": "L2 writebacks that access L2 cache",
        "CounterHTOff": "0,1,2,3,4,5,6,7"
    },
    {
        "PublicDescription": "Transactions accessing L2 pipe.",
        "EventCode": "0xf0",
        "Counter": "0,1,2,3",
        "UMask": "0x80",
        "EventName": "L2_TRANS.ALL_REQUESTS",
        "SampleAfterValue": "200003",
        "BriefDescription": "Transactions accessing L2 pipe",
        "CounterHTOff": "0,1,2,3,4,5,6,7"
    },
    {
        "PublicDescription": "L2 cache lines in I state filling L2.",
        "EventCode": "0xF1",
        "Counter": "0,1,2,3",
        "UMask": "0x1",
        "EventName": "L2_LINES_IN.I",
        "SampleAfterValue": "100003",
        "BriefDescription": "L2 cache lines in I state filling L2",
        "CounterHTOff": "0,1,2,3,4,5,6,7"
    },
    {
        "PublicDescription": "L2 cache lines in S state filling L2.",
        "EventCode": "0xF1",
        "Counter": "0,1,2,3",
        "UMask": "0x2",
        "EventName": "L2_LINES_IN.S",
        "SampleAfterValue": "100003",
        "BriefDescription": "L2 cache lines in S state filling L2",
        "CounterHTOff": "0,1,2,3,4,5,6,7"
    },
    {
        "PublicDescription": "L2 cache lines in E state filling L2.",
        "EventCode": "0xF1",
        "Counter": "0,1,2,3",
        "UMask": "0x4",
        "EventName": "L2_LINES_IN.E",
        "SampleAfterValue": "100003",
        "BriefDescription": "L2 cache lines in E state filling L2",
        "CounterHTOff": "0,1,2,3,4,5,6,7"
    },
    {
        "PublicDescription": "This event counts the number of L2 cache lines brought into the L2 cache.  Lines are filled into the L2 cache when there was an L2 miss.",
        "EventCode": "0xF1",
        "Counter": "0,1,2,3",
        "UMask": "0x7",
        "EventName": "L2_LINES_IN.ALL",
        "SampleAfterValue": "100003",
        "BriefDescription": "L2 cache lines filling L2",
        "CounterHTOff": "0,1,2,3,4,5,6,7"
    },
    {
        "PublicDescription": "Clean L2 cache lines evicted by demand.",
        "EventCode": "0xF2",
        "Counter": "0,1,2,3",
        "UMask": "0x5",
        "EventName": "L2_LINES_OUT.DEMAND_CLEAN",
        "SampleAfterValue": "100003",
        "BriefDescription": "Clean L2 cache lines evicted by demand",
        "CounterHTOff": "0,1,2,3,4,5,6,7"
    },
    {
        "PublicDescription": "Dirty L2 cache lines evicted by demand.",
        "EventCode": "0xF2",
        "Counter": "0,1,2,3",
        "UMask": "0x6",
        "EventName": "L2_LINES_OUT.DEMAND_DIRTY",
        "SampleAfterValue": "100003",
        "BriefDescription": "Dirty L2 cache lines evicted by demand",
        "CounterHTOff": "0,1,2,3,4,5,6,7"
    },
    {
        "PublicDescription": "",
        "EventCode": "0xf4",
        "Counter": "0,1,2,3",
        "UMask": "0x10",
        "EventName": "SQ_MISC.SPLIT_LOCK",
        "SampleAfterValue": "100003",
        "BriefDescription": "Split locks in SQ",
        "CounterHTOff": "0,1,2,3,4,5,6,7"
    },
    {
        "PublicDescription": "Counts all requests that hit in the L3 Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
        "EventCode": "0xB7, 0xBB",
        "MSRValue": "0x3f803c8fff",
        "Counter": "0,1,2,3",
        "UMask": "0x1",
        "EventName": "OFFCORE_RESPONSE.ALL_REQUESTS.L3_HIT.ANY_RESPONSE",
        "MSRIndex": "0x1a6,0x1a7",
        "SampleAfterValue": "100003",
        "BriefDescription": "Counts all requests that hit in the L3",
        "Offcore": "1",
        "CounterHTOff": "0,1,2,3"
    },
    {
        "PublicDescription": "Counts all data/code/rfo reads (demand & prefetch) that hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
        "EventCode": "0xB7, 0xBB",
        "MSRValue": "0x10003c07f7",
        "Counter": "0,1,2,3",
        "UMask": "0x1",
        "EventName": "OFFCORE_RESPONSE.ALL_READS.L3_HIT.HITM_OTHER_CORE",
        "MSRIndex": "0x1a6,0x1a7",
        "SampleAfterValue": "100003",
        "BriefDescription": "Counts all data/code/rfo reads (demand & prefetch) that hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded",
        "Offcore": "1",
        "CounterHTOff": "0,1,2,3"
    },
    {
        "PublicDescription": "Counts all data/code/rfo reads (demand & prefetch) that hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
        "EventCode": "0xB7, 0xBB",
        "MSRValue": "0x04003c07f7",
        "Counter": "0,1,2,3",
        "UMask": "0x1",
        "EventName": "OFFCORE_RESPONSE.ALL_READS.L3_HIT.HIT_OTHER_CORE_NO_FWD",
        "MSRIndex": "0x1a6,0x1a7",
        "SampleAfterValue": "100003",
        "BriefDescription": "Counts all data/code/rfo reads (demand & prefetch) that hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded",
        "Offcore": "1",
        "CounterHTOff": "0,1,2,3"
    },
    {
        "PublicDescription": "Counts all demand & prefetch code reads that hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
        "EventCode": "0xB7, 0xBB",
        "MSRValue": "0x04003c0244",
        "Counter": "0,1,2,3",
        "UMask": "0x1",
        "EventName": "OFFCORE_RESPONSE.ALL_CODE_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD",
        "MSRIndex": "0x1a6,0x1a7",
        "SampleAfterValue": "100003",
        "BriefDescription": "Counts all demand & prefetch code reads that hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded",
        "Offcore": "1",
        "CounterHTOff": "0,1,2,3"
    },
    {
        "PublicDescription": "Counts all demand & prefetch RFOs that hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
        "EventCode": "0xB7, 0xBB",
        "MSRValue": "0x10003c0122",
        "Counter": "0,1,2,3",
        "UMask": "0x1",
        "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_HIT.HITM_OTHER_CORE",
        "MSRIndex": "0x1a6,0x1a7",
        "SampleAfterValue": "100003",
        "BriefDescription": "Counts all demand & prefetch RFOs that hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded",
        "Offcore": "1",
        "CounterHTOff": "0,1,2,3"
    },
    {
        "PublicDescription": "Counts all demand & prefetch RFOs that hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
        "EventCode": "0xB7, 0xBB",
        "MSRValue": "0x04003c0122",
        "Counter": "0,1,2,3",
        "UMask": "0x1",
        "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_HIT.HIT_OTHER_CORE_NO_FWD",
        "MSRIndex": "0x1a6,0x1a7",
        "SampleAfterValue": "100003",
        "BriefDescription": "Counts all demand & prefetch RFOs that hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded",
        "Offcore": "1",
        "CounterHTOff": "0,1,2,3"
    },
    {
        "PublicDescription": "Counts all demand & prefetch data reads that hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
        "EventCode": "0xB7, 0xBB",
        "MSRValue": "0x10003c0091",
        "Counter": "0,1,2,3",
        "UMask": "0x1",
        "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_HIT.HITM_OTHER_CORE",
        "MSRIndex": "0x1a6,0x1a7",
        "SampleAfterValue": "100003",
        "BriefDescription": "Counts all demand & prefetch data reads that hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded",
        "Offcore": "1",
        "CounterHTOff": "0,1,2,3"
    },
    {
        "PublicDescription": "Counts all demand & prefetch data reads that hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
        "EventCode": "0xB7, 0xBB",
        "MSRValue": "0x04003c0091",
        "Counter": "0,1,2,3",
        "UMask": "0x1",
        "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD",
        "MSRIndex": "0x1a6,0x1a7",
        "SampleAfterValue": "100003",
        "BriefDescription": "Counts all demand & prefetch data reads that hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded",
        "Offcore": "1",
        "CounterHTOff": "0,1,2,3"
    },
    {
        "PublicDescription": "Counts prefetch (that bring data to LLC only) code reads that hit in the L3 Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
        "EventCode": "0xB7, 0xBB",
        "MSRValue": "0x3f803c0200",
        "Counter": "0,1,2,3",
        "UMask": "0x1",
        "EventName": "OFFCORE_RESPONSE.PF_L3_CODE_RD.L3_HIT.ANY_RESPONSE",
        "MSRIndex": "0x1a6,0x1a7",
        "SampleAfterValue": "100003",
        "BriefDescription": "Counts prefetch (that bring data to LLC only) code reads that hit in the L3",
        "Offcore": "1",
        "CounterHTOff": "0,1,2,3"
    },
    {
        "PublicDescription": "Counts all prefetch (that bring data to LLC only) RFOs  that hit in the L3 Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
        "EventCode": "0xB7, 0xBB",
        "MSRValue": "0x3f803c0100",
        "Counter": "0,1,2,3",
        "UMask": "0x1",
        "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_HIT.ANY_RESPONSE",
        "MSRIndex": "0x1a6,0x1a7",
        "SampleAfterValue": "100003",
        "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs  that hit in the L3",
        "Offcore": "1",
        "CounterHTOff": "0,1,2,3"
    },
    {
        "PublicDescription": "Counts all prefetch (that bring data to LLC only) data reads that hit in the L3 Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
        "EventCode": "0xB7, 0xBB",
        "MSRValue": "0x3f803c0080",
        "Counter": "0,1,2,3",
        "UMask": "0x1",
        "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_HIT.ANY_RESPONSE",
        "MSRIndex": "0x1a6,0x1a7",
        "SampleAfterValue": "100003",
        "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads that hit in the L3",
        "Offcore": "1",
        "CounterHTOff": "0,1,2,3"
    },
    {
        "PublicDescription": "Counts all prefetch (that bring data to LLC only) code reads that hit in the L3 Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
        "EventCode": "0xB7, 0xBB",
        "MSRValue": "0x3f803c0040",
        "Counter": "0,1,2,3",
        "UMask": "0x1",
        "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.L3_HIT.ANY_RESPONSE",
        "MSRIndex": "0x1a6,0x1a7",
        "SampleAfterValue": "100003",
        "BriefDescription": "Counts all prefetch (that bring data to LLC only) code reads that hit in the L3",
        "Offcore": "1",
        "CounterHTOff": "0,1,2,3"
    },
    {
        "PublicDescription": "Counts all prefetch (that bring data to L2) RFOs that hit in the L3 Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
        "EventCode": "0xB7, 0xBB",
        "MSRValue": "0x3f803c0020",
        "Counter": "0,1,2,3",
        "UMask": "0x1",
        "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_HIT.ANY_RESPONSE",
        "MSRIndex": "0x1a6,0x1a7",
        "SampleAfterValue": "100003",
        "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs that hit in the L3",
        "Offcore": "1",
        "CounterHTOff": "0,1,2,3"
    },
    {
        "PublicDescription": "Counts prefetch (that bring data to L2) data reads that hit in the L3 Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
        "EventCode": "0xB7, 0xBB",
        "MSRValue": "0x3f803c0010",
        "Counter": "0,1,2,3",
        "UMask": "0x1",
        "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_HIT.ANY_RESPONSE",
        "MSRIndex": "0x1a6,0x1a7",
        "SampleAfterValue": "100003",
        "BriefDescription": "Counts prefetch (that bring data to L2) data reads that hit in the L3",
        "Offcore": "1",
        "CounterHTOff": "0,1,2,3"
    },
    {
        "PublicDescription": "Counts all demand code reads that hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
        "EventCode": "0xB7, 0xBB",
        "MSRValue": "0x10003c0004",
        "Counter": "0,1,2,3",
        "UMask": "0x1",
        "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT.HITM_OTHER_CORE",
        "MSRIndex": "0x1a6,0x1a7",
        "SampleAfterValue": "100003",
        "BriefDescription": "Counts all demand code reads that hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded",
        "Offcore": "1",
        "CounterHTOff": "0,1,2,3"
    },
    {
        "PublicDescription": "Counts all demand code reads that hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
        "EventCode": "0xB7, 0xBB",
        "MSRValue": "0x04003c0004",
        "Counter": "0,1,2,3",
        "UMask": "0x1",
        "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD",
        "MSRIndex": "0x1a6,0x1a7",
        "SampleAfterValue": "100003",
        "BriefDescription": "Counts all demand code reads that hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded",
        "Offcore": "1",
        "CounterHTOff": "0,1,2,3"
    },
    {
        "PublicDescription": "Counts all demand data writes (RFOs) that hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
        "EventCode": "0xB7, 0xBB",
        "MSRValue": "0x10003c0002",
        "Counter": "0,1,2,3",
        "UMask": "0x1",
        "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT.HITM_OTHER_CORE",
        "MSRIndex": "0x1a6,0x1a7",
        "SampleAfterValue": "100003",
        "BriefDescription": "Counts all demand data writes (RFOs) that hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded",
        "Offcore": "1",
        "CounterHTOff": "0,1,2,3"
    },
    {
        "PublicDescription": "Counts all demand data writes (RFOs) that hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
        "EventCode": "0xB7, 0xBB",
        "MSRValue": "0x04003c0002",
        "Counter": "0,1,2,3",
        "UMask": "0x1",
        "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT.HIT_OTHER_CORE_NO_FWD",
        "MSRIndex": "0x1a6,0x1a7",
        "SampleAfterValue": "100003",
        "BriefDescription": "Counts all demand data writes (RFOs) that hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded",
        "Offcore": "1",
        "CounterHTOff": "0,1,2,3"
    },
    {
        "PublicDescription": "Counts demand data reads that hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
        "EventCode": "0xB7, 0xBB",
        "MSRValue": "0x10003c0001",
        "Counter": "0,1,2,3",
        "UMask": "0x1",
        "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT.HITM_OTHER_CORE",
        "MSRIndex": "0x1a6,0x1a7",
        "SampleAfterValue": "100003",
        "BriefDescription": "Counts demand data reads that hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded",
        "Offcore": "1",
        "CounterHTOff": "0,1,2,3"
    },
    {
        "PublicDescription": "Counts demand data reads that hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
        "EventCode": "0xB7, 0xBB",
        "MSRValue": "0x04003c0001",
        "Counter": "0,1,2,3",
        "UMask": "0x1",
        "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD",
        "MSRIndex": "0x1a6,0x1a7",
        "SampleAfterValue": "100003",
        "BriefDescription": "Counts demand data reads that hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded",
        "Offcore": "1",
        "CounterHTOff": "0,1,2,3"
    }
]