[
    {
        "PublicDescription": "Counts the number of demand Data Read requests that miss L2 cache. Only not rejected loads are counted.",
        "EventCode": "0x24",
        "Counter": "0,1,2,3",
        "UMask": "0x21",
        "EventName": "L2_RQSTS.DEMAND_DATA_RD_MISS",
        "SampleAfterValue": "200003",
        "BriefDescription": "Demand Data Read miss L2, no rejects",
        "CounterHTOff": "0,1,2,3,4,5,6,7"
    },
    {
        "PublicDescription": "Counts the RFO (Read-for-Ownership) requests that miss L2 cache.",
        "EventCode": "0x24",
        "Counter": "0,1,2,3",
        "UMask": "0x22",
        "EventName": "L2_RQSTS.RFO_MISS",
        "SampleAfterValue": "200003",
        "BriefDescription": "RFO requests that miss L2 cache",
        "CounterHTOff": "0,1,2,3,4,5,6,7"
    },
    {
        "PublicDescription": "Counts L2 cache misses when fetching instructions.",
        "EventCode": "0x24",
        "Counter": "0,1,2,3",
        "UMask": "0x24",
        "EventName": "L2_RQSTS.CODE_RD_MISS",
        "SampleAfterValue": "200003",
        "BriefDescription": "L2 cache misses when fetching instructions",
        "CounterHTOff": "0,1,2,3,4,5,6,7"
    },
    {
        "PublicDescription": "Demand requests that miss L2 cache.",
        "EventCode": "0x24",
        "Counter": "0,1,2,3",
        "UMask": "0x27",
        "EventName": "L2_RQSTS.ALL_DEMAND_MISS",
        "SampleAfterValue": "200003",
        "BriefDescription": "Demand requests that miss L2 cache",
        "CounterHTOff": "0,1,2,3,4,5,6,7"
    },
    {
        "PublicDescription": "Counts requests from the L1/L2/L3 hardware prefetchers or Load software prefetches that miss L2 cache.",
        "EventCode": "0x24",
        "Counter": "0,1,2,3",
        "UMask": "0x38",
        "EventName": "L2_RQSTS.PF_MISS",
        "SampleAfterValue": "200003",
        "BriefDescription": "Requests from the L1/L2/L3 hardware prefetchers or Load software prefetches that miss L2 cache",
        "CounterHTOff": "0,1,2,3,4,5,6,7"
    },
    {
        "PublicDescription": "All requests that miss L2 cache.",
        "EventCode": "0x24",
        "Counter": "0,1,2,3",
        "UMask": "0x3f",
        "EventName": "L2_RQSTS.MISS",
        "SampleAfterValue": "200003",
        "BriefDescription": "All requests that miss L2 cache",
        "CounterHTOff": "0,1,2,3,4,5,6,7"
    },
    {
        "PublicDescription": "Counts the number of demand Data Read requests that hit L2 cache. Only non rejected loads are counted.",
        "EventCode": "0x24",
        "Counter": "0,1,2,3",
        "UMask": "0x41",
        "EventName": "L2_RQSTS.DEMAND_DATA_RD_HIT",
        "SampleAfterValue": "200003",
        "BriefDescription": "Demand Data Read requests that hit L2 cache",
        "CounterHTOff": "0,1,2,3,4,5,6,7"
    },
    {
        "PublicDescription": "Counts the RFO (Read-for-Ownership) requests that hit L2 cache.",
        "EventCode": "0x24",
        "Counter": "0,1,2,3",
        "UMask": "0x42",
        "EventName": "L2_RQSTS.RFO_HIT",
        "SampleAfterValue": "200003",
        "BriefDescription": "RFO requests that hit L2 cache",
        "CounterHTOff": "0,1,2,3,4,5,6,7"
    },
    {
        "PublicDescription": "Counts L2 cache hits when fetching instructions, code reads.",
        "EventCode": "0x24",
        "Counter": "0,1,2,3",
        "UMask": "0x44",
        "EventName": "L2_RQSTS.CODE_RD_HIT",
        "SampleAfterValue": "200003",
        "BriefDescription": "L2 cache hits when fetching instructions, code reads.",
        "CounterHTOff": "0,1,2,3,4,5,6,7"
    },
    {
        "PublicDescription": "Counts requests from the L1/L2/L3 hardware prefetchers or Load software prefetches that hit L2 cache.",
        "EventCode": "0x24",
        "Counter": "0,1,2,3",
        "UMask": "0xd8",
        "EventName": "L2_RQSTS.PF_HIT",
        "SampleAfterValue": "200003",
        "BriefDescription": "Requests from the L1/L2/L3 hardware prefetchers or Load software prefetches that hit L2 cache",
        "CounterHTOff": "0,1,2,3,4,5,6,7"
    },
    {
        "PublicDescription": "Counts the number of demand Data Read requests (including requests from L1D hardware prefetchers). These loads may hit or miss L2 cache. Only non rejected loads are counted.",
        "EventCode": "0x24",
        "Counter": "0,1,2,3",
        "UMask": "0xe1",
        "EventName": "L2_RQSTS.ALL_DEMAND_DATA_RD",
        "SampleAfterValue": "200003",
        "BriefDescription": "Demand Data Read requests",
        "CounterHTOff": "0,1,2,3,4,5,6,7"
    },
    {
        "PublicDescription": "Counts the total number of RFO (read for ownership) requests to L2 cache. L2 RFO requests include both L1D demand RFO misses as well as L1D RFO prefetches.",
        "EventCode": "0x24",
        "Counter": "0,1,2,3",
        "UMask": "0xe2",
        "EventName": "L2_RQSTS.ALL_RFO",
        "SampleAfterValue": "200003",
        "BriefDescription": "RFO requests to L2 cache",
        "CounterHTOff": "0,1,2,3,4,5,6,7"
    },
    {
        "PublicDescription": "Counts the total number of L2 code requests.",
        "EventCode": "0x24",
        "Counter": "0,1,2,3",
        "UMask": "0xe4",
        "EventName": "L2_RQSTS.ALL_CODE_RD",
        "SampleAfterValue": "200003",
        "BriefDescription": "L2 code requests",
        "CounterHTOff": "0,1,2,3,4,5,6,7"
    },
    {
        "PublicDescription": "Demand requests to L2 cache.",
        "EventCode": "0x24",
        "Counter": "0,1,2,3",
        "UMask": "0xe7",
        "EventName": "L2_RQSTS.ALL_DEMAND_REFERENCES",
        "SampleAfterValue": "200003",
        "BriefDescription": "Demand requests to L2 cache",
        "CounterHTOff": "0,1,2,3,4,5,6,7"
    },
    {
        "PublicDescription": "Counts the total number of requests from the L2 hardware prefetchers.",
        "EventCode": "0x24",
        "Counter": "0,1,2,3",
        "UMask": "0xf8",
        "EventName": "L2_RQSTS.ALL_PF",
        "SampleAfterValue": "200003",
        "BriefDescription": "Requests from the L1/L2/L3 hardware prefetchers or Load software prefetches",
        "CounterHTOff": "0,1,2,3,4,5,6,7"
    },
    {
        "PublicDescription": "All L2 requests.",
        "EventCode": "0x24",
        "Counter": "0,1,2,3",
        "UMask": "0xff",
        "EventName": "L2_RQSTS.REFERENCES",
        "SampleAfterValue": "200003",
        "BriefDescription": "All L2 requests",
        "CounterHTOff": "0,1,2,3,4,5,6,7"
    },
    {
        "PublicDescription": "Counts core-originated cacheable requests that miss the L3 cache (Longest Latency cache). Requests include data and code reads, Reads-for-Ownership (RFOs), speculative accesses and hardware prefetches from L1 and L2. It does not include all misses to the L3.",
        "EventCode": "0x2E",
        "Counter": "0,1,2,3",
        "UMask": "0x41",
        "Errata": "SKL057",
        "EventName": "LONGEST_LAT_CACHE.MISS",
        "SampleAfterValue": "100003",
        "BriefDescription": "Core-originated cacheable demand requests missed L3",
        "CounterHTOff": "0,1,2,3,4,5,6,7"
    },
    {
        "PublicDescription": "Counts core-originated cacheable requests to the  L3 cache (Longest Latency cache). Requests include data and code reads, Reads-for-Ownership (RFOs), speculative accesses and hardware prefetches from L1 and L2.  It does not include all accesses to the L3.",
        "EventCode": "0x2E",
        "Counter": "0,1,2,3",
        "UMask": "0x4f",
        "Errata": "SKL057",
        "EventName": "LONGEST_LAT_CACHE.REFERENCE",
        "SampleAfterValue": "100003",
        "BriefDescription": "Core-originated cacheable demand requests that refer to L3",
        "CounterHTOff": "0,1,2,3,4,5,6,7"
    },
    {
        "PublicDescription": "Counts duration of L1D miss outstanding, that is each cycle number of Fill Buffers (FB) outstanding required by Demand Reads. FB either is held by demand loads, or it is held by non-demand loads and gets hit at least once by demand. The valid outstanding interval is defined until the FB deallocation by one of the following ways: from FB allocation, if FB is allocated by demand from the demand Hit FB, if it is allocated by hardware or software prefetch.Note: In the L1D, a Demand Read contains cacheable or noncacheable demand loads, including ones causing cache-line splits and reads due to page walks resulted from any request type.",
        "EventCode": "0x48",
        "Counter": "0,1,2,3",
        "UMask": "0x1",
        "EventName": "L1D_PEND_MISS.PENDING",
        "SampleAfterValue": "2000003",
        "BriefDescription": "L1D miss outstandings duration in cycles",
        "CounterHTOff": "0,1,2,3,4,5,6,7"
    },
    {
        "PublicDescription": "Counts duration of L1D miss outstanding in cycles.",
        "EventCode": "0x48",
        "Counter": "0,1,2,3",
        "UMask": "0x1",
        "EventName": "L1D_PEND_MISS.PENDING_CYCLES",
        "SampleAfterValue": "2000003",
        "BriefDescription": "Cycles with L1D load Misses outstanding.",
        "CounterMask": "1",
        "CounterHTOff": "0,1,2,3,4,5,6,7"
    },
    {
        "EventCode": "0x48",
        "Counter": "0,1,2,3",
        "UMask": "0x1",
        "AnyThread": "1",
        "EventName": "L1D_PEND_MISS.PENDING_CYCLES_ANY",
        "SampleAfterValue": "2000003",
        "BriefDescription": "Cycles with L1D load Misses outstanding from any thread on physical core.",
        "CounterMask": "1",
        "CounterHTOff": "0,1,2,3,4,5,6,7"
    },
    {
        "PublicDescription": "Number of times a request needed a FB (Fill Buffer) entry but there was no entry available for it. A request includes cacheable/uncacheable demands that are load, store or SW prefetch instructions.",
        "EventCode": "0x48",
        "Counter": "0,1,2,3",
        "UMask": "0x2",
        "EventName": "L1D_PEND_MISS.FB_FULL",
        "SampleAfterValue": "2000003",
        "BriefDescription": "Number of times a request needed a FB entry but there was no entry available for it. That is the FB unavailability was dominant reason for blocking the request. A request includes cacheable/uncacheable demands that is load, store or SW prefetch.",
        "CounterHTOff": "0,1,2,3,4,5,6,7"
    },
    {
        "PublicDescription": "Counts L1D data line replacements including opportunistic replacements, and replacements that require stall-for-replace or block-for-replace.",
        "EventCode": "0x51",
        "Counter": "0,1,2,3",
        "UMask": "0x1",
        "EventName": "L1D.REPLACEMENT",
        "SampleAfterValue": "2000003",
        "BriefDescription": "L1D data line replacements",
        "CounterHTOff": "0,1,2,3,4,5,6,7"
    },
    {
        "PublicDescription": "Counts the number of offcore outstanding Demand Data Read transactions in the super queue (SQ) every cycle. A transaction is considered to be in the Offcore outstanding state between L2 miss and transaction completion sent to requestor. See the corresponding Umask under OFFCORE_REQUESTS.Note: A prefetch promoted to Demand is counted from the promotion point.",
        "EventCode": "0x60",
        "Counter": "0,1,2,3",
        "UMask": "0x1",
        "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD",
        "SampleAfterValue": "2000003",
        "BriefDescription": "Offcore outstanding Demand Data Read transactions in uncore queue.",
        "CounterHTOff": "0,1,2,3,4,5,6,7"
    },
    {
        "PublicDescription": "Counts cycles when offcore outstanding Demand Data Read transactions are present in the super queue (SQ). A transaction is considered to be in the Offcore outstanding state between L2 miss and transaction completion sent to requestor (SQ de-allocation).",
        "EventCode": "0x60",
        "Counter": "0,1,2,3",
        "UMask": "0x1",
        "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_DATA_RD",
        "SampleAfterValue": "2000003",
        "BriefDescription": "Cycles when offcore outstanding Demand Data Read transactions are present in SuperQueue (SQ), queue to uncore",
        "CounterMask": "1",
        "CounterHTOff": "0,1,2,3,4,5,6,7"
    },
    {
        "EventCode": "0x60",
        "Counter": "0,1,2,3",
        "UMask": "0x1",
        "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD_GE_6",
        "SampleAfterValue": "2000003",
        "BriefDescription": "Cycles with at least 6 offcore outstanding Demand Data Read transactions in uncore queue.",
        "CounterMask": "6",
        "CounterHTOff": "0,1,2,3,4,5,6,7"
    },
    {
        "PublicDescription": "Counts the number of offcore outstanding Code Reads transactions in the super queue every cycle. The 'Offcore outstanding' state of the transaction lasts from the L2 miss until the sending transaction completion to requestor (SQ deallocation). See the corresponding Umask under OFFCORE_REQUESTS.",
        "EventCode": "0x60",
        "Counter": "0,1,2,3",
        "UMask": "0x2",
        "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_CODE_RD",
        "SampleAfterValue": "2000003",
        "BriefDescription": "Offcore outstanding Code Reads transactions in the SuperQueue (SQ), queue to uncore, every cycle.",
        "CounterHTOff": "0,1,2,3,4,5,6,7"
    },
    {
        "PublicDescription": "Counts the number of offcore outstanding Code Reads transactions in the super queue every cycle. The 'Offcore outstanding' state of the transaction lasts from the L2 miss until the sending transaction completion to requestor (SQ deallocation). See the corresponding Umask under OFFCORE_REQUESTS.",
        "EventCode": "0x60",
        "Counter": "0,1,2,3",
        "UMask": "0x2",
        "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_CODE_RD",
        "SampleAfterValue": "2000003",
        "BriefDescription": "Cycles with offcore outstanding Code Reads transactions in the SuperQueue (SQ), queue to uncore.",
        "CounterMask": "1",
        "CounterHTOff": "0,1,2,3,4,5,6,7"
    },
    {
        "PublicDescription": "Counts the number of offcore outstanding RFO (store) transactions in the super queue (SQ) every cycle. A transaction is considered to be in the Offcore outstanding state between L2 miss and transaction completion sent to requestor (SQ de-allocation). See corresponding Umask under OFFCORE_REQUESTS.",
        "EventCode": "0x60",
        "Counter": "0,1,2,3",
        "UMask": "0x4",
        "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_RFO",
        "SampleAfterValue": "2000003",
        "BriefDescription": "Offcore outstanding demand rfo reads transactions in SuperQueue (SQ), queue to uncore, every cycle",
        "CounterHTOff": "0,1,2,3,4,5,6,7"
    },
    {
        "PublicDescription": "Counts the number of offcore outstanding demand rfo Reads transactions in the super queue every cycle. The 'Offcore outstanding' state of the transaction lasts from the L2 miss until the sending transaction completion to requestor (SQ deallocation). See the corresponding Umask under OFFCORE_REQUESTS.",
        "EventCode": "0x60",
        "Counter": "0,1,2,3",
        "UMask": "0x4",
        "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO",
        "SampleAfterValue": "2000003",
        "BriefDescription": "Cycles with offcore outstanding demand rfo reads transactions in SuperQueue (SQ), queue to uncore.",
        "CounterMask": "1",
        "CounterHTOff": "0,1,2,3,4,5,6,7"
    },
    {
        "PublicDescription": "Counts the number of offcore outstanding cacheable Core Data Read transactions in the super queue every cycle. A transaction is considered to be in the Offcore outstanding state between L2 miss and transaction completion sent to requestor (SQ de-allocation). See corresponding Umask under OFFCORE_REQUESTS.",
        "EventCode": "0x60",
        "Counter": "0,1,2,3",
        "UMask": "0x8",
        "EventName": "OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD",
        "SampleAfterValue": "2000003",
        "BriefDescription": "Offcore outstanding cacheable Core Data Read transactions in SuperQueue (SQ), queue to uncore",
        "CounterHTOff": "0,1,2,3,4,5,6,7"
    },
    {
        "PublicDescription": "Counts cycles when offcore outstanding cacheable Core Data Read transactions are present in the super queue. A transaction is considered to be in the Offcore outstanding state between L2 miss and transaction completion sent to requestor (SQ de-allocation). See corresponding Umask under OFFCORE_REQUESTS.",
        "EventCode": "0x60",
        "Counter": "0,1,2,3",
        "UMask": "0x8",
        "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD",
        "SampleAfterValue": "2000003",
        "BriefDescription": "Cycles when offcore outstanding cacheable Core Data Read transactions are present in SuperQueue (SQ), queue to uncore.",
        "CounterMask": "1",
        "CounterHTOff": "0,1,2,3,4,5,6,7"
    },
    {
        "PublicDescription": "Counts the Demand Data Read requests sent to uncore. Use it in conjunction with OFFCORE_REQUESTS_OUTSTANDING to determine average latency in the uncore.",
        "EventCode": "0xB0",
        "Counter": "0,1,2,3",
        "UMask": "0x1",
        "EventName": "OFFCORE_REQUESTS.DEMAND_DATA_RD",
        "SampleAfterValue": "100003",
        "BriefDescription": "Demand Data Read requests sent to uncore",
        "CounterHTOff": "0,1,2,3,4,5,6,7"
    },
    {
        "PublicDescription": "Counts both cacheable and non-cacheable code read requests.",
        "EventCode": "0xB0",
        "Counter": "0,1,2,3",
        "UMask": "0x2",
        "EventName": "OFFCORE_REQUESTS.DEMAND_CODE_RD",
        "SampleAfterValue": "100003",
        "BriefDescription": "Cacheable and noncachaeble code read requests",
        "CounterHTOff": "0,1,2,3,4,5,6,7"
    },
    {
        "PublicDescription": "Counts the demand RFO (read for ownership) requests including regular RFOs, locks, ItoM.",
        "EventCode": "0xB0",
        "Counter": "0,1,2,3",
        "UMask": "0x4",
        "EventName": "OFFCORE_REQUESTS.DEMAND_RFO",
        "SampleAfterValue": "100003",
        "BriefDescription": "Demand RFO requests including regular RFOs, locks, ItoM",
        "CounterHTOff": "0,1,2,3,4,5,6,7"
    },
    {
        "PublicDescription": "Counts the demand and prefetch data reads. All Core Data Reads include cacheable 'Demands' and L2 prefetchers (not L3 prefetchers). Counting also covers reads due to page walks resulted from any request type.",
        "EventCode": "0xB0",
        "Counter": "0,1,2,3",
        "UMask": "0x8",
        "EventName": "OFFCORE_REQUESTS.ALL_DATA_RD",
        "SampleAfterValue": "100003",
        "BriefDescription": "Demand and prefetch data reads",
        "CounterHTOff": "0,1,2,3,4,5,6,7"
    },
    {
        "PublicDescription": "Counts memory transactions reached the super queue including requests initiated by the core, all L3 prefetches, page walks, etc..",
        "EventCode": "0xB0",
        "Counter": "0,1,2,3",
        "UMask": "0x80",
        "EventName": "OFFCORE_REQUESTS.ALL_REQUESTS",
        "SampleAfterValue": "100003",
        "BriefDescription": "Any memory transaction that reached the SQ.",
        "CounterHTOff": "0,1,2,3,4,5,6,7"
    },
    {
        "PublicDescription": "Counts the number of cases when the offcore requests buffer cannot take more entries for the core. This can happen when the superqueue does not contain eligible entries, or when L1D writeback pending FIFO requests is full.Note: Writeback pending FIFO has six entries.",
        "EventCode": "0xB2",
        "Counter": "0,1,2,3",
        "UMask": "0x1",
        "EventName": "OFFCORE_REQUESTS_BUFFER.SQ_FULL",
        "SampleAfterValue": "2000003",
        "BriefDescription": "Offcore requests buffer cannot take more entries for this thread core.",
        "CounterHTOff": "0,1,2,3,4,5,6,7"
    },
    {
        "PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
        "EventCode": "0xB7, 0xBB",
        "Counter": "0,1,2,3",
        "UMask": "0x1",
        "EventName": "OFFCORE_RESPONSE",
        "SampleAfterValue": "100003",
        "BriefDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction",
        "CounterHTOff": "0,1,2,3"
    },
    {
        "PEBS": "1",
        "PublicDescription": "Retired load instructions that miss the STLB.",
        "EventCode": "0xD0",
        "Counter": "0,1,2,3",
        "UMask": "0x11",
        "EventName": "MEM_INST_RETIRED.STLB_MISS_LOADS",
        "SampleAfterValue": "100003",
        "BriefDescription": "Retired load instructions that miss the STLB. (Precise Event)",
        "CounterHTOff": "0,1,2,3",
        "Data_LA": "1"
    },
    {
        "PEBS": "1",
        "PublicDescription": "Retired store instructions that miss the STLB.",
        "EventCode": "0xD0",
        "Counter": "0,1,2,3",
        "UMask": "0x12",
        "EventName": "MEM_INST_RETIRED.STLB_MISS_STORES",
        "SampleAfterValue": "100003",
        "BriefDescription": "Retired store instructions that miss the STLB. (Precise Event)",
        "CounterHTOff": "0,1,2,3",
        "Data_LA": "1",
        "L1_Hit_Indication": "1"
    },
    {
        "PEBS": "1",
        "EventCode": "0xD0",
        "Counter": "0,1,2,3",
        "UMask": "0x21",
        "EventName": "MEM_INST_RETIRED.LOCK_LOADS",
        "SampleAfterValue": "100007",
        "BriefDescription": "Retired load instructions with locked access. (Precise Event)",
        "CounterHTOff": "0,1,2,3",
        "Data_LA": "1"
    },
    {
        "PEBS": "1",
        "EventCode": "0xD0",
        "Counter": "0,1,2,3",
        "UMask": "0x41",
        "EventName": "MEM_INST_RETIRED.SPLIT_LOADS",
        "SampleAfterValue": "100003",
        "BriefDescription": "Retired load instructions that split across a cacheline boundary. (Precise Event)",
        "CounterHTOff": "0,1,2,3",
        "Data_LA": "1"
    },
    {
        "PEBS": "1",
        "EventCode": "0xD0",
        "Counter": "0,1,2,3",
        "UMask": "0x42",
        "EventName": "MEM_INST_RETIRED.SPLIT_STORES",
        "SampleAfterValue": "100003",
        "BriefDescription": "Retired store instructions that split across a cacheline boundary. (Precise Event)",
        "CounterHTOff": "0,1,2,3",
        "Data_LA": "1",
        "L1_Hit_Indication": "1"
    },
    {
        "PEBS": "1",
        "EventCode": "0xD0",
        "Counter": "0,1,2,3",
        "UMask": "0x81",
        "EventName": "MEM_INST_RETIRED.ALL_LOADS",
        "SampleAfterValue": "2000003",
        "BriefDescription": "All retired load instructions. (Precise Event)",
        "CounterHTOff": "0,1,2,3",
        "Data_LA": "1"
    },
    {
        "PEBS": "1",
        "PublicDescription": "All retired store instructions.",
        "EventCode": "0xD0",
        "Counter": "0,1,2,3",
        "UMask": "0x82",
        "EventName": "MEM_INST_RETIRED.ALL_STORES",
        "SampleAfterValue": "2000003",
        "BriefDescription": "All retired store instructions. (Precise Event)",
        "CounterHTOff": "0,1,2,3",
        "Data_LA": "1",
        "L1_Hit_Indication": "1"
    },
    {
        "PEBS": "1",
        "PublicDescription": "Counts retired load instructions with at least one uop that hit in the L1 data cache. This event includes all SW prefetches and lock instructions regardless of the data source.\r\n",
        "EventCode": "0xD1",
        "Counter": "0,1,2,3",
        "UMask": "0x1",
        "EventName": "MEM_LOAD_RETIRED.L1_HIT",
        "SampleAfterValue": "2000003",
        "BriefDescription": "Retired load instructions with L1 cache hits as data sources",
        "CounterHTOff": "0,1,2,3",
        "Data_LA": "1"
    },
    {
        "PEBS": "1",
        "PublicDescription": "Retired load instructions with L2 cache hits as data sources.",
        "EventCode": "0xD1",
        "Counter": "0,1,2,3",
        "UMask": "0x2",
        "EventName": "MEM_LOAD_RETIRED.L2_HIT",
        "SampleAfterValue": "100003",
        "BriefDescription": "Retired load instructions with L2 cache hits as data sources",
        "CounterHTOff": "0,1,2,3",
        "Data_LA": "1"
    },
    {
        "PEBS": "1",
        "PublicDescription": "Retired load instructions with L3 cache hits as data sources.",
        "EventCode": "0xD1",
        "Counter": "0,1,2,3",
        "UMask": "0x4",
        "EventName": "MEM_LOAD_RETIRED.L3_HIT",
        "SampleAfterValue": "50021",
        "BriefDescription": "Retired load instructions with L3 cache hits as data sources",
        "CounterHTOff": "0,1,2,3",
        "Data_LA": "1"
    },
    {
        "PEBS": "1",
        "PublicDescription": "Counts retired load instructions with at least one uop that missed in the L1 cache.",
        "EventCode": "0xD1",
        "Counter": "0,1,2,3",
        "UMask": "0x8",
        "EventName": "MEM_LOAD_RETIRED.L1_MISS",
        "SampleAfterValue": "100003",
        "BriefDescription": "Retired load instructions missed L1 cache as data sources",
        "CounterHTOff": "0,1,2,3",
        "Data_LA": "1"
    },
    {
        "PEBS": "1",
        "PublicDescription": "Retired load instructions missed L2 cache as data sources.",
        "EventCode": "0xD1",
        "Counter": "0,1,2,3",
        "UMask": "0x10",
        "EventName": "MEM_LOAD_RETIRED.L2_MISS",
        "SampleAfterValue": "50021",
        "BriefDescription": "Retired load instructions missed L2 cache as data sources",
        "CounterHTOff": "0,1,2,3",
        "Data_LA": "1"
    },
    {
        "PEBS": "1",
        "PublicDescription": "Retired load instructions missed L3 cache as data sources.",
        "EventCode": "0xD1",
        "Counter": "0,1,2,3",
        "UMask": "0x20",
        "EventName": "MEM_LOAD_RETIRED.L3_MISS",
        "SampleAfterValue": "100007",
        "BriefDescription": "Retired load instructions missed L3 cache as data sources",
        "CounterHTOff": "0,1,2,3",
        "Data_LA": "1"
    },
    {
        "PEBS": "1",
        "PublicDescription": "Counts retired load instructions with at least one uop was load missed in L1 but hit FB (Fill Buffers) due to preceding miss to the same cache line with data not ready. \r\n",
        "EventCode": "0xD1",
        "Counter": "0,1,2,3",
        "UMask": "0x40",
        "EventName": "MEM_LOAD_RETIRED.FB_HIT",
        "SampleAfterValue": "100007",
        "BriefDescription": "Retired load instructions which data sources were load missed L1 but hit FB due to preceding miss to the same cache line with data not ready",
        "CounterHTOff": "0,1,2,3",
        "Data_LA": "1"
    },
    {
        "PEBS": "1",
        "EventCode": "0xD2",
        "Counter": "0,1,2,3",
        "UMask": "0x1",
        "EventName": "MEM_LOAD_L3_HIT_RETIRED.XSNP_MISS",
        "SampleAfterValue": "20011",
        "BriefDescription": "Retired load instructions which data sources were L3 hit and cross-core snoop missed in on-pkg core cache.",
        "CounterHTOff": "0,1,2,3",
        "Data_LA": "1"
    },
    {
        "PEBS": "1",
        "PublicDescription": "Retired load instructions which data sources were L3 and cross-core snoop hits in on-pkg core cache.",
        "EventCode": "0xD2",
        "Counter": "0,1,2,3",
        "UMask": "0x2",
        "EventName": "MEM_LOAD_L3_HIT_RETIRED.XSNP_HIT",
        "SampleAfterValue": "20011",
        "BriefDescription": "Retired load instructions which data sources were L3 and cross-core snoop hits in on-pkg core cache",
        "CounterHTOff": "0,1,2,3",
        "Data_LA": "1"
    },
    {
        "PEBS": "1",
        "PublicDescription": "Retired load instructions which data sources were HitM responses from shared L3.",
        "EventCode": "0xD2",
        "Counter": "0,1,2,3",
        "UMask": "0x4",
        "EventName": "MEM_LOAD_L3_HIT_RETIRED.XSNP_HITM",
        "SampleAfterValue": "20011",
        "BriefDescription": "Retired load instructions which data sources were HitM responses from shared L3",
        "CounterHTOff": "0,1,2,3",
        "Data_LA": "1"
    },
    {
        "PEBS": "1",
        "PublicDescription": "Retired load instructions which data sources were hits in L3 without snoops required.",
        "EventCode": "0xD2",
        "Counter": "0,1,2,3",
        "UMask": "0x8",
        "EventName": "MEM_LOAD_L3_HIT_RETIRED.XSNP_NONE",
        "SampleAfterValue": "100003",
        "BriefDescription": "Retired load instructions which data sources were hits in L3 without snoops required",
        "CounterHTOff": "0,1,2,3",
        "Data_LA": "1"
    },
    {
        "PEBS": "1",
        "EventCode": "0xD4",
        "Counter": "0,1,2,3",
        "UMask": "0x4",
        "EventName": "MEM_LOAD_MISC_RETIRED.UC",
        "SampleAfterValue": "100007",
        "BriefDescription": "Retired instructions with at least 1 uncacheable load or lock.",
        "CounterHTOff": "0,1,2,3",
        "Data_LA": "1"
    },
    {
        "PublicDescription": "Counts L2 writebacks that access L2 cache.",
        "EventCode": "0xF0",
        "Counter": "0,1,2,3",
        "UMask": "0x40",
        "EventName": "L2_TRANS.L2_WB",
        "SampleAfterValue": "200003",
        "BriefDescription": "L2 writebacks that access L2 cache",
        "CounterHTOff": "0,1,2,3,4,5,6,7"
    },
    {
        "PublicDescription": "Counts the number of L2 cache lines filling the L2. Counting does not cover rejects.",
        "EventCode": "0xF1",
        "Counter": "0,1,2,3",
        "UMask": "0x1f",
        "EventName": "L2_LINES_IN.ALL",
        "SampleAfterValue": "100003",
        "BriefDescription": "L2 cache lines filling L2",
        "CounterHTOff": "0,1,2,3,4,5,6,7"
    },
    {
        "EventCode": "0xF2",
        "Counter": "0,1,2,3",
        "UMask": "0x1",
        "EventName": "L2_LINES_OUT.SILENT",
        "SampleAfterValue": "200003",
        "BriefDescription": "Counts the number of lines that are silently dropped by L2 cache when triggered by an L2 cache fill. These lines are typically in Shared or Exclusive state. A non-threaded event.",
        "CounterHTOff": "0,1,2,3,4,5,6,7"
    },
    {
        "EventCode": "0xF2",
        "Counter": "0,1,2,3",
        "UMask": "0x2",
        "EventName": "L2_LINES_OUT.NON_SILENT",
        "SampleAfterValue": "200003",
        "BriefDescription": "Counts the number of lines that are evicted by L2 cache when triggered by an L2 cache fill. Those lines are in Modified state. Modified lines are written back to L3",
        "CounterHTOff": "0,1,2,3,4,5,6,7"
    },
    {
        "PublicDescription": "Counts the number of lines that have been hardware prefetched but not used and now evicted by L2 cache.",
        "EventCode": "0xF2",
        "Counter": "0,1,2,3",
        "UMask": "0x4",
        "EventName": "L2_LINES_OUT.USELESS_PREF",
        "SampleAfterValue": "200003",
        "BriefDescription": "Counts the number of lines that have been hardware prefetched but not used and now evicted by L2 cache",
        "CounterHTOff": "0,1,2,3,4,5,6,7"
    },
    {
        "EventCode": "0xF2",
        "Counter": "0,1,2,3",
        "UMask": "0x4",
        "EventName": "L2_LINES_OUT.USELESS_HWPF",
        "SampleAfterValue": "200003",
        "BriefDescription": "Counts the number of lines that have been hardware prefetched but not used and now evicted by L2 cache",
        "CounterHTOff": "0,1,2,3,4,5,6,7"
    },
    {
        "PublicDescription": "Counts the number of cache line split locks sent to the uncore.",
        "EventCode": "0xF4",
        "Counter": "0,1,2,3",
        "UMask": "0x10",
        "EventName": "SQ_MISC.SPLIT_LOCK",
        "SampleAfterValue": "100003",
        "BriefDescription": "Number of cache line split locks sent to uncore.",
        "CounterHTOff": "0,1,2,3,4,5,6,7"
    },
    {
        "PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
        "EventCode": "0xB7, 0xBB",
        "MSRValue": "0x3fc0400001 ",
        "Counter": "0,1,2,3",
        "UMask": "0x1",
        "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L4_HIT_LOCAL_L4.ANY_SNOOP",
        "MSRIndex": "0x1a6,0x1a7",
        "SampleAfterValue": "100003",
        "BriefDescription": "DEMAND_DATA_RD & L4_HIT_LOCAL_L4 & ANY_SNOOP",
        "Offcore": "1",
        "CounterHTOff": "0,1,2,3"
    },
    {
        "PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
        "EventCode": "0xB7, 0xBB",
        "MSRValue": "0x1000400001 ",
        "Counter": "0,1,2,3",
        "UMask": "0x1",
        "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L4_HIT_LOCAL_L4.SNOOP_HITM",
        "MSRIndex": "0x1a6,0x1a7",
        "SampleAfterValue": "100003",
        "BriefDescription": "DEMAND_DATA_RD & L4_HIT_LOCAL_L4 & SNOOP_HITM",
        "Offcore": "1",
        "CounterHTOff": "0,1,2,3"
    },
    {
        "PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
        "EventCode": "0xB7, 0xBB",
        "MSRValue": "0x0400400001 ",
        "Counter": "0,1,2,3",
        "UMask": "0x1",
        "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L4_HIT_LOCAL_L4.SNOOP_HIT_NO_FWD",
        "MSRIndex": "0x1a6,0x1a7",
        "SampleAfterValue": "100003",
        "BriefDescription": "DEMAND_DATA_RD & L4_HIT_LOCAL_L4 & SNOOP_HIT_NO_FWD",
        "Offcore": "1",
        "CounterHTOff": "0,1,2,3"
    },
    {
        "PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
        "EventCode": "0xB7, 0xBB",
        "MSRValue": "0x0200400001 ",
        "Counter": "0,1,2,3",
        "UMask": "0x1",
        "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L4_HIT_LOCAL_L4.SNOOP_MISS",
        "MSRIndex": "0x1a6,0x1a7",
        "SampleAfterValue": "100003",
        "BriefDescription": "DEMAND_DATA_RD & L4_HIT_LOCAL_L4 & SNOOP_MISS",
        "Offcore": "1",
        "CounterHTOff": "0,1,2,3"
    },
    {
        "PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
        "EventCode": "0xB7, 0xBB",
        "MSRValue": "0x0100400001 ",
        "Counter": "0,1,2,3",
        "UMask": "0x1",
        "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L4_HIT_LOCAL_L4.SNOOP_NOT_NEEDED",
        "MSRIndex": "0x1a6,0x1a7",
        "SampleAfterValue": "100003",
        "BriefDescription": "DEMAND_DATA_RD & L4_HIT_LOCAL_L4 & SNOOP_NOT_NEEDED",
        "Offcore": "1",
        "CounterHTOff": "0,1,2,3"
    },
    {
        "PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
        "EventCode": "0xB7, 0xBB",
        "MSRValue": "0x0080400001 ",
        "Counter": "0,1,2,3",
        "UMask": "0x1",
        "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L4_HIT_LOCAL_L4.SNOOP_NONE",
        "MSRIndex": "0x1a6,0x1a7",
        "SampleAfterValue": "100003",
        "BriefDescription": "DEMAND_DATA_RD & L4_HIT_LOCAL_L4 & SNOOP_NONE",
        "Offcore": "1",
        "CounterHTOff": "0,1,2,3"
    },
    {
        "PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
        "EventCode": "0xB7, 0xBB",
        "MSRValue": "0x3fc01c0001 ",
        "Counter": "0,1,2,3",
        "UMask": "0x1",
        "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT.ANY_SNOOP",
        "MSRIndex": "0x1a6,0x1a7",
        "SampleAfterValue": "100003",
        "BriefDescription": "DEMAND_DATA_RD & L3_HIT & ANY_SNOOP",
        "Offcore": "1",
        "CounterHTOff": "0,1,2,3"
    },
    {
        "PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
        "EventCode": "0xB7, 0xBB",
        "MSRValue": "0x10001c0001 ",
        "Counter": "0,1,2,3",
        "UMask": "0x1",
        "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM",
        "MSRIndex": "0x1a6,0x1a7",
        "SampleAfterValue": "100003",
        "BriefDescription": "DEMAND_DATA_RD & L3_HIT & SNOOP_HITM",
        "Offcore": "1",
        "CounterHTOff": "0,1,2,3"
    },
    {
        "PublicDescription": "Counts demand data reads that hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded. Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
        "EventCode": "0xB7, 0xBB",
        "MSRValue": "0x04001c0001 ",
        "Counter": "0,1,2,3",
        "UMask": "0x1",
        "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_NO_FWD",
        "MSRIndex": "0x1a6,0x1a7",
        "SampleAfterValue": "100003",
        "BriefDescription": "Counts demand data reads that hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded.",
        "Offcore": "1",
        "CounterHTOff": "0,1,2,3"
    },
    {
        "PublicDescription": "Counts demand data reads that hit in the L3 and the snoops sent to sibling cores return clean response. Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
        "EventCode": "0xB7, 0xBB",
        "MSRValue": "0x02001c0001 ",
        "Counter": "0,1,2,3",
        "UMask": "0x1",
        "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT.SNOOP_MISS",
        "MSRIndex": "0x1a6,0x1a7",
        "SampleAfterValue": "100003",
        "BriefDescription": "Counts demand data reads that hit in the L3 and the snoops sent to sibling cores return clean response.",
        "Offcore": "1",
        "CounterHTOff": "0,1,2,3"
    },
    {
        "PublicDescription": "Counts demand data reads that hit in the L3 and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores. Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
        "EventCode": "0xB7, 0xBB",
        "MSRValue": "0x01001c0001 ",
        "Counter": "0,1,2,3",
        "UMask": "0x1",
        "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT.SNOOP_NOT_NEEDED",
        "MSRIndex": "0x1a6,0x1a7",
        "SampleAfterValue": "100003",
        "BriefDescription": "Counts demand data reads that hit in the L3 and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores.",
        "Offcore": "1",
        "CounterHTOff": "0,1,2,3"
    },
    {
        "PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
        "EventCode": "0xB7, 0xBB",
        "MSRValue": "0x00801c0001 ",
        "Counter": "0,1,2,3",
        "UMask": "0x1",
        "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT.SNOOP_NONE",
        "MSRIndex": "0x1a6,0x1a7",
        "SampleAfterValue": "100003",
        "BriefDescription": "DEMAND_DATA_RD & L3_HIT & SNOOP_NONE",
        "Offcore": "1",
        "CounterHTOff": "0,1,2,3"
    },
    {
        "PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
        "EventCode": "0xB7, 0xBB",
        "MSRValue": "0x3fc0020001 ",
        "Counter": "0,1,2,3",
        "UMask": "0x1",
        "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.SUPPLIER_NONE.ANY_SNOOP",
        "MSRIndex": "0x1a6,0x1a7",
        "SampleAfterValue": "100003",
        "BriefDescription": "DEMAND_DATA_RD & SUPPLIER_NONE & ANY_SNOOP",
        "Offcore": "1",
        "CounterHTOff": "0,1,2,3"
    },
    {
        "PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
        "EventCode": "0xB7, 0xBB",
        "MSRValue": "0x1000020001 ",
        "Counter": "0,1,2,3",
        "UMask": "0x1",
        "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.SUPPLIER_NONE.SNOOP_HITM",
        "MSRIndex": "0x1a6,0x1a7",
        "SampleAfterValue": "100003",
        "BriefDescription": "DEMAND_DATA_RD & SUPPLIER_NONE & SNOOP_HITM",
        "Offcore": "1",
        "CounterHTOff": "0,1,2,3"
    },
    {
        "PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
        "EventCode": "0xB7, 0xBB",
        "MSRValue": "0x0400020001 ",
        "Counter": "0,1,2,3",
        "UMask": "0x1",
        "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.SUPPLIER_NONE.SNOOP_HIT_NO_FWD",
        "MSRIndex": "0x1a6,0x1a7",
        "SampleAfterValue": "100003",
        "BriefDescription": "DEMAND_DATA_RD & SUPPLIER_NONE & SNOOP_HIT_NO_FWD",
        "Offcore": "1",
        "CounterHTOff": "0,1,2,3"
    },
    {
        "PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
        "EventCode": "0xB7, 0xBB",
        "MSRValue": "0x0200020001 ",
        "Counter": "0,1,2,3",
        "UMask": "0x1",
        "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.SUPPLIER_NONE.SNOOP_MISS",
        "MSRIndex": "0x1a6,0x1a7",
        "SampleAfterValue": "100003",
        "BriefDescription": "DEMAND_DATA_RD & SUPPLIER_NONE & SNOOP_MISS",
        "Offcore": "1",
        "CounterHTOff": "0,1,2,3"
    },
    {
        "PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
        "EventCode": "0xB7, 0xBB",
        "MSRValue": "0x0100020001 ",
        "Counter": "0,1,2,3",
        "UMask": "0x1",
        "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.SUPPLIER_NONE.SNOOP_NOT_NEEDED",
        "MSRIndex": "0x1a6,0x1a7",
        "SampleAfterValue": "100003",
        "BriefDescription": "DEMAND_DATA_RD & SUPPLIER_NONE & SNOOP_NOT_NEEDED",
        "Offcore": "1",
        "CounterHTOff": "0,1,2,3"
    },
    {
        "PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
        "EventCode": "0xB7, 0xBB",
        "MSRValue": "0x0080020001 ",
        "Counter": "0,1,2,3",
        "UMask": "0x1",
        "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.SUPPLIER_NONE.SNOOP_NONE",
        "MSRIndex": "0x1a6,0x1a7",
        "SampleAfterValue": "100003",
        "BriefDescription": "DEMAND_DATA_RD & SUPPLIER_NONE & SNOOP_NONE",
        "Offcore": "1",
        "CounterHTOff": "0,1,2,3"
    },
    {
        "PublicDescription": "Counts demand data reads that have any response type. Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
        "EventCode": "0xB7, 0xBB",
        "MSRValue": "0x0000010001 ",
        "Counter": "0,1,2,3",
        "UMask": "0x1",
        "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.ANY_RESPONSE",
        "MSRIndex": "0x1a6,0x1a7",
        "SampleAfterValue": "100003",
        "BriefDescription": "Counts demand data reads that have any response type.",
        "Offcore": "1",
        "CounterHTOff": "0,1,2,3"
    }
]