Fix cache line size calculation.
CTR_EL0 gives the line size in 4-byte words so the lines are 4 times
larger than we've been giving them credit for.
Change-Id: I6f11dfd0df84ec7d6be0c9b6363bd92cf224cb6a
diff --git a/src/arch/aarch64/mm.c b/src/arch/aarch64/mm.c
index b9f7270..74102ee 100644
--- a/src/arch/aarch64/mm.c
+++ b/src/arch/aarch64/mm.c
@@ -88,6 +88,8 @@
#define STAGE2_ACCESS_READ UINT64_C(1)
#define STAGE2_ACCESS_WRITE UINT64_C(2)
+#define CACHE_WORD_SIZE 4
+
/**
* Threshold number of pages in TLB to invalidate after which we invalidate all
* TLB entries on a given level.
@@ -360,13 +362,22 @@
}
/**
+ * Returns the smallest cache line size of all the caches for this core.
+ */
+static uint16_t arch_mm_dcache_line_size(void)
+{
+ return CACHE_WORD_SIZE *
+ (UINT16_C(1) << ((read_msr(CTR_EL0) >> 16) & 0xf));
+}
+
+/**
* Ensures that the range of data in the cache is written back so that it is
* visible to all cores in the system.
*/
void arch_mm_write_back_dcache(void *base, size_t size)
{
- /* Clean each data cache line the corresponds to data in the range. */
- uint16_t line_size = 1 << ((read_msr(CTR_EL0) >> 16) & 0xf);
+ /* Clean each data cache line that corresponds to data in the range. */
+ uint16_t line_size = arch_mm_dcache_line_size();
uintptr_t line_begin = (uintptr_t)base & ~(line_size - 1);
uintptr_t end = (uintptr_t)base + size;
