commit ef3c3cd92c2d337909eaf094f3accbb340ed7b1e
author Mahesh Bireddy <mahesh.reddybireddy@arm.com> Tue Jan 07 12:26:38 2020 +0530
committer Andrew Scull <ascull@google.com> Tue Jan 07 11:00:40 2020 +0000
tree 22702bde8ba0c6705fa702aa65dcad67f18238f2
parent 6cd05e1954054e798d6471324ed0acf3eff7928d

Counter-timer virtual offset register state is unknown, so should be initialized.

Signed-off-by: Mahesh Bireddy <mahesh.reddybireddy@arm.com>
Change-Id: If3c1aa9cadf9466ab936f01e17722ea687f6b7ca

src/arch/aarch64/hypervisor/cpu.c

diff --git a/src/arch/aarch64/hypervisor/cpu.c b/src/arch/aarch64/hypervisor/cpu.c
index 346c6b6..eadca3b 100644
--- a/src/arch/aarch64/hypervisor/cpu.c
+++ b/src/arch/aarch64/hypervisor/cpu.c
@@ -144,4 +144,7 @@
 	lor_disable();
 
 	write_msr(CPTR_EL2, get_cptr_el2_value());
+
+	/* Initialize counter-timer virtual offset register to 0. */
+	write_msr(CNTVOFF_EL2, 0);
 }