| /* |
| * Copyright (C) 2017 Advanced Micro Devices, Inc. |
| * |
| * Permission is hereby granted, free of charge, to any person obtaining a |
| * copy of this software and associated documentation files (the "Software"), |
| * to deal in the Software without restriction, including without limitation |
| * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
| * and/or sell copies of the Software, and to permit persons to whom the |
| * Software is furnished to do so, subject to the following conditions: |
| * |
| * The above copyright notice and this permission notice shall be included |
| * in all copies or substantial portions of the Software. |
| * |
| * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS |
| * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN |
| * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN |
| * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. |
| */ |
| #ifndef _mmhub_1_0_DEFAULT_HEADER |
| #define _mmhub_1_0_DEFAULT_HEADER |
| |
| |
| // addressBlock: mmhub_dagbdec |
| #define mmDAGB0_RDCLI0_DEFAULT 0xfe5fe0f9 |
| #define mmDAGB0_RDCLI1_DEFAULT 0xfe5fe0f9 |
| #define mmDAGB0_RDCLI2_DEFAULT 0xfe5fe0f9 |
| #define mmDAGB0_RDCLI3_DEFAULT 0xfe5fe0f9 |
| #define mmDAGB0_RDCLI4_DEFAULT 0xfe5fe0f9 |
| #define mmDAGB0_RDCLI5_DEFAULT 0xfe5fe0f9 |
| #define mmDAGB0_RDCLI6_DEFAULT 0xfe5fe0f9 |
| #define mmDAGB0_RDCLI7_DEFAULT 0xfe5fe0f9 |
| #define mmDAGB0_RDCLI8_DEFAULT 0xfe5fe0f9 |
| #define mmDAGB0_RDCLI9_DEFAULT 0xfe5fe0f9 |
| #define mmDAGB0_RDCLI10_DEFAULT 0xfe5fe0f9 |
| #define mmDAGB0_RDCLI11_DEFAULT 0xfe5fe0f9 |
| #define mmDAGB0_RDCLI12_DEFAULT 0xfe5fe0f9 |
| #define mmDAGB0_RDCLI13_DEFAULT 0xfe5fe0f9 |
| #define mmDAGB0_RDCLI14_DEFAULT 0xfe5fe0f9 |
| #define mmDAGB0_RDCLI15_DEFAULT 0xfe5fe0f9 |
| #define mmDAGB0_RD_CNTL_DEFAULT 0x03527df8 |
| #define mmDAGB0_RD_GMI_CNTL_DEFAULT 0x0000304f |
| #define mmDAGB0_RD_ADDR_DAGB_DEFAULT 0x00000039 |
| #define mmDAGB0_RD_OUTPUT_DAGB_MAX_BURST_DEFAULT 0x88888888 |
| #define mmDAGB0_RD_OUTPUT_DAGB_LAZY_TIMER_DEFAULT 0x11111111 |
| #define mmDAGB0_RD_CGTT_CLK_CTRL_DEFAULT 0x00000100 |
| #define mmDAGB0_L1TLB_RD_CGTT_CLK_CTRL_DEFAULT 0x00000100 |
| #define mmDAGB0_ATCVM_RD_CGTT_CLK_CTRL_DEFAULT 0x00000100 |
| #define mmDAGB0_RD_ADDR_DAGB_MAX_BURST0_DEFAULT 0x88888888 |
| #define mmDAGB0_RD_ADDR_DAGB_LAZY_TIMER0_DEFAULT 0x11111111 |
| #define mmDAGB0_RD_ADDR_DAGB_MAX_BURST1_DEFAULT 0x88888888 |
| #define mmDAGB0_RD_ADDR_DAGB_LAZY_TIMER1_DEFAULT 0x11111111 |
| #define mmDAGB0_RD_VC0_CNTL_DEFAULT 0xff2ff082 |
| #define mmDAGB0_RD_VC1_CNTL_DEFAULT 0xff2ff082 |
| #define mmDAGB0_RD_VC2_CNTL_DEFAULT 0xff2ff082 |
| #define mmDAGB0_RD_VC3_CNTL_DEFAULT 0xff2ff082 |
| #define mmDAGB0_RD_VC4_CNTL_DEFAULT 0xff2ff082 |
| #define mmDAGB0_RD_VC5_CNTL_DEFAULT 0xff2ff082 |
| #define mmDAGB0_RD_VC6_CNTL_DEFAULT 0xff2ff082 |
| #define mmDAGB0_RD_VC7_CNTL_DEFAULT 0xff2ff082 |
| #define mmDAGB0_RD_CNTL_MISC_DEFAULT 0x01a10408 |
| #define mmDAGB0_RD_TLB_CREDIT_DEFAULT 0x2f7bdef7 |
| #define mmDAGB0_RDCLI_ASK_PENDING_DEFAULT 0x00000000 |
| #define mmDAGB0_RDCLI_GO_PENDING_DEFAULT 0x00000000 |
| #define mmDAGB0_RDCLI_GBLSEND_PENDING_DEFAULT 0x00000000 |
| #define mmDAGB0_RDCLI_TLB_PENDING_DEFAULT 0x00000000 |
| #define mmDAGB0_RDCLI_OARB_PENDING_DEFAULT 0x00000000 |
| #define mmDAGB0_RDCLI_OSD_PENDING_DEFAULT 0x00000000 |
| #define mmDAGB0_WRCLI0_DEFAULT 0xfe5fe0f9 |
| #define mmDAGB0_WRCLI1_DEFAULT 0xfe5fe0f9 |
| #define mmDAGB0_WRCLI2_DEFAULT 0xfe5fe0f9 |
| #define mmDAGB0_WRCLI3_DEFAULT 0xfe5fe0f9 |
| #define mmDAGB0_WRCLI4_DEFAULT 0xfe5fe0f9 |
| #define mmDAGB0_WRCLI5_DEFAULT 0xfe5fe0f9 |
| #define mmDAGB0_WRCLI6_DEFAULT 0xfe5fe0f9 |
| #define mmDAGB0_WRCLI7_DEFAULT 0xfe5fe0f9 |
| #define mmDAGB0_WRCLI8_DEFAULT 0xfe5fe0f9 |
| #define mmDAGB0_WRCLI9_DEFAULT 0xfe5fe0f9 |
| #define mmDAGB0_WRCLI10_DEFAULT 0xfe5fe0f9 |
| #define mmDAGB0_WRCLI11_DEFAULT 0xfe5fe0f9 |
| #define mmDAGB0_WRCLI12_DEFAULT 0xfe5fe0f9 |
| #define mmDAGB0_WRCLI13_DEFAULT 0xfe5fe0f9 |
| #define mmDAGB0_WRCLI14_DEFAULT 0xfe5fe0f9 |
| #define mmDAGB0_WRCLI15_DEFAULT 0xfe5fe0f9 |
| #define mmDAGB0_WR_CNTL_DEFAULT 0x03527df8 |
| #define mmDAGB0_WR_GMI_CNTL_DEFAULT 0x0000304f |
| #define mmDAGB0_WR_ADDR_DAGB_DEFAULT 0x00000039 |
| #define mmDAGB0_WR_OUTPUT_DAGB_MAX_BURST_DEFAULT 0x88888888 |
| #define mmDAGB0_WR_OUTPUT_DAGB_LAZY_TIMER_DEFAULT 0x11111111 |
| #define mmDAGB0_WR_CGTT_CLK_CTRL_DEFAULT 0x00000100 |
| #define mmDAGB0_L1TLB_WR_CGTT_CLK_CTRL_DEFAULT 0x00000100 |
| #define mmDAGB0_ATCVM_WR_CGTT_CLK_CTRL_DEFAULT 0x00000100 |
| #define mmDAGB0_WR_ADDR_DAGB_MAX_BURST0_DEFAULT 0x88888888 |
| #define mmDAGB0_WR_ADDR_DAGB_LAZY_TIMER0_DEFAULT 0x11111111 |
| #define mmDAGB0_WR_ADDR_DAGB_MAX_BURST1_DEFAULT 0x88888888 |
| #define mmDAGB0_WR_ADDR_DAGB_LAZY_TIMER1_DEFAULT 0x11111111 |
| #define mmDAGB0_WR_DATA_DAGB_DEFAULT 0x00000001 |
| #define mmDAGB0_WR_DATA_DAGB_MAX_BURST0_DEFAULT 0x11111111 |
| #define mmDAGB0_WR_DATA_DAGB_LAZY_TIMER0_DEFAULT 0x00000000 |
| #define mmDAGB0_WR_DATA_DAGB_MAX_BURST1_DEFAULT 0x11111111 |
| #define mmDAGB0_WR_DATA_DAGB_LAZY_TIMER1_DEFAULT 0x00000000 |
| #define mmDAGB0_WR_VC0_CNTL_DEFAULT 0xff2ff082 |
| #define mmDAGB0_WR_VC1_CNTL_DEFAULT 0xff2ff082 |
| #define mmDAGB0_WR_VC2_CNTL_DEFAULT 0xff2ff082 |
| #define mmDAGB0_WR_VC3_CNTL_DEFAULT 0xff2ff082 |
| #define mmDAGB0_WR_VC4_CNTL_DEFAULT 0xff2ff082 |
| #define mmDAGB0_WR_VC5_CNTL_DEFAULT 0xff2ff082 |
| #define mmDAGB0_WR_VC6_CNTL_DEFAULT 0xff2ff082 |
| #define mmDAGB0_WR_VC7_CNTL_DEFAULT 0xff2ff082 |
| #define mmDAGB0_WR_CNTL_MISC_DEFAULT 0x01a10408 |
| #define mmDAGB0_WR_TLB_CREDIT_DEFAULT 0x2f7bdef7 |
| #define mmDAGB0_WR_DATA_CREDIT_DEFAULT 0x5c626870 |
| #define mmDAGB0_WR_MISC_CREDIT_DEFAULT 0x0078dc88 |
| #define mmDAGB0_WRCLI_ASK_PENDING_DEFAULT 0x00000000 |
| #define mmDAGB0_WRCLI_GO_PENDING_DEFAULT 0x00000000 |
| #define mmDAGB0_WRCLI_GBLSEND_PENDING_DEFAULT 0x00000000 |
| #define mmDAGB0_WRCLI_TLB_PENDING_DEFAULT 0x00000000 |
| #define mmDAGB0_WRCLI_OARB_PENDING_DEFAULT 0x00000000 |
| #define mmDAGB0_WRCLI_OSD_PENDING_DEFAULT 0x00000000 |
| #define mmDAGB0_WRCLI_DBUS_ASK_PENDING_DEFAULT 0x00000000 |
| #define mmDAGB0_WRCLI_DBUS_GO_PENDING_DEFAULT 0x00000000 |
| #define mmDAGB0_DAGB_DLY_DEFAULT 0x00000000 |
| #define mmDAGB0_CNTL_MISC_DEFAULT 0xcf7c1ffa |
| #define mmDAGB0_CNTL_MISC2_DEFAULT 0x00000000 |
| #define mmDAGB0_FIFO_EMPTY_DEFAULT 0x00ffffff |
| #define mmDAGB0_FIFO_FULL_DEFAULT 0x00000000 |
| #define mmDAGB0_WR_CREDITS_FULL_DEFAULT 0x0007ffff |
| #define mmDAGB0_RD_CREDITS_FULL_DEFAULT 0x0003ffff |
| #define mmDAGB0_PERFCOUNTER_LO_DEFAULT 0x00000000 |
| #define mmDAGB0_PERFCOUNTER_HI_DEFAULT 0x00000000 |
| #define mmDAGB0_PERFCOUNTER0_CFG_DEFAULT 0x00000000 |
| #define mmDAGB0_PERFCOUNTER1_CFG_DEFAULT 0x00000000 |
| #define mmDAGB0_PERFCOUNTER2_CFG_DEFAULT 0x00000000 |
| #define mmDAGB0_PERFCOUNTER_RSLT_CNTL_DEFAULT 0x04000000 |
| #define mmDAGB0_RESERVE0_DEFAULT 0x00000000 |
| #define mmDAGB0_RESERVE1_DEFAULT 0x00000000 |
| #define mmDAGB0_RESERVE2_DEFAULT 0x00000000 |
| #define mmDAGB0_RESERVE3_DEFAULT 0x00000000 |
| #define mmDAGB0_RESERVE4_DEFAULT 0x00000000 |
| #define mmDAGB0_RESERVE5_DEFAULT 0x00000000 |
| #define mmDAGB0_RESERVE6_DEFAULT 0x00000000 |
| #define mmDAGB0_RESERVE7_DEFAULT 0x00000000 |
| #define mmDAGB0_RESERVE8_DEFAULT 0x00000000 |
| #define mmDAGB0_RESERVE9_DEFAULT 0x00000000 |
| #define mmDAGB0_RESERVE10_DEFAULT 0x00000000 |
| #define mmDAGB0_RESERVE11_DEFAULT 0x00000000 |
| #define mmDAGB0_RESERVE12_DEFAULT 0x00000000 |
| #define mmDAGB0_RESERVE13_DEFAULT 0x00000000 |
| #define mmDAGB0_RESERVE14_DEFAULT 0x00000000 |
| #define mmDAGB0_RESERVE15_DEFAULT 0x00000000 |
| #define mmDAGB0_RESERVE16_DEFAULT 0x00000000 |
| #define mmDAGB0_RESERVE17_DEFAULT 0x00000000 |
| #define mmDAGB1_RDCLI0_DEFAULT 0xfe5fe0f9 |
| #define mmDAGB1_RDCLI1_DEFAULT 0xfe5fe0f9 |
| #define mmDAGB1_RDCLI2_DEFAULT 0xfe5fe0f9 |
| #define mmDAGB1_RDCLI3_DEFAULT 0xfe5fe0f9 |
| #define mmDAGB1_RDCLI4_DEFAULT 0xfe5fe0f9 |
| #define mmDAGB1_RDCLI5_DEFAULT 0xfe5fe0f9 |
| #define mmDAGB1_RDCLI6_DEFAULT 0xfe5fe0f9 |
| #define mmDAGB1_RDCLI7_DEFAULT 0xfe5fe0f9 |
| #define mmDAGB1_RDCLI8_DEFAULT 0xfe5fe0f9 |
| #define mmDAGB1_RDCLI9_DEFAULT 0xfe5fe0f9 |
| #define mmDAGB1_RDCLI10_DEFAULT 0xfe5fe0f9 |
| #define mmDAGB1_RDCLI11_DEFAULT 0xfe5fe0f9 |
| #define mmDAGB1_RDCLI12_DEFAULT 0xfe5fe0f9 |
| #define mmDAGB1_RDCLI13_DEFAULT 0xfe5fe0f9 |
| #define mmDAGB1_RDCLI14_DEFAULT 0xfe5fe0f9 |
| #define mmDAGB1_RDCLI15_DEFAULT 0xfe5fe0f9 |
| #define mmDAGB1_RD_CNTL_DEFAULT 0x03527df8 |
| #define mmDAGB1_RD_GMI_CNTL_DEFAULT 0x0000304f |
| #define mmDAGB1_RD_ADDR_DAGB_DEFAULT 0x00000039 |
| #define mmDAGB1_RD_OUTPUT_DAGB_MAX_BURST_DEFAULT 0x88888888 |
| #define mmDAGB1_RD_OUTPUT_DAGB_LAZY_TIMER_DEFAULT 0x11111111 |
| #define mmDAGB1_RD_CGTT_CLK_CTRL_DEFAULT 0x00000100 |
| #define mmDAGB1_L1TLB_RD_CGTT_CLK_CTRL_DEFAULT 0x00000100 |
| #define mmDAGB1_ATCVM_RD_CGTT_CLK_CTRL_DEFAULT 0x00000100 |
| #define mmDAGB1_RD_ADDR_DAGB_MAX_BURST0_DEFAULT 0x88888888 |
| #define mmDAGB1_RD_ADDR_DAGB_LAZY_TIMER0_DEFAULT 0x11111111 |
| #define mmDAGB1_RD_ADDR_DAGB_MAX_BURST1_DEFAULT 0x88888888 |
| #define mmDAGB1_RD_ADDR_DAGB_LAZY_TIMER1_DEFAULT 0x11111111 |
| #define mmDAGB1_RD_VC0_CNTL_DEFAULT 0xff2ff082 |
| #define mmDAGB1_RD_VC1_CNTL_DEFAULT 0xff2ff082 |
| #define mmDAGB1_RD_VC2_CNTL_DEFAULT 0xff2ff082 |
| #define mmDAGB1_RD_VC3_CNTL_DEFAULT 0xff2ff082 |
| #define mmDAGB1_RD_VC4_CNTL_DEFAULT 0xff2ff082 |
| #define mmDAGB1_RD_VC5_CNTL_DEFAULT 0xff2ff082 |
| #define mmDAGB1_RD_VC6_CNTL_DEFAULT 0xff2ff082 |
| #define mmDAGB1_RD_VC7_CNTL_DEFAULT 0xff2ff082 |
| #define mmDAGB1_RD_CNTL_MISC_DEFAULT 0x01a10408 |
| #define mmDAGB1_RD_TLB_CREDIT_DEFAULT 0x2f7bdef7 |
| #define mmDAGB1_RDCLI_ASK_PENDING_DEFAULT 0x00000000 |
| #define mmDAGB1_RDCLI_GO_PENDING_DEFAULT 0x00000000 |
| #define mmDAGB1_RDCLI_GBLSEND_PENDING_DEFAULT 0x00000000 |
| #define mmDAGB1_RDCLI_TLB_PENDING_DEFAULT 0x00000000 |
| #define mmDAGB1_RDCLI_OARB_PENDING_DEFAULT 0x00000000 |
| #define mmDAGB1_RDCLI_OSD_PENDING_DEFAULT 0x00000000 |
| #define mmDAGB1_WRCLI0_DEFAULT 0xfe5fe0f9 |
| #define mmDAGB1_WRCLI1_DEFAULT 0xfe5fe0f9 |
| #define mmDAGB1_WRCLI2_DEFAULT 0xfe5fe0f9 |
| #define mmDAGB1_WRCLI3_DEFAULT 0xfe5fe0f9 |
| #define mmDAGB1_WRCLI4_DEFAULT 0xfe5fe0f9 |
| #define mmDAGB1_WRCLI5_DEFAULT 0xfe5fe0f9 |
| #define mmDAGB1_WRCLI6_DEFAULT 0xfe5fe0f9 |
| #define mmDAGB1_WRCLI7_DEFAULT 0xfe5fe0f9 |
| #define mmDAGB1_WRCLI8_DEFAULT 0xfe5fe0f9 |
| #define mmDAGB1_WRCLI9_DEFAULT 0xfe5fe0f9 |
| #define mmDAGB1_WRCLI10_DEFAULT 0xfe5fe0f9 |
| #define mmDAGB1_WRCLI11_DEFAULT 0xfe5fe0f9 |
| #define mmDAGB1_WRCLI12_DEFAULT 0xfe5fe0f9 |
| #define mmDAGB1_WRCLI13_DEFAULT 0xfe5fe0f9 |
| #define mmDAGB1_WRCLI14_DEFAULT 0xfe5fe0f9 |
| #define mmDAGB1_WRCLI15_DEFAULT 0xfe5fe0f9 |
| #define mmDAGB1_WR_CNTL_DEFAULT 0x03527df8 |
| #define mmDAGB1_WR_GMI_CNTL_DEFAULT 0x0000304f |
| #define mmDAGB1_WR_ADDR_DAGB_DEFAULT 0x00000039 |
| #define mmDAGB1_WR_OUTPUT_DAGB_MAX_BURST_DEFAULT 0x88888888 |
| #define mmDAGB1_WR_OUTPUT_DAGB_LAZY_TIMER_DEFAULT 0x11111111 |
| #define mmDAGB1_WR_CGTT_CLK_CTRL_DEFAULT 0x00000100 |
| #define mmDAGB1_L1TLB_WR_CGTT_CLK_CTRL_DEFAULT 0x00000100 |
| #define mmDAGB1_ATCVM_WR_CGTT_CLK_CTRL_DEFAULT 0x00000100 |
| #define mmDAGB1_WR_ADDR_DAGB_MAX_BURST0_DEFAULT 0x88888888 |
| #define mmDAGB1_WR_ADDR_DAGB_LAZY_TIMER0_DEFAULT 0x11111111 |
| #define mmDAGB1_WR_ADDR_DAGB_MAX_BURST1_DEFAULT 0x88888888 |
| #define mmDAGB1_WR_ADDR_DAGB_LAZY_TIMER1_DEFAULT 0x11111111 |
| #define mmDAGB1_WR_DATA_DAGB_DEFAULT 0x00000001 |
| #define mmDAGB1_WR_DATA_DAGB_MAX_BURST0_DEFAULT 0x11111111 |
| #define mmDAGB1_WR_DATA_DAGB_LAZY_TIMER0_DEFAULT 0x00000000 |
| #define mmDAGB1_WR_DATA_DAGB_MAX_BURST1_DEFAULT 0x11111111 |
| #define mmDAGB1_WR_DATA_DAGB_LAZY_TIMER1_DEFAULT 0x00000000 |
| #define mmDAGB1_WR_VC0_CNTL_DEFAULT 0xff2ff082 |
| #define mmDAGB1_WR_VC1_CNTL_DEFAULT 0xff2ff082 |
| #define mmDAGB1_WR_VC2_CNTL_DEFAULT 0xff2ff082 |
| #define mmDAGB1_WR_VC3_CNTL_DEFAULT 0xff2ff082 |
| #define mmDAGB1_WR_VC4_CNTL_DEFAULT 0xff2ff082 |
| #define mmDAGB1_WR_VC5_CNTL_DEFAULT 0xff2ff082 |
| #define mmDAGB1_WR_VC6_CNTL_DEFAULT 0xff2ff082 |
| #define mmDAGB1_WR_VC7_CNTL_DEFAULT 0xff2ff082 |
| #define mmDAGB1_WR_CNTL_MISC_DEFAULT 0x01a10408 |
| #define mmDAGB1_WR_TLB_CREDIT_DEFAULT 0x2f7bdef7 |
| #define mmDAGB1_WR_DATA_CREDIT_DEFAULT 0x5c626870 |
| #define mmDAGB1_WR_MISC_CREDIT_DEFAULT 0x0078dc88 |
| #define mmDAGB1_WRCLI_ASK_PENDING_DEFAULT 0x00000000 |
| #define mmDAGB1_WRCLI_GO_PENDING_DEFAULT 0x00000000 |
| #define mmDAGB1_WRCLI_GBLSEND_PENDING_DEFAULT 0x00000000 |
| #define mmDAGB1_WRCLI_TLB_PENDING_DEFAULT 0x00000000 |
| #define mmDAGB1_WRCLI_OARB_PENDING_DEFAULT 0x00000000 |
| #define mmDAGB1_WRCLI_OSD_PENDING_DEFAULT 0x00000000 |
| #define mmDAGB1_WRCLI_DBUS_ASK_PENDING_DEFAULT 0x00000000 |
| #define mmDAGB1_WRCLI_DBUS_GO_PENDING_DEFAULT 0x00000000 |
| #define mmDAGB1_DAGB_DLY_DEFAULT 0x00000000 |
| #define mmDAGB1_CNTL_MISC_DEFAULT 0xcf7c1ffa |
| #define mmDAGB1_CNTL_MISC2_DEFAULT 0x00000000 |
| #define mmDAGB1_FIFO_EMPTY_DEFAULT 0x00ffffff |
| #define mmDAGB1_FIFO_FULL_DEFAULT 0x00000000 |
| #define mmDAGB1_WR_CREDITS_FULL_DEFAULT 0x0007ffff |
| #define mmDAGB1_RD_CREDITS_FULL_DEFAULT 0x0003ffff |
| #define mmDAGB1_PERFCOUNTER_LO_DEFAULT 0x00000000 |
| #define mmDAGB1_PERFCOUNTER_HI_DEFAULT 0x00000000 |
| #define mmDAGB1_PERFCOUNTER0_CFG_DEFAULT 0x00000000 |
| #define mmDAGB1_PERFCOUNTER1_CFG_DEFAULT 0x00000000 |
| #define mmDAGB1_PERFCOUNTER2_CFG_DEFAULT 0x00000000 |
| #define mmDAGB1_PERFCOUNTER_RSLT_CNTL_DEFAULT 0x04000000 |
| #define mmDAGB1_RESERVE0_DEFAULT 0x00000000 |
| #define mmDAGB1_RESERVE1_DEFAULT 0x00000000 |
| #define mmDAGB1_RESERVE2_DEFAULT 0x00000000 |
| #define mmDAGB1_RESERVE3_DEFAULT 0x00000000 |
| #define mmDAGB1_RESERVE4_DEFAULT 0x00000000 |
| #define mmDAGB1_RESERVE5_DEFAULT 0x00000000 |
| #define mmDAGB1_RESERVE6_DEFAULT 0x00000000 |
| #define mmDAGB1_RESERVE7_DEFAULT 0x00000000 |
| #define mmDAGB1_RESERVE8_DEFAULT 0x00000000 |
| #define mmDAGB1_RESERVE9_DEFAULT 0x00000000 |
| #define mmDAGB1_RESERVE10_DEFAULT 0x00000000 |
| #define mmDAGB1_RESERVE11_DEFAULT 0x00000000 |
| #define mmDAGB1_RESERVE12_DEFAULT 0x00000000 |
| #define mmDAGB1_RESERVE13_DEFAULT 0x00000000 |
| #define mmDAGB1_RESERVE14_DEFAULT 0x00000000 |
| #define mmDAGB1_RESERVE15_DEFAULT 0x00000000 |
| #define mmDAGB1_RESERVE16_DEFAULT 0x00000000 |
| #define mmDAGB1_RESERVE17_DEFAULT 0x00000000 |
| |
| |
| // addressBlock: mmhub_ea_mmeadec |
| #define mmMMEA0_DRAM_RD_CLI2GRP_MAP0_DEFAULT 0x55555555 |
| #define mmMMEA0_DRAM_RD_CLI2GRP_MAP1_DEFAULT 0x55555555 |
| #define mmMMEA0_DRAM_WR_CLI2GRP_MAP0_DEFAULT 0x55555555 |
| #define mmMMEA0_DRAM_WR_CLI2GRP_MAP1_DEFAULT 0x55555555 |
| #define mmMMEA0_DRAM_RD_GRP2VC_MAP_DEFAULT 0x00000e25 |
| #define mmMMEA0_DRAM_WR_GRP2VC_MAP_DEFAULT 0x00000e25 |
| #define mmMMEA0_DRAM_RD_LAZY_DEFAULT 0x00000924 |
| #define mmMMEA0_DRAM_WR_LAZY_DEFAULT 0x00000924 |
| #define mmMMEA0_DRAM_RD_CAM_CNTL_DEFAULT 0x06db3333 |
| #define mmMMEA0_DRAM_WR_CAM_CNTL_DEFAULT 0x06db3333 |
| #define mmMMEA0_DRAM_PAGE_BURST_DEFAULT 0x20002000 |
| #define mmMMEA0_DRAM_RD_PRI_AGE_DEFAULT 0x00db6249 |
| #define mmMMEA0_DRAM_WR_PRI_AGE_DEFAULT 0x00db6249 |
| #define mmMMEA0_DRAM_RD_PRI_QUEUING_DEFAULT 0x00000db6 |
| #define mmMMEA0_DRAM_WR_PRI_QUEUING_DEFAULT 0x00000db6 |
| #define mmMMEA0_DRAM_RD_PRI_FIXED_DEFAULT 0x00000924 |
| #define mmMMEA0_DRAM_WR_PRI_FIXED_DEFAULT 0x00000924 |
| #define mmMMEA0_DRAM_RD_PRI_URGENCY_DEFAULT 0x0000fdb6 |
| #define mmMMEA0_DRAM_WR_PRI_URGENCY_DEFAULT 0x0000fdb6 |
| #define mmMMEA0_DRAM_RD_PRI_QUANT_PRI1_DEFAULT 0x3f3f3f3f |
| #define mmMMEA0_DRAM_RD_PRI_QUANT_PRI2_DEFAULT 0x7f7f7f7f |
| #define mmMMEA0_DRAM_RD_PRI_QUANT_PRI3_DEFAULT 0xffffffff |
| #define mmMMEA0_DRAM_WR_PRI_QUANT_PRI1_DEFAULT 0x3f3f3f3f |
| #define mmMMEA0_DRAM_WR_PRI_QUANT_PRI2_DEFAULT 0x7f7f7f7f |
| #define mmMMEA0_DRAM_WR_PRI_QUANT_PRI3_DEFAULT 0xffffffff |
| #define mmMMEA0_ADDRNORM_BASE_ADDR0_DEFAULT 0x00000000 |
| #define mmMMEA0_ADDRNORM_LIMIT_ADDR0_DEFAULT 0x00000000 |
| #define mmMMEA0_ADDRNORM_BASE_ADDR1_DEFAULT 0x00000000 |
| #define mmMMEA0_ADDRNORM_LIMIT_ADDR1_DEFAULT 0x00000000 |
| #define mmMMEA0_ADDRNORM_OFFSET_ADDR1_DEFAULT 0x00000000 |
| #define mmMMEA0_ADDRNORM_HOLE_CNTL_DEFAULT 0x00000000 |
| #define mmMMEA0_ADDRDEC_BANK_CFG_DEFAULT 0x000001ef |
| #define mmMMEA0_ADDRDEC_MISC_CFG_DEFAULT 0x3ffff000 |
| #define mmMMEA0_ADDRDECDRAM_ADDR_HASH_BANK0_DEFAULT 0x00000000 |
| #define mmMMEA0_ADDRDECDRAM_ADDR_HASH_BANK1_DEFAULT 0x00000000 |
| #define mmMMEA0_ADDRDECDRAM_ADDR_HASH_BANK2_DEFAULT 0x00000000 |
| #define mmMMEA0_ADDRDECDRAM_ADDR_HASH_BANK3_DEFAULT 0x00000000 |
| #define mmMMEA0_ADDRDECDRAM_ADDR_HASH_BANK4_DEFAULT 0x00000000 |
| #define mmMMEA0_ADDRDECDRAM_ADDR_HASH_PC_DEFAULT 0x00000000 |
| #define mmMMEA0_ADDRDECDRAM_ADDR_HASH_PC2_DEFAULT 0x00000000 |
| #define mmMMEA0_ADDRDECDRAM_ADDR_HASH_CS0_DEFAULT 0x00000000 |
| #define mmMMEA0_ADDRDECDRAM_ADDR_HASH_CS1_DEFAULT 0x00000000 |
| #define mmMMEA0_ADDRDECDRAM_HARVEST_ENABLE_DEFAULT 0x00000000 |
| #define mmMMEA0_ADDRDEC0_BASE_ADDR_CS0_DEFAULT 0x00000000 |
| #define mmMMEA0_ADDRDEC0_BASE_ADDR_CS1_DEFAULT 0x00000000 |
| #define mmMMEA0_ADDRDEC0_BASE_ADDR_CS2_DEFAULT 0x00000000 |
| #define mmMMEA0_ADDRDEC0_BASE_ADDR_CS3_DEFAULT 0x00000000 |
| #define mmMMEA0_ADDRDEC0_BASE_ADDR_SECCS0_DEFAULT 0x00000000 |
| #define mmMMEA0_ADDRDEC0_BASE_ADDR_SECCS1_DEFAULT 0x00000000 |
| #define mmMMEA0_ADDRDEC0_BASE_ADDR_SECCS2_DEFAULT 0x00000000 |
| #define mmMMEA0_ADDRDEC0_BASE_ADDR_SECCS3_DEFAULT 0x00000000 |
| #define mmMMEA0_ADDRDEC0_ADDR_MASK_CS01_DEFAULT 0xfffffffe |
| #define mmMMEA0_ADDRDEC0_ADDR_MASK_CS23_DEFAULT 0xfffffffe |
| #define mmMMEA0_ADDRDEC0_ADDR_MASK_SECCS01_DEFAULT 0xfffffffe |
| #define mmMMEA0_ADDRDEC0_ADDR_MASK_SECCS23_DEFAULT 0xfffffffe |
| #define mmMMEA0_ADDRDEC0_ADDR_CFG_CS01_DEFAULT 0x00050408 |
| #define mmMMEA0_ADDRDEC0_ADDR_CFG_CS23_DEFAULT 0x00050408 |
| #define mmMMEA0_ADDRDEC0_ADDR_SEL_CS01_DEFAULT 0x04076543 |
| #define mmMMEA0_ADDRDEC0_ADDR_SEL_CS23_DEFAULT 0x04076543 |
| #define mmMMEA0_ADDRDEC0_COL_SEL_LO_CS01_DEFAULT 0x87654321 |
| #define mmMMEA0_ADDRDEC0_COL_SEL_LO_CS23_DEFAULT 0x87654321 |
| #define mmMMEA0_ADDRDEC0_COL_SEL_HI_CS01_DEFAULT 0xa9876543 |
| #define mmMMEA0_ADDRDEC0_COL_SEL_HI_CS23_DEFAULT 0xa9876543 |
| #define mmMMEA0_ADDRDEC0_RM_SEL_CS01_DEFAULT 0x00000000 |
| #define mmMMEA0_ADDRDEC0_RM_SEL_CS23_DEFAULT 0x00000000 |
| #define mmMMEA0_ADDRDEC0_RM_SEL_SECCS01_DEFAULT 0x00000000 |
| #define mmMMEA0_ADDRDEC0_RM_SEL_SECCS23_DEFAULT 0x00000000 |
| #define mmMMEA0_ADDRDEC1_BASE_ADDR_CS0_DEFAULT 0x00000000 |
| #define mmMMEA0_ADDRDEC1_BASE_ADDR_CS1_DEFAULT 0x00000000 |
| #define mmMMEA0_ADDRDEC1_BASE_ADDR_CS2_DEFAULT 0x00000000 |
| #define mmMMEA0_ADDRDEC1_BASE_ADDR_CS3_DEFAULT 0x00000000 |
| #define mmMMEA0_ADDRDEC1_BASE_ADDR_SECCS0_DEFAULT 0x00000000 |
| #define mmMMEA0_ADDRDEC1_BASE_ADDR_SECCS1_DEFAULT 0x00000000 |
| #define mmMMEA0_ADDRDEC1_BASE_ADDR_SECCS2_DEFAULT 0x00000000 |
| #define mmMMEA0_ADDRDEC1_BASE_ADDR_SECCS3_DEFAULT 0x00000000 |
| #define mmMMEA0_ADDRDEC1_ADDR_MASK_CS01_DEFAULT 0xfffffffe |
| #define mmMMEA0_ADDRDEC1_ADDR_MASK_CS23_DEFAULT 0xfffffffe |
| #define mmMMEA0_ADDRDEC1_ADDR_MASK_SECCS01_DEFAULT 0xfffffffe |
| #define mmMMEA0_ADDRDEC1_ADDR_MASK_SECCS23_DEFAULT 0xfffffffe |
| #define mmMMEA0_ADDRDEC1_ADDR_CFG_CS01_DEFAULT 0x00050408 |
| #define mmMMEA0_ADDRDEC1_ADDR_CFG_CS23_DEFAULT 0x00050408 |
| #define mmMMEA0_ADDRDEC1_ADDR_SEL_CS01_DEFAULT 0x04076543 |
| #define mmMMEA0_ADDRDEC1_ADDR_SEL_CS23_DEFAULT 0x04076543 |
| #define mmMMEA0_ADDRDEC1_COL_SEL_LO_CS01_DEFAULT 0x87654321 |
| #define mmMMEA0_ADDRDEC1_COL_SEL_LO_CS23_DEFAULT 0x87654321 |
| #define mmMMEA0_ADDRDEC1_COL_SEL_HI_CS01_DEFAULT 0xa9876543 |
| #define mmMMEA0_ADDRDEC1_COL_SEL_HI_CS23_DEFAULT 0xa9876543 |
| #define mmMMEA0_ADDRDEC1_RM_SEL_CS01_DEFAULT 0x00000000 |
| #define mmMMEA0_ADDRDEC1_RM_SEL_CS23_DEFAULT 0x00000000 |
| #define mmMMEA0_ADDRDEC1_RM_SEL_SECCS01_DEFAULT 0x00000000 |
| #define mmMMEA0_ADDRDEC1_RM_SEL_SECCS23_DEFAULT 0x00000000 |
| #define mmMMEA0_IO_RD_CLI2GRP_MAP0_DEFAULT 0xe4e4e4e4 |
| #define mmMMEA0_IO_RD_CLI2GRP_MAP1_DEFAULT 0xe4e4e4e4 |
| #define mmMMEA0_IO_WR_CLI2GRP_MAP0_DEFAULT 0xe4e4e4e4 |
| #define mmMMEA0_IO_WR_CLI2GRP_MAP1_DEFAULT 0xe4e4e4e4 |
| #define mmMMEA0_IO_RD_COMBINE_FLUSH_DEFAULT 0x00007777 |
| #define mmMMEA0_IO_WR_COMBINE_FLUSH_DEFAULT 0x00007777 |
| #define mmMMEA0_IO_GROUP_BURST_DEFAULT 0x1f031f03 |
| #define mmMMEA0_IO_RD_PRI_AGE_DEFAULT 0x00db6249 |
| #define mmMMEA0_IO_WR_PRI_AGE_DEFAULT 0x00db6249 |
| #define mmMMEA0_IO_RD_PRI_QUEUING_DEFAULT 0x00000db6 |
| #define mmMMEA0_IO_WR_PRI_QUEUING_DEFAULT 0x00000db6 |
| #define mmMMEA0_IO_RD_PRI_FIXED_DEFAULT 0x00000924 |
| #define mmMMEA0_IO_WR_PRI_FIXED_DEFAULT 0x00000924 |
| #define mmMMEA0_IO_RD_PRI_URGENCY_DEFAULT 0x00000492 |
| #define mmMMEA0_IO_WR_PRI_URGENCY_DEFAULT 0x00000492 |
| #define mmMMEA0_IO_RD_PRI_URGENCY_MASK_DEFAULT 0xffffffff |
| #define mmMMEA0_IO_WR_PRI_URGENCY_MASK_DEFAULT 0xffffffff |
| #define mmMMEA0_IO_RD_PRI_QUANT_PRI1_DEFAULT 0x3f3f3f3f |
| #define mmMMEA0_IO_RD_PRI_QUANT_PRI2_DEFAULT 0x7f7f7f7f |
| #define mmMMEA0_IO_RD_PRI_QUANT_PRI3_DEFAULT 0xffffffff |
| #define mmMMEA0_IO_WR_PRI_QUANT_PRI1_DEFAULT 0x3f3f3f3f |
| #define mmMMEA0_IO_WR_PRI_QUANT_PRI2_DEFAULT 0x7f7f7f7f |
| #define mmMMEA0_IO_WR_PRI_QUANT_PRI3_DEFAULT 0xffffffff |
| #define mmMMEA0_SDP_ARB_DRAM_DEFAULT 0x00102040 |
| #define mmMMEA0_SDP_ARB_FINAL_DEFAULT 0x00007fff |
| #define mmMMEA0_SDP_DRAM_PRIORITY_DEFAULT 0x00000000 |
| #define mmMMEA0_SDP_IO_PRIORITY_DEFAULT 0x00000000 |
| #define mmMMEA0_SDP_CREDITS_DEFAULT 0x000100bf |
| #define mmMMEA0_SDP_TAG_RESERVE0_DEFAULT 0x00000000 |
| #define mmMMEA0_SDP_TAG_RESERVE1_DEFAULT 0x00000000 |
| #define mmMMEA0_SDP_VCC_RESERVE0_DEFAULT 0x00000000 |
| #define mmMMEA0_SDP_VCC_RESERVE1_DEFAULT 0x00000000 |
| #define mmMMEA0_SDP_VCD_RESERVE0_DEFAULT 0x00000000 |
| #define mmMMEA0_SDP_VCD_RESERVE1_DEFAULT 0x00000000 |
| #define mmMMEA0_SDP_REQ_CNTL_DEFAULT 0x0000000f |
| #define mmMMEA0_MISC_DEFAULT 0x00180130 |
| #define mmMMEA0_LATENCY_SAMPLING_DEFAULT 0x00000000 |
| #define mmMMEA0_PERFCOUNTER_LO_DEFAULT 0x00000000 |
| #define mmMMEA0_PERFCOUNTER_HI_DEFAULT 0x00000000 |
| #define mmMMEA0_PERFCOUNTER0_CFG_DEFAULT 0x00000000 |
| #define mmMMEA0_PERFCOUNTER1_CFG_DEFAULT 0x00000000 |
| #define mmMMEA0_PERFCOUNTER_RSLT_CNTL_DEFAULT 0x04000000 |
| #define mmMMEA0_EDC_CNT_DEFAULT 0x00000000 |
| #define mmMMEA0_EDC_CNT2_DEFAULT 0x00000000 |
| #define mmMMEA0_DSM_CNTL_DEFAULT 0x00000000 |
| #define mmMMEA0_DSM_CNTLA_DEFAULT 0x00000000 |
| #define mmMMEA0_DSM_CNTLB_DEFAULT 0x00000000 |
| #define mmMMEA0_DSM_CNTL2_DEFAULT 0x00000000 |
| #define mmMMEA0_DSM_CNTL2A_DEFAULT 0x00000000 |
| #define mmMMEA0_DSM_CNTL2B_DEFAULT 0x00000000 |
| #define mmMMEA0_CGTT_CLK_CTRL_DEFAULT 0x00000100 |
| #define mmMMEA0_EDC_MODE_DEFAULT 0x00000000 |
| #define mmMMEA0_ERR_STATUS_DEFAULT 0x00000000 |
| #define mmMMEA0_MISC2_DEFAULT 0x00000000 |
| #define mmMMEA1_DRAM_RD_CLI2GRP_MAP0_DEFAULT 0x55555555 |
| #define mmMMEA1_DRAM_RD_CLI2GRP_MAP1_DEFAULT 0x55555555 |
| #define mmMMEA1_DRAM_WR_CLI2GRP_MAP0_DEFAULT 0x55555555 |
| #define mmMMEA1_DRAM_WR_CLI2GRP_MAP1_DEFAULT 0x55555555 |
| #define mmMMEA1_DRAM_RD_GRP2VC_MAP_DEFAULT 0x00000e25 |
| #define mmMMEA1_DRAM_WR_GRP2VC_MAP_DEFAULT 0x00000e25 |
| #define mmMMEA1_DRAM_RD_LAZY_DEFAULT 0x00000924 |
| #define mmMMEA1_DRAM_WR_LAZY_DEFAULT 0x00000924 |
| #define mmMMEA1_DRAM_RD_CAM_CNTL_DEFAULT 0x06db3333 |
| #define mmMMEA1_DRAM_WR_CAM_CNTL_DEFAULT 0x06db3333 |
| #define mmMMEA1_DRAM_PAGE_BURST_DEFAULT 0x20002000 |
| #define mmMMEA1_DRAM_RD_PRI_AGE_DEFAULT 0x00db6249 |
| #define mmMMEA1_DRAM_WR_PRI_AGE_DEFAULT 0x00db6249 |
| #define mmMMEA1_DRAM_RD_PRI_QUEUING_DEFAULT 0x00000db6 |
| #define mmMMEA1_DRAM_WR_PRI_QUEUING_DEFAULT 0x00000db6 |
| #define mmMMEA1_DRAM_RD_PRI_FIXED_DEFAULT 0x00000924 |
| #define mmMMEA1_DRAM_WR_PRI_FIXED_DEFAULT 0x00000924 |
| #define mmMMEA1_DRAM_RD_PRI_URGENCY_DEFAULT 0x0000fdb6 |
| #define mmMMEA1_DRAM_WR_PRI_URGENCY_DEFAULT 0x0000fdb6 |
| #define mmMMEA1_DRAM_RD_PRI_QUANT_PRI1_DEFAULT 0x3f3f3f3f |
| #define mmMMEA1_DRAM_RD_PRI_QUANT_PRI2_DEFAULT 0x7f7f7f7f |
| #define mmMMEA1_DRAM_RD_PRI_QUANT_PRI3_DEFAULT 0xffffffff |
| #define mmMMEA1_DRAM_WR_PRI_QUANT_PRI1_DEFAULT 0x3f3f3f3f |
| #define mmMMEA1_DRAM_WR_PRI_QUANT_PRI2_DEFAULT 0x7f7f7f7f |
| #define mmMMEA1_DRAM_WR_PRI_QUANT_PRI3_DEFAULT 0xffffffff |
| #define mmMMEA1_ADDRNORM_BASE_ADDR0_DEFAULT 0x00000000 |
| #define mmMMEA1_ADDRNORM_LIMIT_ADDR0_DEFAULT 0x00000000 |
| #define mmMMEA1_ADDRNORM_BASE_ADDR1_DEFAULT 0x00000000 |
| #define mmMMEA1_ADDRNORM_LIMIT_ADDR1_DEFAULT 0x00000000 |
| #define mmMMEA1_ADDRNORM_OFFSET_ADDR1_DEFAULT 0x00000000 |
| #define mmMMEA1_ADDRNORM_HOLE_CNTL_DEFAULT 0x00000000 |
| #define mmMMEA1_ADDRDEC_BANK_CFG_DEFAULT 0x000001ef |
| #define mmMMEA1_ADDRDEC_MISC_CFG_DEFAULT 0x3ffff000 |
| #define mmMMEA1_ADDRDECDRAM_ADDR_HASH_BANK0_DEFAULT 0x00000000 |
| #define mmMMEA1_ADDRDECDRAM_ADDR_HASH_BANK1_DEFAULT 0x00000000 |
| #define mmMMEA1_ADDRDECDRAM_ADDR_HASH_BANK2_DEFAULT 0x00000000 |
| #define mmMMEA1_ADDRDECDRAM_ADDR_HASH_BANK3_DEFAULT 0x00000000 |
| #define mmMMEA1_ADDRDECDRAM_ADDR_HASH_BANK4_DEFAULT 0x00000000 |
| #define mmMMEA1_ADDRDECDRAM_ADDR_HASH_PC_DEFAULT 0x00000000 |
| #define mmMMEA1_ADDRDECDRAM_ADDR_HASH_PC2_DEFAULT 0x00000000 |
| #define mmMMEA1_ADDRDECDRAM_ADDR_HASH_CS0_DEFAULT 0x00000000 |
| #define mmMMEA1_ADDRDECDRAM_ADDR_HASH_CS1_DEFAULT 0x00000000 |
| #define mmMMEA1_ADDRDECDRAM_HARVEST_ENABLE_DEFAULT 0x00000000 |
| #define mmMMEA1_ADDRDEC0_BASE_ADDR_CS0_DEFAULT 0x00000000 |
| #define mmMMEA1_ADDRDEC0_BASE_ADDR_CS1_DEFAULT 0x00000000 |
| #define mmMMEA1_ADDRDEC0_BASE_ADDR_CS2_DEFAULT 0x00000000 |
| #define mmMMEA1_ADDRDEC0_BASE_ADDR_CS3_DEFAULT 0x00000000 |
| #define mmMMEA1_ADDRDEC0_BASE_ADDR_SECCS0_DEFAULT 0x00000000 |
| #define mmMMEA1_ADDRDEC0_BASE_ADDR_SECCS1_DEFAULT 0x00000000 |
| #define mmMMEA1_ADDRDEC0_BASE_ADDR_SECCS2_DEFAULT 0x00000000 |
| #define mmMMEA1_ADDRDEC0_BASE_ADDR_SECCS3_DEFAULT 0x00000000 |
| #define mmMMEA1_ADDRDEC0_ADDR_MASK_CS01_DEFAULT 0xfffffffe |
| #define mmMMEA1_ADDRDEC0_ADDR_MASK_CS23_DEFAULT 0xfffffffe |
| #define mmMMEA1_ADDRDEC0_ADDR_MASK_SECCS01_DEFAULT 0xfffffffe |
| #define mmMMEA1_ADDRDEC0_ADDR_MASK_SECCS23_DEFAULT 0xfffffffe |
| #define mmMMEA1_ADDRDEC0_ADDR_CFG_CS01_DEFAULT 0x00050408 |
| #define mmMMEA1_ADDRDEC0_ADDR_CFG_CS23_DEFAULT 0x00050408 |
| #define mmMMEA1_ADDRDEC0_ADDR_SEL_CS01_DEFAULT 0x04076543 |
| #define mmMMEA1_ADDRDEC0_ADDR_SEL_CS23_DEFAULT 0x04076543 |
| #define mmMMEA1_ADDRDEC0_COL_SEL_LO_CS01_DEFAULT 0x87654321 |
| #define mmMMEA1_ADDRDEC0_COL_SEL_LO_CS23_DEFAULT 0x87654321 |
| #define mmMMEA1_ADDRDEC0_COL_SEL_HI_CS01_DEFAULT 0xa9876543 |
| #define mmMMEA1_ADDRDEC0_COL_SEL_HI_CS23_DEFAULT 0xa9876543 |
| #define mmMMEA1_ADDRDEC0_RM_SEL_CS01_DEFAULT 0x00000000 |
| #define mmMMEA1_ADDRDEC0_RM_SEL_CS23_DEFAULT 0x00000000 |
| #define mmMMEA1_ADDRDEC0_RM_SEL_SECCS01_DEFAULT 0x00000000 |
| #define mmMMEA1_ADDRDEC0_RM_SEL_SECCS23_DEFAULT 0x00000000 |
| #define mmMMEA1_ADDRDEC1_BASE_ADDR_CS0_DEFAULT 0x00000000 |
| #define mmMMEA1_ADDRDEC1_BASE_ADDR_CS1_DEFAULT 0x00000000 |
| #define mmMMEA1_ADDRDEC1_BASE_ADDR_CS2_DEFAULT 0x00000000 |
| #define mmMMEA1_ADDRDEC1_BASE_ADDR_CS3_DEFAULT 0x00000000 |
| #define mmMMEA1_ADDRDEC1_BASE_ADDR_SECCS0_DEFAULT 0x00000000 |
| #define mmMMEA1_ADDRDEC1_BASE_ADDR_SECCS1_DEFAULT 0x00000000 |
| #define mmMMEA1_ADDRDEC1_BASE_ADDR_SECCS2_DEFAULT 0x00000000 |
| #define mmMMEA1_ADDRDEC1_BASE_ADDR_SECCS3_DEFAULT 0x00000000 |
| #define mmMMEA1_ADDRDEC1_ADDR_MASK_CS01_DEFAULT 0xfffffffe |
| #define mmMMEA1_ADDRDEC1_ADDR_MASK_CS23_DEFAULT 0xfffffffe |
| #define mmMMEA1_ADDRDEC1_ADDR_MASK_SECCS01_DEFAULT 0xfffffffe |
| #define mmMMEA1_ADDRDEC1_ADDR_MASK_SECCS23_DEFAULT 0xfffffffe |
| #define mmMMEA1_ADDRDEC1_ADDR_CFG_CS01_DEFAULT 0x00050408 |
| #define mmMMEA1_ADDRDEC1_ADDR_CFG_CS23_DEFAULT 0x00050408 |
| #define mmMMEA1_ADDRDEC1_ADDR_SEL_CS01_DEFAULT 0x04076543 |
| #define mmMMEA1_ADDRDEC1_ADDR_SEL_CS23_DEFAULT 0x04076543 |
| #define mmMMEA1_ADDRDEC1_COL_SEL_LO_CS01_DEFAULT 0x87654321 |
| #define mmMMEA1_ADDRDEC1_COL_SEL_LO_CS23_DEFAULT 0x87654321 |
| #define mmMMEA1_ADDRDEC1_COL_SEL_HI_CS01_DEFAULT 0xa9876543 |
| #define mmMMEA1_ADDRDEC1_COL_SEL_HI_CS23_DEFAULT 0xa9876543 |
| #define mmMMEA1_ADDRDEC1_RM_SEL_CS01_DEFAULT 0x00000000 |
| #define mmMMEA1_ADDRDEC1_RM_SEL_CS23_DEFAULT 0x00000000 |
| #define mmMMEA1_ADDRDEC1_RM_SEL_SECCS01_DEFAULT 0x00000000 |
| #define mmMMEA1_ADDRDEC1_RM_SEL_SECCS23_DEFAULT 0x00000000 |
| #define mmMMEA1_IO_RD_CLI2GRP_MAP0_DEFAULT 0xe4e4e4e4 |
| #define mmMMEA1_IO_RD_CLI2GRP_MAP1_DEFAULT 0xe4e4e4e4 |
| #define mmMMEA1_IO_WR_CLI2GRP_MAP0_DEFAULT 0xe4e4e4e4 |
| #define mmMMEA1_IO_WR_CLI2GRP_MAP1_DEFAULT 0xe4e4e4e4 |
| #define mmMMEA1_IO_RD_COMBINE_FLUSH_DEFAULT 0x00007777 |
| #define mmMMEA1_IO_WR_COMBINE_FLUSH_DEFAULT 0x00007777 |
| #define mmMMEA1_IO_GROUP_BURST_DEFAULT 0x1f031f03 |
| #define mmMMEA1_IO_RD_PRI_AGE_DEFAULT 0x00db6249 |
| #define mmMMEA1_IO_WR_PRI_AGE_DEFAULT 0x00db6249 |
| #define mmMMEA1_IO_RD_PRI_QUEUING_DEFAULT 0x00000db6 |
| #define mmMMEA1_IO_WR_PRI_QUEUING_DEFAULT 0x00000db6 |
| #define mmMMEA1_IO_RD_PRI_FIXED_DEFAULT 0x00000924 |
| #define mmMMEA1_IO_WR_PRI_FIXED_DEFAULT 0x00000924 |
| #define mmMMEA1_IO_RD_PRI_URGENCY_DEFAULT 0x00000492 |
| #define mmMMEA1_IO_WR_PRI_URGENCY_DEFAULT 0x00000492 |
| #define mmMMEA1_IO_RD_PRI_URGENCY_MASK_DEFAULT 0xffffffff |
| #define mmMMEA1_IO_WR_PRI_URGENCY_MASK_DEFAULT 0xffffffff |
| #define mmMMEA1_IO_RD_PRI_QUANT_PRI1_DEFAULT 0x3f3f3f3f |
| #define mmMMEA1_IO_RD_PRI_QUANT_PRI2_DEFAULT 0x7f7f7f7f |
| #define mmMMEA1_IO_RD_PRI_QUANT_PRI3_DEFAULT 0xffffffff |
| #define mmMMEA1_IO_WR_PRI_QUANT_PRI1_DEFAULT 0x3f3f3f3f |
| #define mmMMEA1_IO_WR_PRI_QUANT_PRI2_DEFAULT 0x7f7f7f7f |
| #define mmMMEA1_IO_WR_PRI_QUANT_PRI3_DEFAULT 0xffffffff |
| #define mmMMEA1_SDP_ARB_DRAM_DEFAULT 0x00102040 |
| #define mmMMEA1_SDP_ARB_FINAL_DEFAULT 0x00007fff |
| #define mmMMEA1_SDP_DRAM_PRIORITY_DEFAULT 0x00000000 |
| #define mmMMEA1_SDP_IO_PRIORITY_DEFAULT 0x00000000 |
| #define mmMMEA1_SDP_CREDITS_DEFAULT 0x000100bf |
| #define mmMMEA1_SDP_TAG_RESERVE0_DEFAULT 0x00000000 |
| #define mmMMEA1_SDP_TAG_RESERVE1_DEFAULT 0x00000000 |
| #define mmMMEA1_SDP_VCC_RESERVE0_DEFAULT 0x00000000 |
| #define mmMMEA1_SDP_VCC_RESERVE1_DEFAULT 0x00000000 |
| #define mmMMEA1_SDP_VCD_RESERVE0_DEFAULT 0x00000000 |
| #define mmMMEA1_SDP_VCD_RESERVE1_DEFAULT 0x00000000 |
| #define mmMMEA1_SDP_REQ_CNTL_DEFAULT 0x0000000f |
| #define mmMMEA1_MISC_DEFAULT 0x00180130 |
| #define mmMMEA1_LATENCY_SAMPLING_DEFAULT 0x00000000 |
| #define mmMMEA1_PERFCOUNTER_LO_DEFAULT 0x00000000 |
| #define mmMMEA1_PERFCOUNTER_HI_DEFAULT 0x00000000 |
| #define mmMMEA1_PERFCOUNTER0_CFG_DEFAULT 0x00000000 |
| #define mmMMEA1_PERFCOUNTER1_CFG_DEFAULT 0x00000000 |
| #define mmMMEA1_PERFCOUNTER_RSLT_CNTL_DEFAULT 0x04000000 |
| #define mmMMEA1_EDC_CNT_DEFAULT 0x00000000 |
| #define mmMMEA1_EDC_CNT2_DEFAULT 0x00000000 |
| #define mmMMEA1_DSM_CNTL_DEFAULT 0x00000000 |
| #define mmMMEA1_DSM_CNTLA_DEFAULT 0x00000000 |
| #define mmMMEA1_DSM_CNTLB_DEFAULT 0x00000000 |
| #define mmMMEA1_DSM_CNTL2_DEFAULT 0x00000000 |
| #define mmMMEA1_DSM_CNTL2A_DEFAULT 0x00000000 |
| #define mmMMEA1_DSM_CNTL2B_DEFAULT 0x00000000 |
| #define mmMMEA1_CGTT_CLK_CTRL_DEFAULT 0x00000100 |
| #define mmMMEA1_EDC_MODE_DEFAULT 0x00000000 |
| #define mmMMEA1_ERR_STATUS_DEFAULT 0x00000000 |
| #define mmMMEA1_MISC2_DEFAULT 0x00000000 |
| |
| |
| // addressBlock: mmhub_pctldec |
| #define mmPCTL_MISC_DEFAULT 0x00000889 |
| #define mmPCTL_MMHUB_DEEPSLEEP_DEFAULT 0x00000000 |
| #define mmPCTL_MMHUB_DEEPSLEEP_OVERRIDE_DEFAULT 0x00000000 |
| #define mmPCTL_PG_IGNORE_DEEPSLEEP_DEFAULT 0x00000000 |
| #define mmPCTL_PG_DAGB_DEFAULT 0x00000000 |
| #define mmPCTL0_RENG_RAM_INDEX_DEFAULT 0x00000000 |
| #define mmPCTL0_RENG_RAM_DATA_DEFAULT 0x00000000 |
| #define mmPCTL0_RENG_EXECUTE_DEFAULT 0x00000000 |
| #define mmPCTL0_MISC_DEFAULT 0x00001000 |
| #define mmPCTL0_STCTRL_REGISTER_SAVE_RANGE0_DEFAULT 0x00000000 |
| #define mmPCTL0_STCTRL_REGISTER_SAVE_RANGE1_DEFAULT 0x00000000 |
| #define mmPCTL0_STCTRL_REGISTER_SAVE_RANGE2_DEFAULT 0x00000000 |
| #define mmPCTL0_STCTRL_REGISTER_SAVE_EXCL_SET_DEFAULT 0xffffffff |
| #define mmPCTL0_STCTRL_REGISTER_SAVE_EXCL_SET1_DEFAULT 0xffffffff |
| #define mmPCTL1_RENG_RAM_INDEX_DEFAULT 0x00000000 |
| #define mmPCTL1_RENG_RAM_DATA_DEFAULT 0x00000000 |
| #define mmPCTL1_RENG_EXECUTE_DEFAULT 0x00000000 |
| #define mmPCTL1_MISC_DEFAULT 0x00000800 |
| #define mmPCTL1_STCTRL_REGISTER_SAVE_RANGE0_DEFAULT 0x061f05a0 |
| #define mmPCTL1_STCTRL_REGISTER_SAVE_RANGE1_DEFAULT 0x08590800 |
| #define mmPCTL1_STCTRL_REGISTER_SAVE_RANGE2_DEFAULT 0x00000000 |
| #define mmPCTL1_STCTRL_REGISTER_SAVE_EXCL_SET_DEFAULT 0xffffffff |
| #define mmPCTL1_STCTRL_REGISTER_SAVE_EXCL_SET1_DEFAULT 0xffffffff |
| #define mmPCTL2_RENG_RAM_INDEX_DEFAULT 0x00000000 |
| #define mmPCTL2_RENG_RAM_DATA_DEFAULT 0x00000000 |
| #define mmPCTL2_RENG_EXECUTE_DEFAULT 0x00000000 |
| #define mmPCTL2_MISC_DEFAULT 0x00000800 |
| #define mmPCTL2_STCTRL_REGISTER_SAVE_RANGE0_DEFAULT 0x069f0620 |
| #define mmPCTL2_STCTRL_REGISTER_SAVE_RANGE1_DEFAULT 0x08b3085a |
| #define mmPCTL2_STCTRL_REGISTER_SAVE_RANGE2_DEFAULT 0x00000000 |
| #define mmPCTL2_STCTRL_REGISTER_SAVE_EXCL_SET_DEFAULT 0xffffffff |
| #define mmPCTL2_STCTRL_REGISTER_SAVE_EXCL_SET1_DEFAULT 0xffffffff |
| |
| |
| // addressBlock: mmhub_l1tlb_vml1dec |
| #define mmMC_VM_MX_L1_TLB0_STATUS_DEFAULT 0x00000000 |
| #define mmMC_VM_MX_L1_TLB1_STATUS_DEFAULT 0x00000000 |
| #define mmMC_VM_MX_L1_TLB2_STATUS_DEFAULT 0x00000000 |
| #define mmMC_VM_MX_L1_TLB3_STATUS_DEFAULT 0x00000000 |
| #define mmMC_VM_MX_L1_TLB4_STATUS_DEFAULT 0x00000000 |
| #define mmMC_VM_MX_L1_TLB5_STATUS_DEFAULT 0x00000000 |
| #define mmMC_VM_MX_L1_TLB6_STATUS_DEFAULT 0x00000000 |
| #define mmMC_VM_MX_L1_TLB7_STATUS_DEFAULT 0x00000000 |
| |
| |
| // addressBlock: mmhub_l1tlb_vml1pldec |
| #define mmMC_VM_MX_L1_PERFCOUNTER0_CFG_DEFAULT 0x00000000 |
| #define mmMC_VM_MX_L1_PERFCOUNTER1_CFG_DEFAULT 0x00000000 |
| #define mmMC_VM_MX_L1_PERFCOUNTER2_CFG_DEFAULT 0x00000000 |
| #define mmMC_VM_MX_L1_PERFCOUNTER3_CFG_DEFAULT 0x00000000 |
| #define mmMC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL_DEFAULT 0x04000000 |
| |
| |
| // addressBlock: mmhub_l1tlb_vml1prdec |
| #define mmMC_VM_MX_L1_PERFCOUNTER_LO_DEFAULT 0x00000000 |
| #define mmMC_VM_MX_L1_PERFCOUNTER_HI_DEFAULT 0x00000000 |
| |
| |
| // addressBlock: mmhub_utcl2_atcl2dec |
| #define mmATC_L2_CNTL_DEFAULT 0x000001c9 |
| #define mmATC_L2_CNTL2_DEFAULT 0x00000100 |
| #define mmATC_L2_CACHE_DATA0_DEFAULT 0x00000000 |
| #define mmATC_L2_CACHE_DATA1_DEFAULT 0x00000000 |
| #define mmATC_L2_CACHE_DATA2_DEFAULT 0x00000000 |
| #define mmATC_L2_CNTL3_DEFAULT 0x000001f8 |
| #define mmATC_L2_STATUS_DEFAULT 0x00000000 |
| #define mmATC_L2_STATUS2_DEFAULT 0x00000000 |
| #define mmATC_L2_MISC_CG_DEFAULT 0x00000200 |
| #define mmATC_L2_MEM_POWER_LS_DEFAULT 0x00000208 |
| #define mmATC_L2_CGTT_CLK_CTRL_DEFAULT 0x00000080 |
| |
| |
| // addressBlock: mmhub_utcl2_vml2pfdec |
| #define mmVM_L2_CNTL_DEFAULT 0x00080602 |
| #define mmVM_L2_CNTL2_DEFAULT 0x00000000 |
| #define mmVM_L2_CNTL3_DEFAULT 0x80100007 |
| #define mmVM_L2_STATUS_DEFAULT 0x00000000 |
| #define mmVM_DUMMY_PAGE_FAULT_CNTL_DEFAULT 0x00000090 |
| #define mmVM_DUMMY_PAGE_FAULT_ADDR_LO32_DEFAULT 0x00000000 |
| #define mmVM_DUMMY_PAGE_FAULT_ADDR_HI32_DEFAULT 0x00000000 |
| #define mmVM_L2_PROTECTION_FAULT_CNTL_DEFAULT 0x3ffffffc |
| #define mmVM_L2_PROTECTION_FAULT_CNTL2_DEFAULT 0x000a0000 |
| #define mmVM_L2_PROTECTION_FAULT_MM_CNTL3_DEFAULT 0xffffffff |
| #define mmVM_L2_PROTECTION_FAULT_MM_CNTL4_DEFAULT 0xffffffff |
| #define mmVM_L2_PROTECTION_FAULT_STATUS_DEFAULT 0x00000000 |
| #define mmVM_L2_PROTECTION_FAULT_ADDR_LO32_DEFAULT 0x00000000 |
| #define mmVM_L2_PROTECTION_FAULT_ADDR_HI32_DEFAULT 0x00000000 |
| #define mmVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32_DEFAULT 0x00000000 |
| #define mmVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32_DEFAULT 0x00000000 |
| #define mmVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32_DEFAULT 0x00000000 |
| #define mmVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32_DEFAULT 0x00000000 |
| #define mmVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32_DEFAULT 0x00000000 |
| #define mmVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32_DEFAULT 0x00000000 |
| #define mmVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32_DEFAULT 0x00000000 |
| #define mmVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32_DEFAULT 0x00000000 |
| #define mmVM_L2_CNTL4_DEFAULT 0x000000c1 |
| #define mmVM_L2_MM_GROUP_RT_CLASSES_DEFAULT 0x00000000 |
| #define mmVM_L2_BANK_SELECT_RESERVED_CID_DEFAULT 0x00000000 |
| #define mmVM_L2_BANK_SELECT_RESERVED_CID2_DEFAULT 0x00000000 |
| #define mmVM_L2_CACHE_PARITY_CNTL_DEFAULT 0x00000000 |
| #define mmVM_L2_CGTT_CLK_CTRL_DEFAULT 0x00000080 |
| |
| |
| // addressBlock: mmhub_utcl2_vml2vcdec |
| #define mmVM_CONTEXT0_CNTL_DEFAULT 0x007ffe80 |
| #define mmVM_CONTEXT1_CNTL_DEFAULT 0x007ffe80 |
| #define mmVM_CONTEXT2_CNTL_DEFAULT 0x007ffe80 |
| #define mmVM_CONTEXT3_CNTL_DEFAULT 0x007ffe80 |
| #define mmVM_CONTEXT4_CNTL_DEFAULT 0x007ffe80 |
| #define mmVM_CONTEXT5_CNTL_DEFAULT 0x007ffe80 |
| #define mmVM_CONTEXT6_CNTL_DEFAULT 0x007ffe80 |
| #define mmVM_CONTEXT7_CNTL_DEFAULT 0x007ffe80 |
| #define mmVM_CONTEXT8_CNTL_DEFAULT 0x007ffe80 |
| #define mmVM_CONTEXT9_CNTL_DEFAULT 0x007ffe80 |
| #define mmVM_CONTEXT10_CNTL_DEFAULT 0x007ffe80 |
| #define mmVM_CONTEXT11_CNTL_DEFAULT 0x007ffe80 |
| #define mmVM_CONTEXT12_CNTL_DEFAULT 0x007ffe80 |
| #define mmVM_CONTEXT13_CNTL_DEFAULT 0x007ffe80 |
| #define mmVM_CONTEXT14_CNTL_DEFAULT 0x007ffe80 |
| #define mmVM_CONTEXT15_CNTL_DEFAULT 0x007ffe80 |
| #define mmVM_CONTEXTS_DISABLE_DEFAULT 0x00000000 |
| #define mmVM_INVALIDATE_ENG0_SEM_DEFAULT 0x00000000 |
| #define mmVM_INVALIDATE_ENG1_SEM_DEFAULT 0x00000000 |
| #define mmVM_INVALIDATE_ENG2_SEM_DEFAULT 0x00000000 |
| #define mmVM_INVALIDATE_ENG3_SEM_DEFAULT 0x00000000 |
| #define mmVM_INVALIDATE_ENG4_SEM_DEFAULT 0x00000000 |
| #define mmVM_INVALIDATE_ENG5_SEM_DEFAULT 0x00000000 |
| #define mmVM_INVALIDATE_ENG6_SEM_DEFAULT 0x00000000 |
| #define mmVM_INVALIDATE_ENG7_SEM_DEFAULT 0x00000000 |
| #define mmVM_INVALIDATE_ENG8_SEM_DEFAULT 0x00000000 |
| #define mmVM_INVALIDATE_ENG9_SEM_DEFAULT 0x00000000 |
| #define mmVM_INVALIDATE_ENG10_SEM_DEFAULT 0x00000000 |
| #define mmVM_INVALIDATE_ENG11_SEM_DEFAULT 0x00000000 |
| #define mmVM_INVALIDATE_ENG12_SEM_DEFAULT 0x00000000 |
| #define mmVM_INVALIDATE_ENG13_SEM_DEFAULT 0x00000000 |
| #define mmVM_INVALIDATE_ENG14_SEM_DEFAULT 0x00000000 |
| #define mmVM_INVALIDATE_ENG15_SEM_DEFAULT 0x00000000 |
| #define mmVM_INVALIDATE_ENG16_SEM_DEFAULT 0x00000000 |
| #define mmVM_INVALIDATE_ENG17_SEM_DEFAULT 0x00000000 |
| #define mmVM_INVALIDATE_ENG0_REQ_DEFAULT 0x017c0000 |
| #define mmVM_INVALIDATE_ENG1_REQ_DEFAULT 0x017c0000 |
| #define mmVM_INVALIDATE_ENG2_REQ_DEFAULT 0x017c0000 |
| #define mmVM_INVALIDATE_ENG3_REQ_DEFAULT 0x017c0000 |
| #define mmVM_INVALIDATE_ENG4_REQ_DEFAULT 0x017c0000 |
| #define mmVM_INVALIDATE_ENG5_REQ_DEFAULT 0x017c0000 |
| #define mmVM_INVALIDATE_ENG6_REQ_DEFAULT 0x017c0000 |
| #define mmVM_INVALIDATE_ENG7_REQ_DEFAULT 0x017c0000 |
| #define mmVM_INVALIDATE_ENG8_REQ_DEFAULT 0x017c0000 |
| #define mmVM_INVALIDATE_ENG9_REQ_DEFAULT 0x017c0000 |
| #define mmVM_INVALIDATE_ENG10_REQ_DEFAULT 0x017c0000 |
| #define mmVM_INVALIDATE_ENG11_REQ_DEFAULT 0x017c0000 |
| #define mmVM_INVALIDATE_ENG12_REQ_DEFAULT 0x017c0000 |
| #define mmVM_INVALIDATE_ENG13_REQ_DEFAULT 0x017c0000 |
| #define mmVM_INVALIDATE_ENG14_REQ_DEFAULT 0x017c0000 |
| #define mmVM_INVALIDATE_ENG15_REQ_DEFAULT 0x017c0000 |
| #define mmVM_INVALIDATE_ENG16_REQ_DEFAULT 0x017c0000 |
| #define mmVM_INVALIDATE_ENG17_REQ_DEFAULT 0x017c0000 |
| #define mmVM_INVALIDATE_ENG0_ACK_DEFAULT 0x00000000 |
| #define mmVM_INVALIDATE_ENG1_ACK_DEFAULT 0x00000000 |
| #define mmVM_INVALIDATE_ENG2_ACK_DEFAULT 0x00000000 |
| #define mmVM_INVALIDATE_ENG3_ACK_DEFAULT 0x00000000 |
| #define mmVM_INVALIDATE_ENG4_ACK_DEFAULT 0x00000000 |
| #define mmVM_INVALIDATE_ENG5_ACK_DEFAULT 0x00000000 |
| #define mmVM_INVALIDATE_ENG6_ACK_DEFAULT 0x00000000 |
| #define mmVM_INVALIDATE_ENG7_ACK_DEFAULT 0x00000000 |
| #define mmVM_INVALIDATE_ENG8_ACK_DEFAULT 0x00000000 |
| #define mmVM_INVALIDATE_ENG9_ACK_DEFAULT 0x00000000 |
| #define mmVM_INVALIDATE_ENG10_ACK_DEFAULT 0x00000000 |
| #define mmVM_INVALIDATE_ENG11_ACK_DEFAULT 0x00000000 |
| #define mmVM_INVALIDATE_ENG12_ACK_DEFAULT 0x00000000 |
| #define mmVM_INVALIDATE_ENG13_ACK_DEFAULT 0x00000000 |
| #define mmVM_INVALIDATE_ENG14_ACK_DEFAULT 0x00000000 |
| #define mmVM_INVALIDATE_ENG15_ACK_DEFAULT 0x00000000 |
| #define mmVM_INVALIDATE_ENG16_ACK_DEFAULT 0x00000000 |
| #define mmVM_INVALIDATE_ENG17_ACK_DEFAULT 0x00000000 |
| #define mmVM_INVALIDATE_ENG0_ADDR_RANGE_LO32_DEFAULT 0x00000000 |
| #define mmVM_INVALIDATE_ENG0_ADDR_RANGE_HI32_DEFAULT 0x00000000 |
| #define mmVM_INVALIDATE_ENG1_ADDR_RANGE_LO32_DEFAULT 0x00000000 |
| #define mmVM_INVALIDATE_ENG1_ADDR_RANGE_HI32_DEFAULT 0x00000000 |
| #define mmVM_INVALIDATE_ENG2_ADDR_RANGE_LO32_DEFAULT 0x00000000 |
| #define mmVM_INVALIDATE_ENG2_ADDR_RANGE_HI32_DEFAULT 0x00000000 |
| #define mmVM_INVALIDATE_ENG3_ADDR_RANGE_LO32_DEFAULT 0x00000000 |
| #define mmVM_INVALIDATE_ENG3_ADDR_RANGE_HI32_DEFAULT 0x00000000 |
| #define mmVM_INVALIDATE_ENG4_ADDR_RANGE_LO32_DEFAULT 0x00000000 |
| #define mmVM_INVALIDATE_ENG4_ADDR_RANGE_HI32_DEFAULT 0x00000000 |
| #define mmVM_INVALIDATE_ENG5_ADDR_RANGE_LO32_DEFAULT 0x00000000 |
| #define mmVM_INVALIDATE_ENG5_ADDR_RANGE_HI32_DEFAULT 0x00000000 |
| #define mmVM_INVALIDATE_ENG6_ADDR_RANGE_LO32_DEFAULT 0x00000000 |
| #define mmVM_INVALIDATE_ENG6_ADDR_RANGE_HI32_DEFAULT 0x00000000 |
| #define mmVM_INVALIDATE_ENG7_ADDR_RANGE_LO32_DEFAULT 0x00000000 |
| #define mmVM_INVALIDATE_ENG7_ADDR_RANGE_HI32_DEFAULT 0x00000000 |
| #define mmVM_INVALIDATE_ENG8_ADDR_RANGE_LO32_DEFAULT 0x00000000 |
| #define mmVM_INVALIDATE_ENG8_ADDR_RANGE_HI32_DEFAULT 0x00000000 |
| #define mmVM_INVALIDATE_ENG9_ADDR_RANGE_LO32_DEFAULT 0x00000000 |
| #define mmVM_INVALIDATE_ENG9_ADDR_RANGE_HI32_DEFAULT 0x00000000 |
| #define mmVM_INVALIDATE_ENG10_ADDR_RANGE_LO32_DEFAULT 0x00000000 |
| #define mmVM_INVALIDATE_ENG10_ADDR_RANGE_HI32_DEFAULT 0x00000000 |
| #define mmVM_INVALIDATE_ENG11_ADDR_RANGE_LO32_DEFAULT 0x00000000 |
| #define mmVM_INVALIDATE_ENG11_ADDR_RANGE_HI32_DEFAULT 0x00000000 |
| #define mmVM_INVALIDATE_ENG12_ADDR_RANGE_LO32_DEFAULT 0x00000000 |
| #define mmVM_INVALIDATE_ENG12_ADDR_RANGE_HI32_DEFAULT 0x00000000 |
| #define mmVM_INVALIDATE_ENG13_ADDR_RANGE_LO32_DEFAULT 0x00000000 |
| #define mmVM_INVALIDATE_ENG13_ADDR_RANGE_HI32_DEFAULT 0x00000000 |
| #define mmVM_INVALIDATE_ENG14_ADDR_RANGE_LO32_DEFAULT 0x00000000 |
| #define mmVM_INVALIDATE_ENG14_ADDR_RANGE_HI32_DEFAULT 0x00000000 |
| #define mmVM_INVALIDATE_ENG15_ADDR_RANGE_LO32_DEFAULT 0x00000000 |
| #define mmVM_INVALIDATE_ENG15_ADDR_RANGE_HI32_DEFAULT 0x00000000 |
| #define mmVM_INVALIDATE_ENG16_ADDR_RANGE_LO32_DEFAULT 0x00000000 |
| #define mmVM_INVALIDATE_ENG16_ADDR_RANGE_HI32_DEFAULT 0x00000000 |
| #define mmVM_INVALIDATE_ENG17_ADDR_RANGE_LO32_DEFAULT 0x00000000 |
| #define mmVM_INVALIDATE_ENG17_ADDR_RANGE_HI32_DEFAULT 0x00000000 |
| #define mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32_DEFAULT 0x00000000 |
| #define mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32_DEFAULT 0x00000000 |
| #define mmVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32_DEFAULT 0x00000000 |
| #define mmVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32_DEFAULT 0x00000000 |
| #define mmVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32_DEFAULT 0x00000000 |
| #define mmVM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32_DEFAULT 0x00000000 |
| #define mmVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32_DEFAULT 0x00000000 |
| #define mmVM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32_DEFAULT 0x00000000 |
| #define mmVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32_DEFAULT 0x00000000 |
| #define mmVM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32_DEFAULT 0x00000000 |
| #define mmVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32_DEFAULT 0x00000000 |
| #define mmVM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32_DEFAULT 0x00000000 |
| #define mmVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32_DEFAULT 0x00000000 |
| #define mmVM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32_DEFAULT 0x00000000 |
| #define mmVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32_DEFAULT 0x00000000 |
| #define mmVM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32_DEFAULT 0x00000000 |
| #define mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32_DEFAULT 0x00000000 |
| #define mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32_DEFAULT 0x00000000 |
| #define mmVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32_DEFAULT 0x00000000 |
| #define mmVM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32_DEFAULT 0x00000000 |
| #define mmVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32_DEFAULT 0x00000000 |
| #define mmVM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32_DEFAULT 0x00000000 |
| #define mmVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32_DEFAULT 0x00000000 |
| #define mmVM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32_DEFAULT 0x00000000 |
| #define mmVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32_DEFAULT 0x00000000 |
| #define mmVM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32_DEFAULT 0x00000000 |
| #define mmVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32_DEFAULT 0x00000000 |
| #define mmVM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32_DEFAULT 0x00000000 |
| #define mmVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32_DEFAULT 0x00000000 |
| #define mmVM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32_DEFAULT 0x00000000 |
| #define mmVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32_DEFAULT 0x00000000 |
| #define mmVM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32_DEFAULT 0x00000000 |
| #define mmVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32_DEFAULT 0x00000000 |
| #define mmVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32_DEFAULT 0x00000000 |
| #define mmVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32_DEFAULT 0x00000000 |
| #define mmVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32_DEFAULT 0x00000000 |
| #define mmVM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32_DEFAULT 0x00000000 |
| #define mmVM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32_DEFAULT 0x00000000 |
| #define mmVM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32_DEFAULT 0x00000000 |
| #define mmVM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32_DEFAULT 0x00000000 |
| #define mmVM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32_DEFAULT 0x00000000 |
| #define mmVM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32_DEFAULT 0x00000000 |
| #define mmVM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32_DEFAULT 0x00000000 |
| #define mmVM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32_DEFAULT 0x00000000 |
| #define mmVM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32_DEFAULT 0x00000000 |
| #define mmVM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32_DEFAULT 0x00000000 |
| #define mmVM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32_DEFAULT 0x00000000 |
| #define mmVM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32_DEFAULT 0x00000000 |
| #define mmVM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32_DEFAULT 0x00000000 |
| #define mmVM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32_DEFAULT 0x00000000 |
| #define mmVM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32_DEFAULT 0x00000000 |
| #define mmVM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32_DEFAULT 0x00000000 |
| #define mmVM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32_DEFAULT 0x00000000 |
| #define mmVM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32_DEFAULT 0x00000000 |
| #define mmVM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32_DEFAULT 0x00000000 |
| #define mmVM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32_DEFAULT 0x00000000 |
| #define mmVM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32_DEFAULT 0x00000000 |
| #define mmVM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32_DEFAULT 0x00000000 |
| #define mmVM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32_DEFAULT 0x00000000 |
| #define mmVM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32_DEFAULT 0x00000000 |
| #define mmVM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32_DEFAULT 0x00000000 |
| #define mmVM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32_DEFAULT 0x00000000 |
| #define mmVM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32_DEFAULT 0x00000000 |
| #define mmVM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32_DEFAULT 0x00000000 |
| #define mmVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32_DEFAULT 0x00000000 |
| #define mmVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32_DEFAULT 0x00000000 |
| #define mmVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32_DEFAULT 0x00000000 |
| #define mmVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32_DEFAULT 0x00000000 |
| #define mmVM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32_DEFAULT 0x00000000 |
| #define mmVM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32_DEFAULT 0x00000000 |
| #define mmVM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32_DEFAULT 0x00000000 |
| #define mmVM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32_DEFAULT 0x00000000 |
| #define mmVM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32_DEFAULT 0x00000000 |
| #define mmVM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32_DEFAULT 0x00000000 |
| #define mmVM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32_DEFAULT 0x00000000 |
| #define mmVM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32_DEFAULT 0x00000000 |
| #define mmVM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32_DEFAULT 0x00000000 |
| #define mmVM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32_DEFAULT 0x00000000 |
| #define mmVM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32_DEFAULT 0x00000000 |
| #define mmVM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32_DEFAULT 0x00000000 |
| #define mmVM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32_DEFAULT 0x00000000 |
| #define mmVM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32_DEFAULT 0x00000000 |
| #define mmVM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32_DEFAULT 0x00000000 |
| #define mmVM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32_DEFAULT 0x00000000 |
| #define mmVM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32_DEFAULT 0x00000000 |
| #define mmVM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32_DEFAULT 0x00000000 |
| #define mmVM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32_DEFAULT 0x00000000 |
| #define mmVM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32_DEFAULT 0x00000000 |
| #define mmVM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32_DEFAULT 0x00000000 |
| #define mmVM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32_DEFAULT 0x00000000 |
| #define mmVM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32_DEFAULT 0x00000000 |
| #define mmVM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32_DEFAULT 0x00000000 |
| #define mmVM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32_DEFAULT 0x00000000 |
| #define mmVM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32_DEFAULT 0x00000000 |
| #define mmVM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32_DEFAULT 0x00000000 |
| #define mmVM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32_DEFAULT 0x00000000 |
| |
| |
| // addressBlock: mmhub_utcl2_vml2pldec |
| #define mmMC_VM_L2_PERFCOUNTER0_CFG_DEFAULT 0x00000000 |
| #define mmMC_VM_L2_PERFCOUNTER1_CFG_DEFAULT 0x00000000 |
| #define mmMC_VM_L2_PERFCOUNTER2_CFG_DEFAULT 0x00000000 |
| #define mmMC_VM_L2_PERFCOUNTER3_CFG_DEFAULT 0x00000000 |
| #define mmMC_VM_L2_PERFCOUNTER4_CFG_DEFAULT 0x00000000 |
| #define mmMC_VM_L2_PERFCOUNTER5_CFG_DEFAULT 0x00000000 |
| #define mmMC_VM_L2_PERFCOUNTER6_CFG_DEFAULT 0x00000000 |
| #define mmMC_VM_L2_PERFCOUNTER7_CFG_DEFAULT 0x00000000 |
| #define mmMC_VM_L2_PERFCOUNTER_RSLT_CNTL_DEFAULT 0x04000000 |
| |
| |
| // addressBlock: mmhub_utcl2_vml2prdec |
| #define mmMC_VM_L2_PERFCOUNTER_LO_DEFAULT 0x00000000 |
| #define mmMC_VM_L2_PERFCOUNTER_HI_DEFAULT 0x00000000 |
| |
| |
| // addressBlock: mmhub_utcl2_vmsharedhvdec |
| #define mmMC_VM_FB_SIZE_OFFSET_VF0_DEFAULT 0x00000000 |
| #define mmMC_VM_FB_SIZE_OFFSET_VF1_DEFAULT 0x00000000 |
| #define mmMC_VM_FB_SIZE_OFFSET_VF2_DEFAULT 0x00000000 |
| #define mmMC_VM_FB_SIZE_OFFSET_VF3_DEFAULT 0x00000000 |
| #define mmMC_VM_FB_SIZE_OFFSET_VF4_DEFAULT 0x00000000 |
| #define mmMC_VM_FB_SIZE_OFFSET_VF5_DEFAULT 0x00000000 |
| #define mmMC_VM_FB_SIZE_OFFSET_VF6_DEFAULT 0x00000000 |
| #define mmMC_VM_FB_SIZE_OFFSET_VF7_DEFAULT 0x00000000 |
| #define mmMC_VM_FB_SIZE_OFFSET_VF8_DEFAULT 0x00000000 |
| #define mmMC_VM_FB_SIZE_OFFSET_VF9_DEFAULT 0x00000000 |
| #define mmMC_VM_FB_SIZE_OFFSET_VF10_DEFAULT 0x00000000 |
| #define mmMC_VM_FB_SIZE_OFFSET_VF11_DEFAULT 0x00000000 |
| #define mmMC_VM_FB_SIZE_OFFSET_VF12_DEFAULT 0x00000000 |
| #define mmMC_VM_FB_SIZE_OFFSET_VF13_DEFAULT 0x00000000 |
| #define mmMC_VM_FB_SIZE_OFFSET_VF14_DEFAULT 0x00000000 |
| #define mmMC_VM_FB_SIZE_OFFSET_VF15_DEFAULT 0x00000000 |
| #define mmVM_IOMMU_MMIO_CNTRL_1_DEFAULT 0x00000100 |
| #define mmMC_VM_MARC_BASE_LO_0_DEFAULT 0x00000000 |
| #define mmMC_VM_MARC_BASE_LO_1_DEFAULT 0x00000000 |
| #define mmMC_VM_MARC_BASE_LO_2_DEFAULT 0x00000000 |
| #define mmMC_VM_MARC_BASE_LO_3_DEFAULT 0x00000000 |
| #define mmMC_VM_MARC_BASE_HI_0_DEFAULT 0x00000000 |
| #define mmMC_VM_MARC_BASE_HI_1_DEFAULT 0x00000000 |
| #define mmMC_VM_MARC_BASE_HI_2_DEFAULT 0x00000000 |
| #define mmMC_VM_MARC_BASE_HI_3_DEFAULT 0x00000000 |
| #define mmMC_VM_MARC_RELOC_LO_0_DEFAULT 0x00000000 |
| #define mmMC_VM_MARC_RELOC_LO_1_DEFAULT 0x00000000 |
| #define mmMC_VM_MARC_RELOC_LO_2_DEFAULT 0x00000000 |
| #define mmMC_VM_MARC_RELOC_LO_3_DEFAULT 0x00000000 |
| #define mmMC_VM_MARC_RELOC_HI_0_DEFAULT 0x00000000 |
| #define mmMC_VM_MARC_RELOC_HI_1_DEFAULT 0x00000000 |
| #define mmMC_VM_MARC_RELOC_HI_2_DEFAULT 0x00000000 |
| #define mmMC_VM_MARC_RELOC_HI_3_DEFAULT 0x00000000 |
| #define mmMC_VM_MARC_LEN_LO_0_DEFAULT 0x00000000 |
| #define mmMC_VM_MARC_LEN_LO_1_DEFAULT 0x00000000 |
| #define mmMC_VM_MARC_LEN_LO_2_DEFAULT 0x00000000 |
| #define mmMC_VM_MARC_LEN_LO_3_DEFAULT 0x00000000 |
| #define mmMC_VM_MARC_LEN_HI_0_DEFAULT 0x00000000 |
| #define mmMC_VM_MARC_LEN_HI_1_DEFAULT 0x00000000 |
| #define mmMC_VM_MARC_LEN_HI_2_DEFAULT 0x00000000 |
| #define mmMC_VM_MARC_LEN_HI_3_DEFAULT 0x00000000 |
| #define mmVM_IOMMU_CONTROL_REGISTER_DEFAULT 0x00000000 |
| #define mmVM_IOMMU_PERFORMANCE_OPTIMIZATION_CONTROL_REGISTER_DEFAULT 0x00000000 |
| #define mmVM_PCIE_ATS_CNTL_DEFAULT 0x00000000 |
| #define mmVM_PCIE_ATS_CNTL_VF_0_DEFAULT 0x00000000 |
| #define mmVM_PCIE_ATS_CNTL_VF_1_DEFAULT 0x00000000 |
| #define mmVM_PCIE_ATS_CNTL_VF_2_DEFAULT 0x00000000 |
| #define mmVM_PCIE_ATS_CNTL_VF_3_DEFAULT 0x00000000 |
| #define mmVM_PCIE_ATS_CNTL_VF_4_DEFAULT 0x00000000 |
| #define mmVM_PCIE_ATS_CNTL_VF_5_DEFAULT 0x00000000 |
| #define mmVM_PCIE_ATS_CNTL_VF_6_DEFAULT 0x00000000 |
| #define mmVM_PCIE_ATS_CNTL_VF_7_DEFAULT 0x00000000 |
| #define mmVM_PCIE_ATS_CNTL_VF_8_DEFAULT 0x00000000 |
| #define mmVM_PCIE_ATS_CNTL_VF_9_DEFAULT 0x00000000 |
| #define mmVM_PCIE_ATS_CNTL_VF_10_DEFAULT 0x00000000 |
| #define mmVM_PCIE_ATS_CNTL_VF_11_DEFAULT 0x00000000 |
| #define mmVM_PCIE_ATS_CNTL_VF_12_DEFAULT 0x00000000 |
| #define mmVM_PCIE_ATS_CNTL_VF_13_DEFAULT 0x00000000 |
| #define mmVM_PCIE_ATS_CNTL_VF_14_DEFAULT 0x00000000 |
| #define mmVM_PCIE_ATS_CNTL_VF_15_DEFAULT 0x00000000 |
| #define mmUTCL2_CGTT_CLK_CTRL_DEFAULT 0x00000080 |
| |
| |
| // addressBlock: mmhub_utcl2_vmsharedpfdec |
| #define mmMC_VM_NB_MMIOBASE_DEFAULT 0x00000000 |
| #define mmMC_VM_NB_MMIOLIMIT_DEFAULT 0x00000000 |
| #define mmMC_VM_NB_PCI_CTRL_DEFAULT 0x00000000 |
| #define mmMC_VM_NB_PCI_ARB_DEFAULT 0x00000008 |
| #define mmMC_VM_NB_TOP_OF_DRAM_SLOT1_DEFAULT 0x00000000 |
| #define mmMC_VM_NB_LOWER_TOP_OF_DRAM2_DEFAULT 0x00000000 |
| #define mmMC_VM_NB_UPPER_TOP_OF_DRAM2_DEFAULT 0x00000000 |
| #define mmMC_VM_FB_OFFSET_DEFAULT 0x00000000 |
| #define mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB_DEFAULT 0x00000000 |
| #define mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB_DEFAULT 0x00000000 |
| #define mmMC_VM_STEERING_DEFAULT 0x00000001 |
| #define mmMC_SHARED_VIRT_RESET_REQ_DEFAULT 0x00000000 |
| #define mmMC_MEM_POWER_LS_DEFAULT 0x00000208 |
| #define mmMC_VM_CACHEABLE_DRAM_ADDRESS_START_DEFAULT 0x00000000 |
| #define mmMC_VM_CACHEABLE_DRAM_ADDRESS_END_DEFAULT 0x00000000 |
| #define mmMC_VM_APT_CNTL_DEFAULT 0x00000000 |
| #define mmMC_VM_LOCAL_HBM_ADDRESS_START_DEFAULT 0x00000000 |
| #define mmMC_VM_LOCAL_HBM_ADDRESS_END_DEFAULT 0x000fffff |
| #define mmMC_VM_LOCAL_HBM_ADDRESS_LOCK_CNTL_DEFAULT 0x00000000 |
| |
| |
| // addressBlock: mmhub_utcl2_vmsharedvcdec |
| #define mmMC_VM_FB_LOCATION_BASE_DEFAULT 0x00000000 |
| #define mmMC_VM_FB_LOCATION_TOP_DEFAULT 0x00000000 |
| #define mmMC_VM_AGP_TOP_DEFAULT 0x00000000 |
| #define mmMC_VM_AGP_BOT_DEFAULT 0x00000000 |
| #define mmMC_VM_AGP_BASE_DEFAULT 0x00000000 |
| #define mmMC_VM_SYSTEM_APERTURE_LOW_ADDR_DEFAULT 0x00000000 |
| #define mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR_DEFAULT 0x00000000 |
| #define mmMC_VM_MX_L1_TLB_CNTL_DEFAULT 0x00002501 |
| |
| |
| // addressBlock: mmhub_utcl2_atcl2pfcntrdec |
| #define mmATC_L2_PERFCOUNTER_LO_DEFAULT 0x00000000 |
| #define mmATC_L2_PERFCOUNTER_HI_DEFAULT 0x00000000 |
| |
| |
| // addressBlock: mmhub_utcl2_atcl2pfcntldec |
| #define mmATC_L2_PERFCOUNTER0_CFG_DEFAULT 0x00000000 |
| #define mmATC_L2_PERFCOUNTER1_CFG_DEFAULT 0x00000000 |
| #define mmATC_L2_PERFCOUNTER_RSLT_CNTL_DEFAULT 0x04000000 |
| |
| #endif |
