| /* |
| * Copyright (C) 2017 Advanced Micro Devices, Inc. |
| * |
| * Permission is hereby granted, free of charge, to any person obtaining a |
| * copy of this software and associated documentation files (the "Software"), |
| * to deal in the Software without restriction, including without limitation |
| * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
| * and/or sell copies of the Software, and to permit persons to whom the |
| * Software is furnished to do so, subject to the following conditions: |
| * |
| * The above copyright notice and this permission notice shall be included |
| * in all copies or substantial portions of the Software. |
| * |
| * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS |
| * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN |
| * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN |
| * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. |
| */ |
| #ifndef _nbio_7_0_OFFSET_HEADER |
| #define _nbio_7_0_OFFSET_HEADER |
| |
| |
| |
| // addressBlock: nbio_iohub_nb_nbcfg_nb_cfgdec |
| // base address: 0x0 |
| #define cfgNB_NBCFG0_NB_VENDOR_ID 0x0000 |
| #define cfgNB_NBCFG0_NB_DEVICE_ID 0x0002 |
| #define cfgNB_NBCFG0_NB_COMMAND 0x0004 |
| #define cfgNB_NBCFG0_NB_STATUS 0x0006 |
| #define cfgNB_NBCFG0_NB_REVISION_ID 0x0008 |
| #define cfgNB_NBCFG0_NB_REGPROG_INF 0x0009 |
| #define cfgNB_NBCFG0_NB_SUB_CLASS 0x000a |
| #define cfgNB_NBCFG0_NB_BASE_CODE 0x000b |
| #define cfgNB_NBCFG0_NB_CACHE_LINE 0x000c |
| #define cfgNB_NBCFG0_NB_LATENCY 0x000d |
| #define cfgNB_NBCFG0_NB_HEADER 0x000e |
| #define cfgNB_NBCFG0_NB_ADAPTER_ID 0x002c |
| #define cfgNB_NBCFG0_NB_CAPABILITIES_PTR 0x0034 |
| #define cfgNB_NBCFG0_NB_HEADER_W 0x0048 |
| #define cfgNB_NBCFG0_NB_PCI_CTRL 0x004c |
| #define cfgNB_NBCFG0_NB_ADAPTER_ID_W 0x0050 |
| #define cfgNB_NBCFG0_NB_SMN_INDEX_EXTENSION_0 0x005c |
| #define cfgNB_NBCFG0_NB_SMN_INDEX_0 0x0060 |
| #define cfgNB_NBCFG0_NB_SMN_DATA_0 0x0064 |
| #define cfgNB_NBCFG0_NBCFG_SCRATCH_0 0x0068 |
| #define cfgNB_NBCFG0_NBCFG_SCRATCH_1 0x006c |
| #define cfgNB_NBCFG0_NBCFG_SCRATCH_2 0x0070 |
| #define cfgNB_NBCFG0_NBCFG_SCRATCH_3 0x0074 |
| #define cfgNB_NBCFG0_NBCFG_SCRATCH_4 0x0078 |
| #define cfgNB_NBCFG0_NB_PCI_ARB 0x0084 |
| #define cfgNB_NBCFG0_NB_DRAM_SLOT1_BASE 0x0088 |
| #define cfgNB_NBCFG0_NB_TOP_OF_DRAM_SLOT1 0x0090 |
| #define cfgNB_NBCFG0_NB_SMN_INDEX_EXTENSION_1 0x009c |
| #define cfgNB_NBCFG0_NB_SMN_INDEX_1 0x00a0 |
| #define cfgNB_NBCFG0_NB_SMN_DATA_1 0x00a4 |
| #define cfgNB_NBCFG0_NB_INDEX_DATA_MUTEX0 0x00a8 |
| #define cfgNB_NBCFG0_NB_INDEX_DATA_MUTEX1 0x00ac |
| #define cfgNB_NBCFG0_NB_SMN_INDEX_EXTENSION_2 0x00b4 |
| #define cfgNB_NBCFG0_NB_SMN_INDEX_2 0x00b8 |
| #define cfgNB_NBCFG0_NB_SMN_DATA_2 0x00bc |
| #define cfgNB_NBCFG0_NB_SMN_INDEX_EXTENSION_3 0x00c0 |
| #define cfgNB_NBCFG0_NB_SMN_INDEX_3 0x00c4 |
| #define cfgNB_NBCFG0_NB_SMN_DATA_3 0x00c8 |
| #define cfgNB_NBCFG0_NB_SMN_INDEX_EXTENSION_4 0x00cc |
| #define cfgNB_NBCFG0_NB_SMN_INDEX_4 0x00d0 |
| #define cfgNB_NBCFG0_NB_SMN_DATA_4 0x00d4 |
| #define cfgNB_NBCFG0_NB_SMN_INDEX_EXTENSION_5 0x00dc |
| #define cfgNB_NBCFG0_NB_SMN_INDEX_5 0x00e0 |
| #define cfgNB_NBCFG0_NB_SMN_DATA_5 0x00e4 |
| #define cfgNB_NBCFG0_NB_PERF_CNT_CTRL 0x00f4 |
| #define cfgNB_NBCFG0_NB_SMN_INDEX_6 0x00f8 |
| #define cfgNB_NBCFG0_NB_SMN_DATA_6 0x00fc |
| |
| |
| // addressBlock: nbio_iohub_iommu_l2_iommul2cfg |
| // base address: 0x0 |
| #define cfgIOMMU_L2_0_IOMMU_VENDOR_ID 0x0000 |
| #define cfgIOMMU_L2_0_IOMMU_DEVICE_ID 0x0002 |
| #define cfgIOMMU_L2_0_IOMMU_COMMAND 0x0004 |
| #define cfgIOMMU_L2_0_IOMMU_STATUS 0x0006 |
| #define cfgIOMMU_L2_0_IOMMU_REVISION_ID 0x0008 |
| #define cfgIOMMU_L2_0_IOMMU_REGPROG_INF 0x0009 |
| #define cfgIOMMU_L2_0_IOMMU_SUB_CLASS 0x000a |
| #define cfgIOMMU_L2_0_IOMMU_BASE_CODE 0x000b |
| #define cfgIOMMU_L2_0_IOMMU_CACHE_LINE 0x000c |
| #define cfgIOMMU_L2_0_IOMMU_LATENCY 0x000d |
| #define cfgIOMMU_L2_0_IOMMU_HEADER 0x000e |
| #define cfgIOMMU_L2_0_IOMMU_BIST 0x000f |
| #define cfgIOMMU_L2_0_IOMMU_ADAPTER_ID 0x002c |
| #define cfgIOMMU_L2_0_IOMMU_CAPABILITIES_PTR 0x0034 |
| #define cfgIOMMU_L2_0_IOMMU_INTERRUPT_LINE 0x003c |
| #define cfgIOMMU_L2_0_IOMMU_INTERRUPT_PIN 0x003d |
| #define cfgIOMMU_L2_0_IOMMU_CAP_HEADER 0x0040 |
| #define cfgIOMMU_L2_0_IOMMU_CAP_BASE_LO 0x0044 |
| #define cfgIOMMU_L2_0_IOMMU_CAP_BASE_HI 0x0048 |
| #define cfgIOMMU_L2_0_IOMMU_CAP_RANGE 0x004c |
| #define cfgIOMMU_L2_0_IOMMU_CAP_MISC 0x0050 |
| #define cfgIOMMU_L2_0_IOMMU_CAP_MISC_1 0x0054 |
| #define cfgIOMMU_L2_0_IOMMU_MSI_CAP 0x0064 |
| #define cfgIOMMU_L2_0_IOMMU_MSI_ADDR_LO 0x0068 |
| #define cfgIOMMU_L2_0_IOMMU_MSI_ADDR_HI 0x006c |
| #define cfgIOMMU_L2_0_IOMMU_MSI_DATA 0x0070 |
| #define cfgIOMMU_L2_0_IOMMU_MSI_MAPPING_CAP 0x0074 |
| #define cfgIOMMU_L2_0_IOMMU_ADAPTER_ID_W 0x0078 |
| #define cfgIOMMU_L2_0_IOMMU_CONTROL_W 0x007c |
| #define cfgIOMMU_L2_0_IOMMU_MMIO_CONTROL0_W 0x0080 |
| #define cfgIOMMU_L2_0_IOMMU_MMIO_CONTROL1_W 0x0084 |
| #define cfgIOMMU_L2_0_IOMMU_RANGE_W 0x0088 |
| #define cfgIOMMU_L2_0_IOMMU_DSFX_CONTROL 0x008c |
| #define cfgIOMMU_L2_0_IOMMU_DSSX_DUMMY_0 0x0090 |
| #define cfgIOMMU_L2_0_IOMMU_DSCX_DUMMY_0 0x0094 |
| #define cfgIOMMU_L2_0_L2B_POISON_DVM_CNTRL 0x0098 |
| #define cfgIOMMU_L2_0_L2_IOHC_DmaReq_Stall_Control 0x009c |
| #define cfgIOMMU_L2_0_IOHC_L2_HostRsp_Stall_Control 0x00a0 |
| #define cfgIOMMU_L2_0_SMMU_MMIO_IDR0_W 0x00a4 |
| #define cfgIOMMU_L2_0_SMMU_MMIO_IDR1_W 0x00a8 |
| #define cfgIOMMU_L2_0_SMMU_MMIO_IDR2_W 0x00ac |
| #define cfgIOMMU_L2_0_SMMU_MMIO_IDR3_W 0x00b0 |
| #define cfgIOMMU_L2_0_SMMU_MMIO_IDR5_W 0x00b8 |
| #define cfgIOMMU_L2_0_SMMU_MMIO_IIDR_W 0x00bc |
| #define cfgIOMMU_L2_0_SMMU_AIDR_W 0x00c0 |
| |
| |
| // addressBlock: nbio_nbif0_bif_cfg_dev0_rc_bifcfgdecp |
| // base address: 0x0 |
| #define cfgBIF_CFG_DEV0_RC0_VENDOR_ID 0x0000 |
| #define cfgBIF_CFG_DEV0_RC0_DEVICE_ID 0x0002 |
| #define cfgBIF_CFG_DEV0_RC0_COMMAND 0x0004 |
| #define cfgBIF_CFG_DEV0_RC0_STATUS 0x0006 |
| #define cfgBIF_CFG_DEV0_RC0_REVISION_ID 0x0008 |
| #define cfgBIF_CFG_DEV0_RC0_PROG_INTERFACE 0x0009 |
| #define cfgBIF_CFG_DEV0_RC0_SUB_CLASS 0x000a |
| #define cfgBIF_CFG_DEV0_RC0_BASE_CLASS 0x000b |
| #define cfgBIF_CFG_DEV0_RC0_CACHE_LINE 0x000c |
| #define cfgBIF_CFG_DEV0_RC0_LATENCY 0x000d |
| #define cfgBIF_CFG_DEV0_RC0_HEADER 0x000e |
| #define cfgBIF_CFG_DEV0_RC0_BIST 0x000f |
| #define cfgBIF_CFG_DEV0_RC0_BASE_ADDR_1 0x0010 |
| #define cfgBIF_CFG_DEV0_RC0_SUB_BUS_NUMBER_LATENCY 0x0018 |
| #define cfgBIF_CFG_DEV0_RC0_IO_BASE_LIMIT 0x001c |
| #define cfgBIF_CFG_DEV0_RC0_SECONDARY_STATUS 0x001e |
| #define cfgBIF_CFG_DEV0_RC0_MEM_BASE_LIMIT 0x0020 |
| #define cfgBIF_CFG_DEV0_RC0_PREF_BASE_LIMIT 0x0024 |
| #define cfgBIF_CFG_DEV0_RC0_PREF_BASE_UPPER 0x0028 |
| #define cfgBIF_CFG_DEV0_RC0_PREF_LIMIT_UPPER 0x002c |
| #define cfgBIF_CFG_DEV0_RC0_IO_BASE_LIMIT_HI 0x0030 |
| #define cfgBIF_CFG_DEV0_RC0_CAP_PTR 0x0034 |
| #define cfgBIF_CFG_DEV0_RC0_INTERRUPT_LINE 0x003c |
| #define cfgBIF_CFG_DEV0_RC0_INTERRUPT_PIN 0x003d |
| #define cfgBIF_CFG_DEV0_RC0_IRQ_BRIDGE_CNTL 0x003e |
| #define cfgBIF_CFG_DEV0_RC0_EXT_BRIDGE_CNTL 0x0040 |
| #define cfgBIF_CFG_DEV0_RC0_PMI_CAP_LIST 0x0050 |
| #define cfgBIF_CFG_DEV0_RC0_PMI_CAP 0x0052 |
| #define cfgBIF_CFG_DEV0_RC0_PMI_STATUS_CNTL 0x0054 |
| #define cfgBIF_CFG_DEV0_RC0_PCIE_CAP_LIST 0x0058 |
| #define cfgBIF_CFG_DEV0_RC0_PCIE_CAP 0x005a |
| #define cfgBIF_CFG_DEV0_RC0_DEVICE_CAP 0x005c |
| #define cfgBIF_CFG_DEV0_RC0_DEVICE_CNTL 0x0060 |
| #define cfgBIF_CFG_DEV0_RC0_DEVICE_STATUS 0x0062 |
| #define cfgBIF_CFG_DEV0_RC0_LINK_CAP 0x0064 |
| #define cfgBIF_CFG_DEV0_RC0_LINK_CNTL 0x0068 |
| #define cfgBIF_CFG_DEV0_RC0_LINK_STATUS 0x006a |
| #define cfgBIF_CFG_DEV0_RC0_SLOT_CAP 0x006c |
| #define cfgBIF_CFG_DEV0_RC0_SLOT_CNTL 0x0070 |
| #define cfgBIF_CFG_DEV0_RC0_SLOT_STATUS 0x0072 |
| #define cfgBIF_CFG_DEV0_RC0_ROOT_CNTL 0x0074 |
| #define cfgBIF_CFG_DEV0_RC0_ROOT_CAP 0x0076 |
| #define cfgBIF_CFG_DEV0_RC0_ROOT_STATUS 0x0078 |
| #define cfgBIF_CFG_DEV0_RC0_DEVICE_CAP2 0x007c |
| #define cfgBIF_CFG_DEV0_RC0_DEVICE_CNTL2 0x0080 |
| #define cfgBIF_CFG_DEV0_RC0_DEVICE_STATUS2 0x0082 |
| #define cfgBIF_CFG_DEV0_RC0_LINK_CAP2 0x0084 |
| #define cfgBIF_CFG_DEV0_RC0_LINK_CNTL2 0x0088 |
| #define cfgBIF_CFG_DEV0_RC0_LINK_STATUS2 0x008a |
| #define cfgBIF_CFG_DEV0_RC0_SLOT_CAP2 0x008c |
| #define cfgBIF_CFG_DEV0_RC0_SLOT_CNTL2 0x0090 |
| #define cfgBIF_CFG_DEV0_RC0_SLOT_STATUS2 0x0092 |
| #define cfgBIF_CFG_DEV0_RC0_MSI_CAP_LIST 0x00a0 |
| #define cfgBIF_CFG_DEV0_RC0_MSI_MSG_CNTL 0x00a2 |
| #define cfgBIF_CFG_DEV0_RC0_MSI_MSG_ADDR_LO 0x00a4 |
| #define cfgBIF_CFG_DEV0_RC0_MSI_MSG_ADDR_HI 0x00a8 |
| #define cfgBIF_CFG_DEV0_RC0_MSI_MSG_DATA 0x00a8 |
| #define cfgBIF_CFG_DEV0_RC0_MSI_MSG_DATA_64 0x00ac |
| #define cfgBIF_CFG_DEV0_RC0_SSID_CAP_LIST 0x00c0 |
| #define cfgBIF_CFG_DEV0_RC0_SSID_CAP 0x00c4 |
| #define cfgBIF_CFG_DEV0_RC0_MSI_MAP_CAP_LIST 0x00c8 |
| #define cfgBIF_CFG_DEV0_RC0_MSI_MAP_CAP 0x00ca |
| #define cfgBIF_CFG_DEV0_RC0_MSI_MAP_ADDR_LO 0x00cc |
| #define cfgBIF_CFG_DEV0_RC0_MSI_MAP_ADDR_HI 0x00d0 |
| #define cfgBIF_CFG_DEV0_RC0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x0100 |
| #define cfgBIF_CFG_DEV0_RC0_PCIE_VENDOR_SPECIFIC_HDR 0x0104 |
| #define cfgBIF_CFG_DEV0_RC0_PCIE_VENDOR_SPECIFIC1 0x0108 |
| #define cfgBIF_CFG_DEV0_RC0_PCIE_VENDOR_SPECIFIC2 0x010c |
| #define cfgBIF_CFG_DEV0_RC0_PCIE_VC_ENH_CAP_LIST 0x0110 |
| #define cfgBIF_CFG_DEV0_RC0_PCIE_PORT_VC_CAP_REG1 0x0114 |
| #define cfgBIF_CFG_DEV0_RC0_PCIE_PORT_VC_CAP_REG2 0x0118 |
| #define cfgBIF_CFG_DEV0_RC0_PCIE_PORT_VC_CNTL 0x011c |
| #define cfgBIF_CFG_DEV0_RC0_PCIE_PORT_VC_STATUS 0x011e |
| #define cfgBIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_CAP 0x0120 |
| #define cfgBIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_CNTL 0x0124 |
| #define cfgBIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_STATUS 0x012a |
| #define cfgBIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_CAP 0x012c |
| #define cfgBIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_CNTL 0x0130 |
| #define cfgBIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_STATUS 0x0136 |
| #define cfgBIF_CFG_DEV0_RC0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST 0x0140 |
| #define cfgBIF_CFG_DEV0_RC0_PCIE_DEV_SERIAL_NUM_DW1 0x0144 |
| #define cfgBIF_CFG_DEV0_RC0_PCIE_DEV_SERIAL_NUM_DW2 0x0148 |
| #define cfgBIF_CFG_DEV0_RC0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x0150 |
| #define cfgBIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS 0x0154 |
| #define cfgBIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK 0x0158 |
| #define cfgBIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY 0x015c |
| #define cfgBIF_CFG_DEV0_RC0_PCIE_CORR_ERR_STATUS 0x0160 |
| #define cfgBIF_CFG_DEV0_RC0_PCIE_CORR_ERR_MASK 0x0164 |
| #define cfgBIF_CFG_DEV0_RC0_PCIE_ADV_ERR_CAP_CNTL 0x0168 |
| #define cfgBIF_CFG_DEV0_RC0_PCIE_HDR_LOG0 0x016c |
| #define cfgBIF_CFG_DEV0_RC0_PCIE_HDR_LOG1 0x0170 |
| #define cfgBIF_CFG_DEV0_RC0_PCIE_HDR_LOG2 0x0174 |
| #define cfgBIF_CFG_DEV0_RC0_PCIE_HDR_LOG3 0x0178 |
| #define cfgBIF_CFG_DEV0_RC0_PCIE_ROOT_ERR_CMD 0x017c |
| #define cfgBIF_CFG_DEV0_RC0_PCIE_ROOT_ERR_STATUS 0x0180 |
| #define cfgBIF_CFG_DEV0_RC0_PCIE_ERR_SRC_ID 0x0184 |
| #define cfgBIF_CFG_DEV0_RC0_PCIE_TLP_PREFIX_LOG0 0x0188 |
| #define cfgBIF_CFG_DEV0_RC0_PCIE_TLP_PREFIX_LOG1 0x018c |
| #define cfgBIF_CFG_DEV0_RC0_PCIE_TLP_PREFIX_LOG2 0x0190 |
| #define cfgBIF_CFG_DEV0_RC0_PCIE_TLP_PREFIX_LOG3 0x0194 |
| #define cfgBIF_CFG_DEV0_RC0_PCIE_SECONDARY_ENH_CAP_LIST 0x0270 |
| #define cfgBIF_CFG_DEV0_RC0_PCIE_LINK_CNTL3 0x0274 |
| #define cfgBIF_CFG_DEV0_RC0_PCIE_LANE_ERROR_STATUS 0x0278 |
| #define cfgBIF_CFG_DEV0_RC0_PCIE_LANE_0_EQUALIZATION_CNTL 0x027c |
| #define cfgBIF_CFG_DEV0_RC0_PCIE_LANE_1_EQUALIZATION_CNTL 0x027e |
| #define cfgBIF_CFG_DEV0_RC0_PCIE_LANE_2_EQUALIZATION_CNTL 0x0280 |
| #define cfgBIF_CFG_DEV0_RC0_PCIE_LANE_3_EQUALIZATION_CNTL 0x0282 |
| #define cfgBIF_CFG_DEV0_RC0_PCIE_LANE_4_EQUALIZATION_CNTL 0x0284 |
| #define cfgBIF_CFG_DEV0_RC0_PCIE_LANE_5_EQUALIZATION_CNTL 0x0286 |
| #define cfgBIF_CFG_DEV0_RC0_PCIE_LANE_6_EQUALIZATION_CNTL 0x0288 |
| #define cfgBIF_CFG_DEV0_RC0_PCIE_LANE_7_EQUALIZATION_CNTL 0x028a |
| #define cfgBIF_CFG_DEV0_RC0_PCIE_LANE_8_EQUALIZATION_CNTL 0x028c |
| #define cfgBIF_CFG_DEV0_RC0_PCIE_LANE_9_EQUALIZATION_CNTL 0x028e |
| #define cfgBIF_CFG_DEV0_RC0_PCIE_LANE_10_EQUALIZATION_CNTL 0x0290 |
| #define cfgBIF_CFG_DEV0_RC0_PCIE_LANE_11_EQUALIZATION_CNTL 0x0292 |
| #define cfgBIF_CFG_DEV0_RC0_PCIE_LANE_12_EQUALIZATION_CNTL 0x0294 |
| #define cfgBIF_CFG_DEV0_RC0_PCIE_LANE_13_EQUALIZATION_CNTL 0x0296 |
| #define cfgBIF_CFG_DEV0_RC0_PCIE_LANE_14_EQUALIZATION_CNTL 0x0298 |
| #define cfgBIF_CFG_DEV0_RC0_PCIE_LANE_15_EQUALIZATION_CNTL 0x029a |
| #define cfgBIF_CFG_DEV0_RC0_PCIE_ACS_ENH_CAP_LIST 0x02a0 |
| #define cfgBIF_CFG_DEV0_RC0_PCIE_ACS_CAP 0x02a4 |
| #define cfgBIF_CFG_DEV0_RC0_PCIE_ACS_CNTL 0x02a6 |
| |
| |
| // addressBlock: nbio_nbif0_bif_cfg_dev1_rc_bifcfgdecp |
| // base address: 0x0 |
| #define cfgBIF_CFG_DEV1_RC0_VENDOR_ID 0x0000 |
| #define cfgBIF_CFG_DEV1_RC0_DEVICE_ID 0x0002 |
| #define cfgBIF_CFG_DEV1_RC0_COMMAND 0x0004 |
| #define cfgBIF_CFG_DEV1_RC0_STATUS 0x0006 |
| #define cfgBIF_CFG_DEV1_RC0_REVISION_ID 0x0008 |
| #define cfgBIF_CFG_DEV1_RC0_PROG_INTERFACE 0x0009 |
| #define cfgBIF_CFG_DEV1_RC0_SUB_CLASS 0x000a |
| #define cfgBIF_CFG_DEV1_RC0_BASE_CLASS 0x000b |
| #define cfgBIF_CFG_DEV1_RC0_CACHE_LINE 0x000c |
| #define cfgBIF_CFG_DEV1_RC0_LATENCY 0x000d |
| #define cfgBIF_CFG_DEV1_RC0_HEADER 0x000e |
| #define cfgBIF_CFG_DEV1_RC0_BIST 0x000f |
| #define cfgBIF_CFG_DEV1_RC0_BASE_ADDR_1 0x0010 |
| #define cfgBIF_CFG_DEV1_RC0_SUB_BUS_NUMBER_LATENCY 0x0018 |
| #define cfgBIF_CFG_DEV1_RC0_IO_BASE_LIMIT 0x001c |
| #define cfgBIF_CFG_DEV1_RC0_SECONDARY_STATUS 0x001e |
| #define cfgBIF_CFG_DEV1_RC0_MEM_BASE_LIMIT 0x0020 |
| #define cfgBIF_CFG_DEV1_RC0_PREF_BASE_LIMIT 0x0024 |
| #define cfgBIF_CFG_DEV1_RC0_PREF_BASE_UPPER 0x0028 |
| #define cfgBIF_CFG_DEV1_RC0_PREF_LIMIT_UPPER 0x002c |
| #define cfgBIF_CFG_DEV1_RC0_IO_BASE_LIMIT_HI 0x0030 |
| #define cfgBIF_CFG_DEV1_RC0_CAP_PTR 0x0034 |
| #define cfgBIF_CFG_DEV1_RC0_INTERRUPT_LINE 0x003c |
| #define cfgBIF_CFG_DEV1_RC0_INTERRUPT_PIN 0x003d |
| #define cfgBIF_CFG_DEV1_RC0_IRQ_BRIDGE_CNTL 0x003e |
| #define cfgBIF_CFG_DEV1_RC0_EXT_BRIDGE_CNTL 0x0040 |
| #define cfgBIF_CFG_DEV1_RC0_PMI_CAP_LIST 0x0050 |
| #define cfgBIF_CFG_DEV1_RC0_PMI_CAP 0x0052 |
| #define cfgBIF_CFG_DEV1_RC0_PMI_STATUS_CNTL 0x0054 |
| #define cfgBIF_CFG_DEV1_RC0_PCIE_CAP_LIST 0x0058 |
| #define cfgBIF_CFG_DEV1_RC0_PCIE_CAP 0x005a |
| #define cfgBIF_CFG_DEV1_RC0_DEVICE_CAP 0x005c |
| #define cfgBIF_CFG_DEV1_RC0_DEVICE_CNTL 0x0060 |
| #define cfgBIF_CFG_DEV1_RC0_DEVICE_STATUS 0x0062 |
| #define cfgBIF_CFG_DEV1_RC0_LINK_CAP 0x0064 |
| #define cfgBIF_CFG_DEV1_RC0_LINK_CNTL 0x0068 |
| #define cfgBIF_CFG_DEV1_RC0_LINK_STATUS 0x006a |
| #define cfgBIF_CFG_DEV1_RC0_SLOT_CAP 0x006c |
| #define cfgBIF_CFG_DEV1_RC0_SLOT_CNTL 0x0070 |
| #define cfgBIF_CFG_DEV1_RC0_SLOT_STATUS 0x0072 |
| #define cfgBIF_CFG_DEV1_RC0_ROOT_CNTL 0x0074 |
| #define cfgBIF_CFG_DEV1_RC0_ROOT_CAP 0x0076 |
| #define cfgBIF_CFG_DEV1_RC0_ROOT_STATUS 0x0078 |
| #define cfgBIF_CFG_DEV1_RC0_DEVICE_CAP2 0x007c |
| #define cfgBIF_CFG_DEV1_RC0_DEVICE_CNTL2 0x0080 |
| #define cfgBIF_CFG_DEV1_RC0_DEVICE_STATUS2 0x0082 |
| #define cfgBIF_CFG_DEV1_RC0_LINK_CAP2 0x0084 |
| #define cfgBIF_CFG_DEV1_RC0_LINK_CNTL2 0x0088 |
| #define cfgBIF_CFG_DEV1_RC0_LINK_STATUS2 0x008a |
| #define cfgBIF_CFG_DEV1_RC0_SLOT_CAP2 0x008c |
| #define cfgBIF_CFG_DEV1_RC0_SLOT_CNTL2 0x0090 |
| #define cfgBIF_CFG_DEV1_RC0_SLOT_STATUS2 0x0092 |
| #define cfgBIF_CFG_DEV1_RC0_MSI_CAP_LIST 0x00a0 |
| #define cfgBIF_CFG_DEV1_RC0_MSI_MSG_CNTL 0x00a2 |
| #define cfgBIF_CFG_DEV1_RC0_MSI_MSG_ADDR_LO 0x00a4 |
| #define cfgBIF_CFG_DEV1_RC0_MSI_MSG_ADDR_HI 0x00a8 |
| #define cfgBIF_CFG_DEV1_RC0_MSI_MSG_DATA 0x00a8 |
| #define cfgBIF_CFG_DEV1_RC0_MSI_MSG_DATA_64 0x00ac |
| #define cfgBIF_CFG_DEV1_RC0_SSID_CAP_LIST 0x00c0 |
| #define cfgBIF_CFG_DEV1_RC0_SSID_CAP 0x00c4 |
| #define cfgBIF_CFG_DEV1_RC0_MSI_MAP_CAP_LIST 0x00c8 |
| #define cfgBIF_CFG_DEV1_RC0_MSI_MAP_CAP 0x00ca |
| #define cfgBIF_CFG_DEV1_RC0_MSI_MAP_ADDR_LO 0x00cc |
| #define cfgBIF_CFG_DEV1_RC0_MSI_MAP_ADDR_HI 0x00d0 |
| #define cfgBIF_CFG_DEV1_RC0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x0100 |
| #define cfgBIF_CFG_DEV1_RC0_PCIE_VENDOR_SPECIFIC_HDR 0x0104 |
| #define cfgBIF_CFG_DEV1_RC0_PCIE_VENDOR_SPECIFIC1 0x0108 |
| #define cfgBIF_CFG_DEV1_RC0_PCIE_VENDOR_SPECIFIC2 0x010c |
| #define cfgBIF_CFG_DEV1_RC0_PCIE_VC_ENH_CAP_LIST 0x0110 |
| #define cfgBIF_CFG_DEV1_RC0_PCIE_PORT_VC_CAP_REG1 0x0114 |
| #define cfgBIF_CFG_DEV1_RC0_PCIE_PORT_VC_CAP_REG2 0x0118 |
| #define cfgBIF_CFG_DEV1_RC0_PCIE_PORT_VC_CNTL 0x011c |
| #define cfgBIF_CFG_DEV1_RC0_PCIE_PORT_VC_STATUS 0x011e |
| #define cfgBIF_CFG_DEV1_RC0_PCIE_VC0_RESOURCE_CAP 0x0120 |
| #define cfgBIF_CFG_DEV1_RC0_PCIE_VC0_RESOURCE_CNTL 0x0124 |
| #define cfgBIF_CFG_DEV1_RC0_PCIE_VC0_RESOURCE_STATUS 0x012a |
| #define cfgBIF_CFG_DEV1_RC0_PCIE_VC1_RESOURCE_CAP 0x012c |
| #define cfgBIF_CFG_DEV1_RC0_PCIE_VC1_RESOURCE_CNTL 0x0130 |
| #define cfgBIF_CFG_DEV1_RC0_PCIE_VC1_RESOURCE_STATUS 0x0136 |
| #define cfgBIF_CFG_DEV1_RC0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST 0x0140 |
| #define cfgBIF_CFG_DEV1_RC0_PCIE_DEV_SERIAL_NUM_DW1 0x0144 |
| #define cfgBIF_CFG_DEV1_RC0_PCIE_DEV_SERIAL_NUM_DW2 0x0148 |
| #define cfgBIF_CFG_DEV1_RC0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x0150 |
| #define cfgBIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_STATUS 0x0154 |
| #define cfgBIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_MASK 0x0158 |
| #define cfgBIF_CFG_DEV1_RC0_PCIE_UNCORR_ERR_SEVERITY 0x015c |
| #define cfgBIF_CFG_DEV1_RC0_PCIE_CORR_ERR_STATUS 0x0160 |
| #define cfgBIF_CFG_DEV1_RC0_PCIE_CORR_ERR_MASK 0x0164 |
| #define cfgBIF_CFG_DEV1_RC0_PCIE_ADV_ERR_CAP_CNTL 0x0168 |
| #define cfgBIF_CFG_DEV1_RC0_PCIE_HDR_LOG0 0x016c |
| #define cfgBIF_CFG_DEV1_RC0_PCIE_HDR_LOG1 0x0170 |
| #define cfgBIF_CFG_DEV1_RC0_PCIE_HDR_LOG2 0x0174 |
| #define cfgBIF_CFG_DEV1_RC0_PCIE_HDR_LOG3 0x0178 |
| #define cfgBIF_CFG_DEV1_RC0_PCIE_ROOT_ERR_CMD 0x017c |
| #define cfgBIF_CFG_DEV1_RC0_PCIE_ROOT_ERR_STATUS 0x0180 |
| #define cfgBIF_CFG_DEV1_RC0_PCIE_ERR_SRC_ID 0x0184 |
| #define cfgBIF_CFG_DEV1_RC0_PCIE_TLP_PREFIX_LOG0 0x0188 |
| #define cfgBIF_CFG_DEV1_RC0_PCIE_TLP_PREFIX_LOG1 0x018c |
| #define cfgBIF_CFG_DEV1_RC0_PCIE_TLP_PREFIX_LOG2 0x0190 |
| #define cfgBIF_CFG_DEV1_RC0_PCIE_TLP_PREFIX_LOG3 0x0194 |
| #define cfgBIF_CFG_DEV1_RC0_PCIE_SECONDARY_ENH_CAP_LIST 0x0270 |
| #define cfgBIF_CFG_DEV1_RC0_PCIE_LINK_CNTL3 0x0274 |
| #define cfgBIF_CFG_DEV1_RC0_PCIE_LANE_ERROR_STATUS 0x0278 |
| #define cfgBIF_CFG_DEV1_RC0_PCIE_LANE_0_EQUALIZATION_CNTL 0x027c |
| #define cfgBIF_CFG_DEV1_RC0_PCIE_LANE_1_EQUALIZATION_CNTL 0x027e |
| #define cfgBIF_CFG_DEV1_RC0_PCIE_LANE_2_EQUALIZATION_CNTL 0x0280 |
| #define cfgBIF_CFG_DEV1_RC0_PCIE_LANE_3_EQUALIZATION_CNTL 0x0282 |
| #define cfgBIF_CFG_DEV1_RC0_PCIE_LANE_4_EQUALIZATION_CNTL 0x0284 |
| #define cfgBIF_CFG_DEV1_RC0_PCIE_LANE_5_EQUALIZATION_CNTL 0x0286 |
| #define cfgBIF_CFG_DEV1_RC0_PCIE_LANE_6_EQUALIZATION_CNTL 0x0288 |
| #define cfgBIF_CFG_DEV1_RC0_PCIE_LANE_7_EQUALIZATION_CNTL 0x028a |
| #define cfgBIF_CFG_DEV1_RC0_PCIE_LANE_8_EQUALIZATION_CNTL 0x028c |
| #define cfgBIF_CFG_DEV1_RC0_PCIE_LANE_9_EQUALIZATION_CNTL 0x028e |
| #define cfgBIF_CFG_DEV1_RC0_PCIE_LANE_10_EQUALIZATION_CNTL 0x0290 |
| #define cfgBIF_CFG_DEV1_RC0_PCIE_LANE_11_EQUALIZATION_CNTL 0x0292 |
| #define cfgBIF_CFG_DEV1_RC0_PCIE_LANE_12_EQUALIZATION_CNTL 0x0294 |
| #define cfgBIF_CFG_DEV1_RC0_PCIE_LANE_13_EQUALIZATION_CNTL 0x0296 |
| #define cfgBIF_CFG_DEV1_RC0_PCIE_LANE_14_EQUALIZATION_CNTL 0x0298 |
| #define cfgBIF_CFG_DEV1_RC0_PCIE_LANE_15_EQUALIZATION_CNTL 0x029a |
| #define cfgBIF_CFG_DEV1_RC0_PCIE_ACS_ENH_CAP_LIST 0x02a0 |
| #define cfgBIF_CFG_DEV1_RC0_PCIE_ACS_CAP 0x02a4 |
| #define cfgBIF_CFG_DEV1_RC0_PCIE_ACS_CNTL 0x02a6 |
| |
| |
| // addressBlock: nbio_iohub_nb_pciedummy0_pciedummy_cfgdec |
| // base address: 0x0 |
| #define cfgNB_PCIEDUMMY0_0_DEVICE_VENDOR_ID 0x0000 |
| #define cfgNB_PCIEDUMMY0_0_STATUS_COMMAND 0x0004 |
| #define cfgNB_PCIEDUMMY0_0_CLASS_CODE_REVID 0x0008 |
| #define cfgNB_PCIEDUMMY0_0_HEADER_TYPE 0x000c |
| #define cfgNB_PCIEDUMMY0_0_HEADER_TYPE_W 0x0040 |
| |
| |
| // addressBlock: nbio_iohub_nb_pciedummy1_pciedummy_cfgdec |
| // base address: 0x0 |
| #define cfgNB_PCIEDUMMY1_0_DEVICE_VENDOR_ID 0x0000 |
| #define cfgNB_PCIEDUMMY1_0_STATUS_COMMAND 0x0004 |
| #define cfgNB_PCIEDUMMY1_0_CLASS_CODE_REVID 0x0008 |
| #define cfgNB_PCIEDUMMY1_0_HEADER_TYPE 0x000c |
| #define cfgNB_PCIEDUMMY1_0_HEADER_TYPE_W 0x0040 |
| |
| |
| // addressBlock: nbio_nbif0_bif_cfg_dev0_epf0_bifcfgdecp |
| // base address: 0x0 |
| #define cfgVENDOR_ID 0x0000 |
| #define cfgDEVICE_ID 0x0002 |
| #define cfgCOMMAND 0x0004 |
| #define cfgSTATUS 0x0006 |
| #define cfgREVISION_ID 0x0008 |
| #define cfgPROG_INTERFACE 0x0009 |
| #define cfgSUB_CLASS 0x000a |
| #define cfgBASE_CLASS 0x000b |
| #define cfgCACHE_LINE 0x000c |
| #define cfgLATENCY 0x000d |
| #define cfgHEADER 0x000e |
| #define cfgBIST 0x000f |
| #define cfgBASE_ADDR_1 0x0010 |
| #define cfgBASE_ADDR_2 0x0014 |
| #define cfgBASE_ADDR_3 0x0018 |
| #define cfgBASE_ADDR_4 0x001c |
| #define cfgBASE_ADDR_5 0x0020 |
| #define cfgBASE_ADDR_6 0x0024 |
| #define cfgADAPTER_ID 0x002c |
| #define cfgROM_BASE_ADDR 0x0030 |
| #define cfgCAP_PTR 0x0034 |
| #define cfgINTERRUPT_LINE 0x003c |
| #define cfgINTERRUPT_PIN 0x003d |
| #define cfgMIN_GRANT 0x003e |
| #define cfgMAX_LATENCY 0x003f |
| #define cfgVENDOR_CAP_LIST 0x0048 |
| #define cfgADAPTER_ID_W 0x004c |
| #define cfgPMI_CAP_LIST 0x0050 |
| #define cfgPMI_CAP 0x0052 |
| #define cfgPMI_STATUS_CNTL 0x0054 |
| #define cfgPCIE_CAP_LIST 0x0064 |
| #define cfgPCIE_CAP 0x0066 |
| #define cfgDEVICE_CAP 0x0068 |
| #define cfgDEVICE_CNTL 0x006c |
| #define cfgDEVICE_STATUS 0x006e |
| #define cfgLINK_CAP 0x0070 |
| #define cfgLINK_CNTL 0x0074 |
| #define cfgLINK_STATUS 0x0076 |
| #define cfgDEVICE_CAP2 0x0088 |
| #define cfgDEVICE_CNTL2 0x008c |
| #define cfgDEVICE_STATUS2 0x008e |
| #define cfgLINK_CAP2 0x0090 |
| #define cfgLINK_CNTL2 0x0094 |
| #define cfgLINK_STATUS2 0x0096 |
| #define cfgSLOT_CAP2 0x0098 |
| #define cfgSLOT_CNTL2 0x009c |
| #define cfgSLOT_STATUS2 0x009e |
| #define cfgMSI_CAP_LIST 0x00a0 |
| #define cfgMSI_MSG_CNTL 0x00a2 |
| #define cfgMSI_MSG_ADDR_LO 0x00a4 |
| #define cfgMSI_MSG_ADDR_HI 0x00a8 |
| #define cfgMSI_MSG_DATA 0x00a8 |
| #define cfgMSI_MASK 0x00ac |
| #define cfgMSI_MSG_DATA_64 0x00ac |
| #define cfgMSI_MASK_64 0x00b0 |
| #define cfgMSI_PENDING 0x00b0 |
| #define cfgMSI_PENDING_64 0x00b4 |
| #define cfgMSIX_CAP_LIST 0x00c0 |
| #define cfgMSIX_MSG_CNTL 0x00c2 |
| #define cfgMSIX_TABLE 0x00c4 |
| #define cfgMSIX_PBA 0x00c8 |
| #define cfgPCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x0100 |
| #define cfgPCIE_VENDOR_SPECIFIC_HDR 0x0104 |
| #define cfgPCIE_VENDOR_SPECIFIC1 0x0108 |
| #define cfgPCIE_VENDOR_SPECIFIC2 0x010c |
| #define cfgPCIE_VC_ENH_CAP_LIST 0x0110 |
| #define cfgPCIE_PORT_VC_CAP_REG1 0x0114 |
| #define cfgPCIE_PORT_VC_CAP_REG2 0x0118 |
| #define cfgPCIE_PORT_VC_CNTL 0x011c |
| #define cfgPCIE_PORT_VC_STATUS 0x011e |
| #define cfgPCIE_VC0_RESOURCE_CAP 0x0120 |
| #define cfgPCIE_VC0_RESOURCE_CNTL 0x0124 |
| #define cfgPCIE_VC0_RESOURCE_STATUS 0x012a |
| #define cfgPCIE_VC1_RESOURCE_CAP 0x012c |
| #define cfgPCIE_VC1_RESOURCE_CNTL 0x0130 |
| #define cfgPCIE_VC1_RESOURCE_STATUS 0x0136 |
| #define cfgPCIE_DEV_SERIAL_NUM_ENH_CAP_LIST 0x0140 |
| #define cfgPCIE_DEV_SERIAL_NUM_DW1 0x0144 |
| #define cfgPCIE_DEV_SERIAL_NUM_DW2 0x0148 |
| #define cfgPCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x0150 |
| #define cfgPCIE_UNCORR_ERR_STATUS 0x0154 |
| #define cfgPCIE_UNCORR_ERR_MASK 0x0158 |
| #define cfgPCIE_UNCORR_ERR_SEVERITY 0x015c |
| #define cfgPCIE_CORR_ERR_STATUS 0x0160 |
| #define cfgPCIE_CORR_ERR_MASK 0x0164 |
| #define cfgPCIE_ADV_ERR_CAP_CNTL 0x0168 |
| #define cfgPCIE_HDR_LOG0 0x016c |
| #define cfgPCIE_HDR_LOG1 0x0170 |
| #define cfgPCIE_HDR_LOG2 0x0174 |
| #define cfgPCIE_HDR_LOG3 0x0178 |
| #define cfgPCIE_TLP_PREFIX_LOG0 0x0188 |
| #define cfgPCIE_TLP_PREFIX_LOG1 0x018c |
| #define cfgPCIE_TLP_PREFIX_LOG2 0x0190 |
| #define cfgPCIE_TLP_PREFIX_LOG3 0x0194 |
| #define cfgPCIE_BAR_ENH_CAP_LIST 0x0200 |
| #define cfgPCIE_BAR1_CAP 0x0204 |
| #define cfgPCIE_BAR1_CNTL 0x0208 |
| #define cfgPCIE_BAR2_CAP 0x020c |
| #define cfgPCIE_BAR2_CNTL 0x0210 |
| #define cfgPCIE_BAR3_CAP 0x0214 |
| #define cfgPCIE_BAR3_CNTL 0x0218 |
| #define cfgPCIE_BAR4_CAP 0x021c |
| #define cfgPCIE_BAR4_CNTL 0x0220 |
| #define cfgPCIE_BAR5_CAP 0x0224 |
| #define cfgPCIE_BAR5_CNTL 0x0228 |
| #define cfgPCIE_BAR6_CAP 0x022c |
| #define cfgPCIE_BAR6_CNTL 0x0230 |
| #define cfgPCIE_PWR_BUDGET_ENH_CAP_LIST 0x0240 |
| #define cfgPCIE_PWR_BUDGET_DATA_SELECT 0x0244 |
| #define cfgPCIE_PWR_BUDGET_DATA 0x0248 |
| #define cfgPCIE_PWR_BUDGET_CAP 0x024c |
| #define cfgPCIE_DPA_ENH_CAP_LIST 0x0250 |
| #define cfgPCIE_DPA_CAP 0x0254 |
| #define cfgPCIE_DPA_LATENCY_INDICATOR 0x0258 |
| #define cfgPCIE_DPA_STATUS 0x025c |
| #define cfgPCIE_DPA_CNTL 0x025e |
| #define cfgPCIE_DPA_SUBSTATE_PWR_ALLOC_0 0x0260 |
| #define cfgPCIE_DPA_SUBSTATE_PWR_ALLOC_1 0x0261 |
| #define cfgPCIE_DPA_SUBSTATE_PWR_ALLOC_2 0x0262 |
| #define cfgPCIE_DPA_SUBSTATE_PWR_ALLOC_3 0x0263 |
| #define cfgPCIE_DPA_SUBSTATE_PWR_ALLOC_4 0x0264 |
| #define cfgPCIE_DPA_SUBSTATE_PWR_ALLOC_5 0x0265 |
| #define cfgPCIE_DPA_SUBSTATE_PWR_ALLOC_6 0x0266 |
| #define cfgPCIE_DPA_SUBSTATE_PWR_ALLOC_7 0x0267 |
| #define cfgPCIE_SECONDARY_ENH_CAP_LIST 0x0270 |
| #define cfgPCIE_LINK_CNTL3 0x0274 |
| #define cfgPCIE_LANE_ERROR_STATUS 0x0278 |
| #define cfgPCIE_LANE_0_EQUALIZATION_CNTL 0x027c |
| #define cfgPCIE_LANE_1_EQUALIZATION_CNTL 0x027e |
| #define cfgPCIE_LANE_2_EQUALIZATION_CNTL 0x0280 |
| #define cfgPCIE_LANE_3_EQUALIZATION_CNTL 0x0282 |
| #define cfgPCIE_LANE_4_EQUALIZATION_CNTL 0x0284 |
| #define cfgPCIE_LANE_5_EQUALIZATION_CNTL 0x0286 |
| #define cfgPCIE_LANE_6_EQUALIZATION_CNTL 0x0288 |
| #define cfgPCIE_LANE_7_EQUALIZATION_CNTL 0x028a |
| #define cfgPCIE_LANE_8_EQUALIZATION_CNTL 0x028c |
| #define cfgPCIE_LANE_9_EQUALIZATION_CNTL 0x028e |
| #define cfgPCIE_LANE_10_EQUALIZATION_CNTL 0x0290 |
| #define cfgPCIE_LANE_11_EQUALIZATION_CNTL 0x0292 |
| #define cfgPCIE_LANE_12_EQUALIZATION_CNTL 0x0294 |
| #define cfgPCIE_LANE_13_EQUALIZATION_CNTL 0x0296 |
| #define cfgPCIE_LANE_14_EQUALIZATION_CNTL 0x0298 |
| #define cfgPCIE_LANE_15_EQUALIZATION_CNTL 0x029a |
| #define cfgPCIE_ACS_ENH_CAP_LIST 0x02a0 |
| #define cfgPCIE_ACS_CAP 0x02a4 |
| #define cfgPCIE_ACS_CNTL 0x02a6 |
| #define cfgPCIE_ATS_ENH_CAP_LIST 0x02b0 |
| #define cfgPCIE_ATS_CAP 0x02b4 |
| #define cfgPCIE_ATS_CNTL 0x02b6 |
| #define cfgPCIE_PAGE_REQ_ENH_CAP_LIST 0x02c0 |
| #define cfgPCIE_PAGE_REQ_CNTL 0x02c4 |
| #define cfgPCIE_PAGE_REQ_STATUS 0x02c6 |
| #define cfgPCIE_OUTSTAND_PAGE_REQ_CAPACITY 0x02c8 |
| #define cfgPCIE_OUTSTAND_PAGE_REQ_ALLOC 0x02cc |
| #define cfgPCIE_PASID_ENH_CAP_LIST 0x02d0 |
| #define cfgPCIE_PASID_CAP 0x02d4 |
| #define cfgPCIE_PASID_CNTL 0x02d6 |
| #define cfgPCIE_TPH_REQR_ENH_CAP_LIST 0x02e0 |
| #define cfgPCIE_TPH_REQR_CAP 0x02e4 |
| #define cfgPCIE_TPH_REQR_CNTL 0x02e8 |
| #define cfgPCIE_MC_ENH_CAP_LIST 0x02f0 |
| #define cfgPCIE_MC_CAP 0x02f4 |
| #define cfgPCIE_MC_CNTL 0x02f6 |
| #define cfgPCIE_MC_ADDR0 0x02f8 |
| #define cfgPCIE_MC_ADDR1 0x02fc |
| #define cfgPCIE_MC_RCV0 0x0300 |
| #define cfgPCIE_MC_RCV1 0x0304 |
| #define cfgPCIE_MC_BLOCK_ALL0 0x0308 |
| #define cfgPCIE_MC_BLOCK_ALL1 0x030c |
| #define cfgPCIE_MC_BLOCK_UNTRANSLATED_0 0x0310 |
| #define cfgPCIE_MC_BLOCK_UNTRANSLATED_1 0x0314 |
| #define cfgPCIE_LTR_ENH_CAP_LIST 0x0320 |
| #define cfgPCIE_LTR_CAP 0x0324 |
| #define cfgPCIE_ARI_ENH_CAP_LIST 0x0328 |
| #define cfgPCIE_ARI_CAP 0x032c |
| #define cfgPCIE_ARI_CNTL 0x032e |
| #define cfgPCIE_SRIOV_ENH_CAP_LIST 0x0330 |
| #define cfgPCIE_SRIOV_CAP 0x0334 |
| #define cfgPCIE_SRIOV_CONTROL 0x0338 |
| #define cfgPCIE_SRIOV_STATUS 0x033a |
| #define cfgPCIE_SRIOV_INITIAL_VFS 0x033c |
| #define cfgPCIE_SRIOV_TOTAL_VFS 0x033e |
| #define cfgPCIE_SRIOV_NUM_VFS 0x0340 |
| #define cfgPCIE_SRIOV_FUNC_DEP_LINK 0x0342 |
| #define cfgPCIE_SRIOV_FIRST_VF_OFFSET 0x0344 |
| #define cfgPCIE_SRIOV_VF_STRIDE 0x0346 |
| #define cfgPCIE_SRIOV_VF_DEVICE_ID 0x034a |
| #define cfgPCIE_SRIOV_SUPPORTED_PAGE_SIZE 0x034c |
| #define cfgPCIE_SRIOV_SYSTEM_PAGE_SIZE 0x0350 |
| #define cfgPCIE_SRIOV_VF_BASE_ADDR_0 0x0354 |
| #define cfgPCIE_SRIOV_VF_BASE_ADDR_1 0x0358 |
| #define cfgPCIE_SRIOV_VF_BASE_ADDR_2 0x035c |
| #define cfgPCIE_SRIOV_VF_BASE_ADDR_3 0x0360 |
| #define cfgPCIE_SRIOV_VF_BASE_ADDR_4 0x0364 |
| #define cfgPCIE_SRIOV_VF_BASE_ADDR_5 0x0368 |
| #define cfgPCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET 0x036c |
| #define cfgPCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV 0x0400 |
| #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV 0x0404 |
| #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW 0x0408 |
| #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE 0x040c |
| #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS 0x0410 |
| #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_RESET_CONTROL 0x0414 |
| #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0 0x0418 |
| #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1 0x041c |
| #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2 0x0420 |
| #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT 0x0424 |
| #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB 0x0428 |
| #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS 0x042c |
| #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB 0x0430 |
| #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB 0x0434 |
| #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB 0x0438 |
| #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB 0x043c |
| #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB 0x0440 |
| #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB 0x0444 |
| #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB 0x0448 |
| #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB 0x044c |
| #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB 0x0450 |
| #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB 0x0454 |
| #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB 0x0458 |
| #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB 0x045c |
| #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB 0x0460 |
| #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB 0x0464 |
| #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB 0x0468 |
| #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB 0x046c |
| #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW0 0x0470 |
| #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW1 0x0474 |
| #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW2 0x0478 |
| #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW3 0x047c |
| #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW4 0x0480 |
| #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW5 0x0484 |
| #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW6 0x0488 |
| #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW7 0x048c |
| #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW8 0x0490 |
| #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW0 0x04a0 |
| #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW1 0x04a4 |
| #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW2 0x04a8 |
| #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW3 0x04ac |
| #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW4 0x04b0 |
| #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW5 0x04b4 |
| #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW6 0x04b8 |
| #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW7 0x04bc |
| #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW8 0x04c0 |
| #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW0 0x04d0 |
| #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW1 0x04d4 |
| #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW2 0x04d8 |
| #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW3 0x04dc |
| #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW4 0x04e0 |
| #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW5 0x04e4 |
| #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW6 0x04e8 |
| #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW7 0x04ec |
| #define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW8 0x04f0 |
| //#define cfgBIF_CFG_DEV0_EPF0_VENDOR_ID 0x0000 |
| //#define cfgBIF_CFG_DEV0_EPF0_DEVICE_ID 0x0002 |
| //#define cfgBIF_CFG_DEV0_EPF0_COMMAND 0x0004 |
| //#define cfgBIF_CFG_DEV0_EPF0_STATUS 0x0006 |
| //#define cfgBIF_CFG_DEV0_EPF0_REVISION_ID 0x0008 |
| //#define cfgBIF_CFG_DEV0_EPF0_PROG_INTERFACE 0x0009 |
| //#define cfgBIF_CFG_DEV0_EPF0_SUB_CLASS 0x000a |
| //#define cfgBIF_CFG_DEV0_EPF0_BASE_CLASS 0x000b |
| //#define cfgBIF_CFG_DEV0_EPF0_CACHE_LINE 0x000c |
| //#define cfgBIF_CFG_DEV0_EPF0_LATENCY 0x000d |
| //#define cfgBIF_CFG_DEV0_EPF0_HEADER 0x000e |
| //#define cfgBIF_CFG_DEV0_EPF0_BIST 0x000f |
| //#define cfgBIF_CFG_DEV0_EPF0_BASE_ADDR_1 0x0010 |
| //#define cfgBIF_CFG_DEV0_EPF0_BASE_ADDR_2 0x0014 |
| //#define cfgBIF_CFG_DEV0_EPF0_BASE_ADDR_3 0x0018 |
| //#define cfgBIF_CFG_DEV0_EPF0_BASE_ADDR_4 0x001c |
| //#define cfgBIF_CFG_DEV0_EPF0_BASE_ADDR_5 0x0020 |
| //#define cfgBIF_CFG_DEV0_EPF0_BASE_ADDR_6 0x0024 |
| //#define cfgBIF_CFG_DEV0_EPF0_ADAPTER_ID 0x002c |
| //#define cfgBIF_CFG_DEV0_EPF0_ROM_BASE_ADDR 0x0030 |
| //#define cfgBIF_CFG_DEV0_EPF0_CAP_PTR 0x0034 |
| //#define cfgBIF_CFG_DEV0_EPF0_INTERRUPT_LINE 0x003c |
| //#define cfgBIF_CFG_DEV0_EPF0_INTERRUPT_PIN 0x003d |
| //#define cfgBIF_CFG_DEV0_EPF0_MIN_GRANT 0x003e |
| //#define cfgBIF_CFG_DEV0_EPF0_MAX_LATENCY 0x003f |
| //#define cfgBIF_CFG_DEV0_EPF0_VENDOR_CAP_LIST 0x0048 |
| //#define cfgBIF_CFG_DEV0_EPF0_ADAPTER_ID_W 0x004c |
| //#define cfgBIF_CFG_DEV0_EPF0_PMI_CAP_LIST 0x0050 |
| //#define cfgBIF_CFG_DEV0_EPF0_PMI_CAP 0x0052 |
| //#define cfgBIF_CFG_DEV0_EPF0_PMI_STATUS_CNTL 0x0054 |
| //#define cfgBIF_CFG_DEV0_EPF0_PCIE_CAP_LIST 0x0064 |
| //#define cfgBIF_CFG_DEV0_EPF0_PCIE_CAP 0x0066 |
| //#define cfgBIF_CFG_DEV0_EPF0_DEVICE_CAP 0x0068 |
| //#define cfgBIF_CFG_DEV0_EPF0_DEVICE_CNTL 0x006c |
| //#define cfgBIF_CFG_DEV0_EPF0_DEVICE_STATUS 0x006e |
| //#define cfgBIF_CFG_DEV0_EPF0_LINK_CAP 0x0070 |
| //#define cfgBIF_CFG_DEV0_EPF0_LINK_CNTL 0x0074 |
| //#define cfgBIF_CFG_DEV0_EPF0_LINK_STATUS 0x0076 |
| //#define cfgBIF_CFG_DEV0_EPF0_DEVICE_CAP2 0x0088 |
| //#define cfgBIF_CFG_DEV0_EPF0_DEVICE_CNTL2 0x008c |
| //#define cfgBIF_CFG_DEV0_EPF0_DEVICE_STATUS2 0x008e |
| //#define cfgBIF_CFG_DEV0_EPF0_LINK_CAP2 0x0090 |
| //#define cfgBIF_CFG_DEV0_EPF0_LINK_CNTL2 0x0094 |
| //#define cfgBIF_CFG_DEV0_EPF0_LINK_STATUS2 0x0096 |
| //#define cfgBIF_CFG_DEV0_EPF0_SLOT_CAP2 0x0098 |
| //#define cfgBIF_CFG_DEV0_EPF0_SLOT_CNTL2 0x009c |
| //#define cfgBIF_CFG_DEV0_EPF0_SLOT_STATUS2 0x009e |
| //#define cfgBIF_CFG_DEV0_EPF0_MSI_CAP_LIST 0x00a0 |
| //#define cfgBIF_CFG_DEV0_EPF0_MSI_MSG_CNTL 0x00a2 |
| //#define cfgBIF_CFG_DEV0_EPF0_MSI_MSG_ADDR_LO 0x00a4 |
| //#define cfgBIF_CFG_DEV0_EPF0_MSI_MSG_ADDR_HI 0x00a8 |
| //#define cfgBIF_CFG_DEV0_EPF0_MSI_MSG_DATA 0x00a8 |
| //#define cfgBIF_CFG_DEV0_EPF0_MSI_MASK 0x00ac |
| //#define cfgBIF_CFG_DEV0_EPF0_MSI_MSG_DATA_64 0x00ac |
| //#define cfgBIF_CFG_DEV0_EPF0_MSI_MASK_64 0x00b0 |
| //#define cfgBIF_CFG_DEV0_EPF0_MSI_PENDING 0x00b0 |
| //#define cfgBIF_CFG_DEV0_EPF0_MSI_PENDING_64 0x00b4 |
| //#define cfgBIF_CFG_DEV0_EPF0_MSIX_CAP_LIST 0x00c0 |
| //#define cfgBIF_CFG_DEV0_EPF0_MSIX_MSG_CNTL 0x00c2 |
| //#define cfgBIF_CFG_DEV0_EPF0_MSIX_TABLE 0x00c4 |
| //#define cfgBIF_CFG_DEV0_EPF0_MSIX_PBA 0x00c8 |
| //#define cfgBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x0100 |
| //#define cfgBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR 0x0104 |
| //#define cfgBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC1 0x0108 |
| //#define cfgBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC2 0x010c |
| //#define cfgBIF_CFG_DEV0_EPF0_PCIE_VC_ENH_CAP_LIST 0x0110 |
| //#define cfgBIF_CFG_DEV0_EPF0_PCIE_PORT_VC_CAP_REG1 0x0114 |
| //#define cfgBIF_CFG_DEV0_EPF0_PCIE_PORT_VC_CAP_REG2 0x0118 |
| //#define cfgBIF_CFG_DEV0_EPF0_PCIE_PORT_VC_CNTL 0x011c |
| //#define cfgBIF_CFG_DEV0_EPF0_PCIE_PORT_VC_STATUS 0x011e |
| //#define cfgBIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_CAP 0x0120 |
| //#define cfgBIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_CNTL 0x0124 |
| //#define cfgBIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_STATUS 0x012a |
| //#define cfgBIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_CAP 0x012c |
| //#define cfgBIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_CNTL 0x0130 |
| //#define cfgBIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_STATUS 0x0136 |
| //#define cfgBIF_CFG_DEV0_EPF0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST 0x0140 |
| //#define cfgBIF_CFG_DEV0_EPF0_PCIE_DEV_SERIAL_NUM_DW1 0x0144 |
| //#define cfgBIF_CFG_DEV0_EPF0_PCIE_DEV_SERIAL_NUM_DW2 0x0148 |
| //#define cfgBIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x0150 |
| //#define cfgBIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS 0x0154 |
| //#define cfgBIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK 0x0158 |
| //#define cfgBIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY 0x015c |
| //#define cfgBIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_STATUS 0x0160 |
| //#define cfgBIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_MASK 0x0164 |
| //#define cfgBIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_CAP_CNTL 0x0168 |
| //#define cfgBIF_CFG_DEV0_EPF0_PCIE_HDR_LOG0 0x016c |
| //#define cfgBIF_CFG_DEV0_EPF0_PCIE_HDR_LOG1 0x0170 |
| //#define cfgBIF_CFG_DEV0_EPF0_PCIE_HDR_LOG2 0x0174 |
| //#define cfgBIF_CFG_DEV0_EPF0_PCIE_HDR_LOG3 0x0178 |
| //#define cfgBIF_CFG_DEV0_EPF0_PCIE_TLP_PREFIX_LOG0 0x0188 |
| //#define cfgBIF_CFG_DEV0_EPF0_PCIE_TLP_PREFIX_LOG1 0x018c |
| //#define cfgBIF_CFG_DEV0_EPF0_PCIE_TLP_PREFIX_LOG2 0x0190 |
| //#define cfgBIF_CFG_DEV0_EPF0_PCIE_TLP_PREFIX_LOG3 0x0194 |
| //#define cfgBIF_CFG_DEV0_EPF0_PCIE_BAR_ENH_CAP_LIST 0x0200 |
| //#define cfgBIF_CFG_DEV0_EPF0_PCIE_BAR1_CAP 0x0204 |
| //#define cfgBIF_CFG_DEV0_EPF0_PCIE_BAR1_CNTL 0x0208 |
| //#define cfgBIF_CFG_DEV0_EPF0_PCIE_BAR2_CAP 0x020c |
| //#define cfgBIF_CFG_DEV0_EPF0_PCIE_BAR2_CNTL 0x0210 |
| //#define cfgBIF_CFG_DEV0_EPF0_PCIE_BAR3_CAP 0x0214 |
| //#define cfgBIF_CFG_DEV0_EPF0_PCIE_BAR3_CNTL 0x0218 |
| //#define cfgBIF_CFG_DEV0_EPF0_PCIE_BAR4_CAP 0x021c |
| //#define cfgBIF_CFG_DEV0_EPF0_PCIE_BAR4_CNTL 0x0220 |
| //#define cfgBIF_CFG_DEV0_EPF0_PCIE_BAR5_CAP 0x0224 |
| //#define cfgBIF_CFG_DEV0_EPF0_PCIE_BAR5_CNTL 0x0228 |
| //#define cfgBIF_CFG_DEV0_EPF0_PCIE_BAR6_CAP 0x022c |
| //#define cfgBIF_CFG_DEV0_EPF0_PCIE_BAR6_CNTL 0x0230 |
| //#define cfgBIF_CFG_DEV0_EPF0_PCIE_PWR_BUDGET_ENH_CAP_LIST 0x0240 |
| //#define cfgBIF_CFG_DEV0_EPF0_PCIE_PWR_BUDGET_DATA_SELECT 0x0244 |
| //#define cfgBIF_CFG_DEV0_EPF0_PCIE_PWR_BUDGET_DATA 0x0248 |
| //#define cfgBIF_CFG_DEV0_EPF0_PCIE_PWR_BUDGET_CAP 0x024c |
| //#define cfgBIF_CFG_DEV0_EPF0_PCIE_DPA_ENH_CAP_LIST 0x0250 |
| //#define cfgBIF_CFG_DEV0_EPF0_PCIE_DPA_CAP 0x0254 |
| //#define cfgBIF_CFG_DEV0_EPF0_PCIE_DPA_LATENCY_INDICATOR 0x0258 |
| //#define cfgBIF_CFG_DEV0_EPF0_PCIE_DPA_STATUS 0x025c |
| //#define cfgBIF_CFG_DEV0_EPF0_PCIE_DPA_CNTL 0x025e |
| //#define cfgBIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0 0x0260 |
| //#define cfgBIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1 0x0261 |
| //#define cfgBIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2 0x0262 |
| //#define cfgBIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3 0x0263 |
| //#define cfgBIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4 0x0264 |
| //#define cfgBIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5 0x0265 |
| //#define cfgBIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6 0x0266 |
| //#define cfgBIF_CFG_DEV0_EPF0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7 0x0267 |
| //#define cfgBIF_CFG_DEV0_EPF0_PCIE_SECONDARY_ENH_CAP_LIST 0x0270 |
| //#define cfgBIF_CFG_DEV0_EPF0_PCIE_LINK_CNTL3 0x0274 |
| //#define cfgBIF_CFG_DEV0_EPF0_PCIE_LANE_ERROR_STATUS 0x0278 |
| //#define cfgBIF_CFG_DEV0_EPF0_PCIE_LANE_0_EQUALIZATION_CNTL 0x027c |
| //#define cfgBIF_CFG_DEV0_EPF0_PCIE_LANE_1_EQUALIZATION_CNTL 0x027e |
| //#define cfgBIF_CFG_DEV0_EPF0_PCIE_LANE_2_EQUALIZATION_CNTL 0x0280 |
| //#define cfgBIF_CFG_DEV0_EPF0_PCIE_LANE_3_EQUALIZATION_CNTL 0x0282 |
| //#define cfgBIF_CFG_DEV0_EPF0_PCIE_LANE_4_EQUALIZATION_CNTL 0x0284 |
| //#define cfgBIF_CFG_DEV0_EPF0_PCIE_LANE_5_EQUALIZATION_CNTL 0x0286 |
| //#define cfgBIF_CFG_DEV0_EPF0_PCIE_LANE_6_EQUALIZATION_CNTL 0x0288 |
| //#define cfgBIF_CFG_DEV0_EPF0_PCIE_LANE_7_EQUALIZATION_CNTL 0x028a |
| //#define cfgBIF_CFG_DEV0_EPF0_PCIE_LANE_8_EQUALIZATION_CNTL 0x028c |
| //#define cfgBIF_CFG_DEV0_EPF0_PCIE_LANE_9_EQUALIZATION_CNTL 0x028e |
| //#define cfgBIF_CFG_DEV0_EPF0_PCIE_LANE_10_EQUALIZATION_CNTL 0x0290 |
| //#define cfgBIF_CFG_DEV0_EPF0_PCIE_LANE_11_EQUALIZATION_CNTL 0x0292 |
| //#define cfgBIF_CFG_DEV0_EPF0_PCIE_LANE_12_EQUALIZATION_CNTL 0x0294 |
| //#define cfgBIF_CFG_DEV0_EPF0_PCIE_LANE_13_EQUALIZATION_CNTL 0x0296 |
| //#define cfgBIF_CFG_DEV0_EPF0_PCIE_LANE_14_EQUALIZATION_CNTL 0x0298 |
| //#define cfgBIF_CFG_DEV0_EPF0_PCIE_LANE_15_EQUALIZATION_CNTL 0x029a |
| //#define cfgBIF_CFG_DEV0_EPF0_PCIE_ACS_ENH_CAP_LIST 0x02a0 |
| //#define cfgBIF_CFG_DEV0_EPF0_PCIE_ACS_CAP 0x02a4 |
| //#define cfgBIF_CFG_DEV0_EPF0_PCIE_ACS_CNTL 0x02a6 |
| //#define cfgBIF_CFG_DEV0_EPF0_PCIE_ATS_ENH_CAP_LIST 0x02b0 |
| //#define cfgBIF_CFG_DEV0_EPF0_PCIE_ATS_CAP 0x02b4 |
| //#define cfgBIF_CFG_DEV0_EPF0_PCIE_ATS_CNTL 0x02b6 |
| //#define cfgBIF_CFG_DEV0_EPF0_PCIE_PAGE_REQ_ENH_CAP_LIST 0x02c0 |
| //#define cfgBIF_CFG_DEV0_EPF0_PCIE_PAGE_REQ_CNTL 0x02c4 |
| //#define cfgBIF_CFG_DEV0_EPF0_PCIE_PAGE_REQ_STATUS 0x02c6 |
| //#define cfgBIF_CFG_DEV0_EPF0_PCIE_OUTSTAND_PAGE_REQ_CAPACITY 0x02c8 |
| //#define cfgBIF_CFG_DEV0_EPF0_PCIE_OUTSTAND_PAGE_REQ_ALLOC 0x02cc |
| //#define cfgBIF_CFG_DEV0_EPF0_PCIE_PASID_ENH_CAP_LIST 0x02d0 |
| //#define cfgBIF_CFG_DEV0_EPF0_PCIE_PASID_CAP 0x02d4 |
| //#define cfgBIF_CFG_DEV0_EPF0_PCIE_PASID_CNTL 0x02d6 |
| //#define cfgBIF_CFG_DEV0_EPF0_PCIE_TPH_REQR_ENH_CAP_LIST 0x02e0 |
| //#define cfgBIF_CFG_DEV0_EPF0_PCIE_TPH_REQR_CAP 0x02e4 |
| //#define cfgBIF_CFG_DEV0_EPF0_PCIE_TPH_REQR_CNTL 0x02e8 |
| //#define cfgBIF_CFG_DEV0_EPF0_PCIE_MC_ENH_CAP_LIST 0x02f0 |
| //#define cfgBIF_CFG_DEV0_EPF0_PCIE_MC_CAP 0x02f4 |
| //#define cfgBIF_CFG_DEV0_EPF0_PCIE_MC_CNTL 0x02f6 |
| //#define cfgBIF_CFG_DEV0_EPF0_PCIE_MC_ADDR0 0x02f8 |
| //#define cfgBIF_CFG_DEV0_EPF0_PCIE_MC_ADDR1 0x02fc |
| //#define cfgBIF_CFG_DEV0_EPF0_PCIE_MC_RCV0 0x0300 |
| //#define cfgBIF_CFG_DEV0_EPF0_PCIE_MC_RCV1 0x0304 |
| //#define cfgBIF_CFG_DEV0_EPF0_PCIE_MC_BLOCK_ALL0 0x0308 |
| //#define cfgBIF_CFG_DEV0_EPF0_PCIE_MC_BLOCK_ALL1 0x030c |
| //#define cfgBIF_CFG_DEV0_EPF0_PCIE_MC_BLOCK_UNTRANSLATED_0 0x0310 |
| //#define cfgBIF_CFG_DEV0_EPF0_PCIE_MC_BLOCK_UNTRANSLATED_1 0x0314 |
| //#define cfgBIF_CFG_DEV0_EPF0_PCIE_LTR_ENH_CAP_LIST 0x0320 |
| //#define cfgBIF_CFG_DEV0_EPF0_PCIE_LTR_CAP 0x0324 |
| //#define cfgBIF_CFG_DEV0_EPF0_PCIE_ARI_ENH_CAP_LIST 0x0328 |
| //#define cfgBIF_CFG_DEV0_EPF0_PCIE_ARI_CAP 0x032c |
| //#define cfgBIF_CFG_DEV0_EPF0_PCIE_ARI_CNTL 0x032e |
| //#define cfgBIF_CFG_DEV0_EPF0_PCIE_SRIOV_ENH_CAP_LIST 0x0330 |
| //#define cfgBIF_CFG_DEV0_EPF0_PCIE_SRIOV_CAP 0x0334 |
| //#define cfgBIF_CFG_DEV0_EPF0_PCIE_SRIOV_CONTROL 0x0338 |
| //#define cfgBIF_CFG_DEV0_EPF0_PCIE_SRIOV_STATUS 0x033a |
| //#define cfgBIF_CFG_DEV0_EPF0_PCIE_SRIOV_INITIAL_VFS 0x033c |
| //#define cfgBIF_CFG_DEV0_EPF0_PCIE_SRIOV_TOTAL_VFS 0x033e |
| //#define cfgBIF_CFG_DEV0_EPF0_PCIE_SRIOV_NUM_VFS 0x0340 |
| //#define cfgBIF_CFG_DEV0_EPF0_PCIE_SRIOV_FUNC_DEP_LINK 0x0342 |
| //#define cfgBIF_CFG_DEV0_EPF0_PCIE_SRIOV_FIRST_VF_OFFSET 0x0344 |
| //#define cfgBIF_CFG_DEV0_EPF0_PCIE_SRIOV_VF_STRIDE 0x0346 |
| //#define cfgBIF_CFG_DEV0_EPF0_PCIE_SRIOV_VF_DEVICE_ID 0x034a |
| //#define cfgBIF_CFG_DEV0_EPF0_PCIE_SRIOV_SUPPORTED_PAGE_SIZE 0x034c |
| //#define cfgBIF_CFG_DEV0_EPF0_PCIE_SRIOV_SYSTEM_PAGE_SIZE 0x0350 |
| //#define cfgBIF_CFG_DEV0_EPF0_PCIE_SRIOV_VF_BASE_ADDR_0 0x0354 |
| //#define cfgBIF_CFG_DEV0_EPF0_PCIE_SRIOV_VF_BASE_ADDR_1 0x0358 |
| //#define cfgBIF_CFG_DEV0_EPF0_PCIE_SRIOV_VF_BASE_ADDR_2 0x035c |
| //#define cfgBIF_CFG_DEV0_EPF0_PCIE_SRIOV_VF_BASE_ADDR_3 0x0360 |
| //#define cfgBIF_CFG_DEV0_EPF0_PCIE_SRIOV_VF_BASE_ADDR_4 0x0364 |
| //#define cfgBIF_CFG_DEV0_EPF0_PCIE_SRIOV_VF_BASE_ADDR_5 0x0368 |
| //#define cfgBIF_CFG_DEV0_EPF0_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET 0x036c |
| //#define cfgBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV 0x0400 |
| //#define cfgBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV 0x0404 |
| //#define cfgBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW 0x0408 |
| //#define cfgBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE 0x040c |
| //#define cfgBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS 0x0410 |
| //#define cfgBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_RESET_CONTROL 0x0414 |
| //#define cfgBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0 0x0418 |
| //#define cfgBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1 0x041c |
| //#define cfgBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2 0x0420 |
| //#define cfgBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT 0x0424 |
| //#define cfgBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB 0x0428 |
| //#define cfgBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS 0x042c |
| //#define cfgBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB 0x0430 |
| //#define cfgBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB 0x0434 |
| //#define cfgBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB 0x0438 |
| //#define cfgBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB 0x043c |
| //#define cfgBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB 0x0440 |
| //#define cfgBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB 0x0444 |
| //#define cfgBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB 0x0448 |
| //#define cfgBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB 0x044c |
| //#define cfgBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB 0x0450 |
| //#define cfgBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB 0x0454 |
| //#define cfgBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB 0x0458 |
| //#define cfgBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB 0x045c |
| //#define cfgBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB 0x0460 |
| //#define cfgBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB 0x0464 |
| //#define cfgBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB 0x0468 |
| //#define cfgBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB 0x046c |
| //#define cfgBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW0 0x0470 |
| //#define cfgBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW1 0x0474 |
| //#define cfgBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW2 0x0478 |
| //#define cfgBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW3 0x047c |
| //#define cfgBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW4 0x0480 |
| //#define cfgBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW5 0x0484 |
| //#define cfgBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW6 0x0488 |
| //#define cfgBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW7 0x048c |
| //#define cfgBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW8 0x0490 |
| //#define cfgBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW0 0x04a0 |
| //#define cfgBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW1 0x04a4 |
| //#define cfgBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW2 0x04a8 |
| //#define cfgBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW3 0x04ac |
| //#define cfgBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW4 0x04b0 |
| //#define cfgBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW5 0x04b4 |
| //#define cfgBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW6 0x04b8 |
| //#define cfgBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW7 0x04bc |
| //#define cfgBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW8 0x04c0 |
| //#define cfgBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW0 0x04d0 |
| //#define cfgBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW1 0x04d4 |
| //#define cfgBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW2 0x04d8 |
| //#define cfgBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW3 0x04dc |
| //#define cfgBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW4 0x04e0 |
| //#define cfgBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW5 0x04e4 |
| //#define cfgBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW6 0x04e8 |
| //#define cfgBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW7 0x04ec |
| //#define cfgBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW8 0x04f0 |
| |
| |
| // addressBlock: nbio_nbif0_bif_cfg_dev0_epf1_bifcfgdecp |
| // base address: 0x0 |
| #define cfgBIF_CFG_DEV0_EPF1_0_VENDOR_ID 0x0000 |
| #define cfgBIF_CFG_DEV0_EPF1_0_DEVICE_ID 0x0002 |
| #define cfgBIF_CFG_DEV0_EPF1_0_COMMAND 0x0004 |
| #define cfgBIF_CFG_DEV0_EPF1_0_STATUS 0x0006 |
| #define cfgBIF_CFG_DEV0_EPF1_0_REVISION_ID 0x0008 |
| #define cfgBIF_CFG_DEV0_EPF1_0_PROG_INTERFACE 0x0009 |
| #define cfgBIF_CFG_DEV0_EPF1_0_SUB_CLASS 0x000a |
| #define cfgBIF_CFG_DEV0_EPF1_0_BASE_CLASS 0x000b |
| #define cfgBIF_CFG_DEV0_EPF1_0_CACHE_LINE 0x000c |
| #define cfgBIF_CFG_DEV0_EPF1_0_LATENCY 0x000d |
| #define cfgBIF_CFG_DEV0_EPF1_0_HEADER 0x000e |
| #define cfgBIF_CFG_DEV0_EPF1_0_BIST 0x000f |
| #define cfgBIF_CFG_DEV0_EPF1_0_BASE_ADDR_1 0x0010 |
| #define cfgBIF_CFG_DEV0_EPF1_0_BASE_ADDR_2 0x0014 |
| #define cfgBIF_CFG_DEV0_EPF1_0_BASE_ADDR_3 0x0018 |
| #define cfgBIF_CFG_DEV0_EPF1_0_BASE_ADDR_4 0x001c |
| #define cfgBIF_CFG_DEV0_EPF1_0_BASE_ADDR_5 0x0020 |
| #define cfgBIF_CFG_DEV0_EPF1_0_BASE_ADDR_6 0x0024 |
| #define cfgBIF_CFG_DEV0_EPF1_0_ADAPTER_ID 0x002c |
| #define cfgBIF_CFG_DEV0_EPF1_0_ROM_BASE_ADDR 0x0030 |
| #define cfgBIF_CFG_DEV0_EPF1_0_CAP_PTR 0x0034 |
| #define cfgBIF_CFG_DEV0_EPF1_0_INTERRUPT_LINE 0x003c |
| #define cfgBIF_CFG_DEV0_EPF1_0_INTERRUPT_PIN 0x003d |
| #define cfgBIF_CFG_DEV0_EPF1_0_MIN_GRANT 0x003e |
| #define cfgBIF_CFG_DEV0_EPF1_0_MAX_LATENCY 0x003f |
| #define cfgBIF_CFG_DEV0_EPF1_0_VENDOR_CAP_LIST 0x0048 |
| #define cfgBIF_CFG_DEV0_EPF1_0_ADAPTER_ID_W 0x004c |
| #define cfgBIF_CFG_DEV0_EPF1_0_PMI_CAP_LIST 0x0050 |
| #define cfgBIF_CFG_DEV0_EPF1_0_PMI_CAP 0x0052 |
| #define cfgBIF_CFG_DEV0_EPF1_0_PMI_STATUS_CNTL 0x0054 |
| #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_CAP_LIST 0x0064 |
| #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_CAP 0x0066 |
| #define cfgBIF_CFG_DEV0_EPF1_0_DEVICE_CAP 0x0068 |
| #define cfgBIF_CFG_DEV0_EPF1_0_DEVICE_CNTL 0x006c |
| #define cfgBIF_CFG_DEV0_EPF1_0_DEVICE_STATUS 0x006e |
| #define cfgBIF_CFG_DEV0_EPF1_0_LINK_CAP 0x0070 |
| #define cfgBIF_CFG_DEV0_EPF1_0_LINK_CNTL 0x0074 |
| #define cfgBIF_CFG_DEV0_EPF1_0_LINK_STATUS 0x0076 |
| #define cfgBIF_CFG_DEV0_EPF1_0_DEVICE_CAP2 0x0088 |
| #define cfgBIF_CFG_DEV0_EPF1_0_DEVICE_CNTL2 0x008c |
| #define cfgBIF_CFG_DEV0_EPF1_0_DEVICE_STATUS2 0x008e |
| #define cfgBIF_CFG_DEV0_EPF1_0_LINK_CAP2 0x0090 |
| #define cfgBIF_CFG_DEV0_EPF1_0_LINK_CNTL2 0x0094 |
| #define cfgBIF_CFG_DEV0_EPF1_0_LINK_STATUS2 0x0096 |
| #define cfgBIF_CFG_DEV0_EPF1_0_SLOT_CAP2 0x0098 |
| #define cfgBIF_CFG_DEV0_EPF1_0_SLOT_CNTL2 0x009c |
| #define cfgBIF_CFG_DEV0_EPF1_0_SLOT_STATUS2 0x009e |
| #define cfgBIF_CFG_DEV0_EPF1_0_MSI_CAP_LIST 0x00a0 |
| #define cfgBIF_CFG_DEV0_EPF1_0_MSI_MSG_CNTL 0x00a2 |
| #define cfgBIF_CFG_DEV0_EPF1_0_MSI_MSG_ADDR_LO 0x00a4 |
| #define cfgBIF_CFG_DEV0_EPF1_0_MSI_MSG_ADDR_HI 0x00a8 |
| #define cfgBIF_CFG_DEV0_EPF1_0_MSI_MSG_DATA 0x00a8 |
| #define cfgBIF_CFG_DEV0_EPF1_0_MSI_MASK 0x00ac |
| #define cfgBIF_CFG_DEV0_EPF1_0_MSI_MSG_DATA_64 0x00ac |
| #define cfgBIF_CFG_DEV0_EPF1_0_MSI_MASK_64 0x00b0 |
| #define cfgBIF_CFG_DEV0_EPF1_0_MSI_PENDING 0x00b0 |
| #define cfgBIF_CFG_DEV0_EPF1_0_MSI_PENDING_64 0x00b4 |
| #define cfgBIF_CFG_DEV0_EPF1_0_MSIX_CAP_LIST 0x00c0 |
| #define cfgBIF_CFG_DEV0_EPF1_0_MSIX_MSG_CNTL 0x00c2 |
| #define cfgBIF_CFG_DEV0_EPF1_0_MSIX_TABLE 0x00c4 |
| #define cfgBIF_CFG_DEV0_EPF1_0_MSIX_PBA 0x00c8 |
| #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x0100 |
| #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR 0x0104 |
| #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC1 0x0108 |
| #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC2 0x010c |
| #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VC_ENH_CAP_LIST 0x0110 |
| #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_PORT_VC_CAP_REG1 0x0114 |
| #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_PORT_VC_CAP_REG2 0x0118 |
| #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_PORT_VC_CNTL 0x011c |
| #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_PORT_VC_STATUS 0x011e |
| #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VC0_RESOURCE_CAP 0x0120 |
| #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VC0_RESOURCE_CNTL 0x0124 |
| #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VC0_RESOURCE_STATUS 0x012a |
| #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VC1_RESOURCE_CAP 0x012c |
| #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VC1_RESOURCE_CNTL 0x0130 |
| #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VC1_RESOURCE_STATUS 0x0136 |
| #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST 0x0140 |
| #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_DEV_SERIAL_NUM_DW1 0x0144 |
| #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_DEV_SERIAL_NUM_DW2 0x0148 |
| #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x0150 |
| #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_STATUS 0x0154 |
| #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_MASK 0x0158 |
| #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_UNCORR_ERR_SEVERITY 0x015c |
| #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_STATUS 0x0160 |
| #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_CORR_ERR_MASK 0x0164 |
| #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_ADV_ERR_CAP_CNTL 0x0168 |
| #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_HDR_LOG0 0x016c |
| #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_HDR_LOG1 0x0170 |
| #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_HDR_LOG2 0x0174 |
| #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_HDR_LOG3 0x0178 |
| #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_TLP_PREFIX_LOG0 0x0188 |
| #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_TLP_PREFIX_LOG1 0x018c |
| #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_TLP_PREFIX_LOG2 0x0190 |
| #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_TLP_PREFIX_LOG3 0x0194 |
| #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_BAR_ENH_CAP_LIST 0x0200 |
| #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_BAR1_CAP 0x0204 |
| #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_BAR1_CNTL 0x0208 |
| #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_BAR2_CAP 0x020c |
| #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_BAR2_CNTL 0x0210 |
| #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_BAR3_CAP 0x0214 |
| #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_BAR3_CNTL 0x0218 |
| #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_BAR4_CAP 0x021c |
| #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_BAR4_CNTL 0x0220 |
| #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_BAR5_CAP 0x0224 |
| #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_BAR5_CNTL 0x0228 |
| #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_BAR6_CAP 0x022c |
| #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_BAR6_CNTL 0x0230 |
| #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_ENH_CAP_LIST 0x0240 |
| #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_DATA_SELECT 0x0244 |
| #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_DATA 0x0248 |
| #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_PWR_BUDGET_CAP 0x024c |
| #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_DPA_ENH_CAP_LIST 0x0250 |
| #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_DPA_CAP 0x0254 |
| #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_DPA_LATENCY_INDICATOR 0x0258 |
| #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_DPA_STATUS 0x025c |
| #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_DPA_CNTL 0x025e |
| #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0 0x0260 |
| #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1 0x0261 |
| #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2 0x0262 |
| #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3 0x0263 |
| #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4 0x0264 |
| #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5 0x0265 |
| #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6 0x0266 |
| #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7 0x0267 |
| #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SECONDARY_ENH_CAP_LIST 0x0270 |
| #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_LINK_CNTL3 0x0274 |
| #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_LANE_ERROR_STATUS 0x0278 |
| #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_LANE_0_EQUALIZATION_CNTL 0x027c |
| #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_LANE_1_EQUALIZATION_CNTL 0x027e |
| #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_LANE_2_EQUALIZATION_CNTL 0x0280 |
| #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_LANE_3_EQUALIZATION_CNTL 0x0282 |
| #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_LANE_4_EQUALIZATION_CNTL 0x0284 |
| #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_LANE_5_EQUALIZATION_CNTL 0x0286 |
| #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_LANE_6_EQUALIZATION_CNTL 0x0288 |
| #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_LANE_7_EQUALIZATION_CNTL 0x028a |
| #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_LANE_8_EQUALIZATION_CNTL 0x028c |
| #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_LANE_9_EQUALIZATION_CNTL 0x028e |
| #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_LANE_10_EQUALIZATION_CNTL 0x0290 |
| #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_LANE_11_EQUALIZATION_CNTL 0x0292 |
| #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_LANE_12_EQUALIZATION_CNTL 0x0294 |
| #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_LANE_13_EQUALIZATION_CNTL 0x0296 |
| #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_LANE_14_EQUALIZATION_CNTL 0x0298 |
| #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_LANE_15_EQUALIZATION_CNTL 0x029a |
| #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_ACS_ENH_CAP_LIST 0x02a0 |
| #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_ACS_CAP 0x02a4 |
| #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_ACS_CNTL 0x02a6 |
| #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_ATS_ENH_CAP_LIST 0x02b0 |
| #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_ATS_CAP 0x02b4 |
| #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_ATS_CNTL 0x02b6 |
| #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_PAGE_REQ_ENH_CAP_LIST 0x02c0 |
| #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_PAGE_REQ_CNTL 0x02c4 |
| #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_PAGE_REQ_STATUS 0x02c6 |
| #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_OUTSTAND_PAGE_REQ_CAPACITY 0x02c8 |
| #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_OUTSTAND_PAGE_REQ_ALLOC 0x02cc |
| #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_PASID_ENH_CAP_LIST 0x02d0 |
| #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_PASID_CAP 0x02d4 |
| #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_PASID_CNTL 0x02d6 |
| #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_TPH_REQR_ENH_CAP_LIST 0x02e0 |
| #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_TPH_REQR_CAP 0x02e4 |
| #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_TPH_REQR_CNTL 0x02e8 |
| #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_MC_ENH_CAP_LIST 0x02f0 |
| #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_MC_CAP 0x02f4 |
| #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_MC_CNTL 0x02f6 |
| #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_MC_ADDR0 0x02f8 |
| #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_MC_ADDR1 0x02fc |
| #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_MC_RCV0 0x0300 |
| #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_MC_RCV1 0x0304 |
| #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_MC_BLOCK_ALL0 0x0308 |
| #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_MC_BLOCK_ALL1 0x030c |
| #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_MC_BLOCK_UNTRANSLATED_0 0x0310 |
| #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_MC_BLOCK_UNTRANSLATED_1 0x0314 |
| #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_LTR_ENH_CAP_LIST 0x0320 |
| #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_LTR_CAP 0x0324 |
| #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_ARI_ENH_CAP_LIST 0x0328 |
| #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_ARI_CAP 0x032c |
| #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_ARI_CNTL 0x032e |
| #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_ENH_CAP_LIST 0x0330 |
| #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_CAP 0x0334 |
| #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_CONTROL 0x0338 |
| #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_STATUS 0x033a |
| #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_INITIAL_VFS 0x033c |
| #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_TOTAL_VFS 0x033e |
| #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_NUM_VFS 0x0340 |
| #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_FUNC_DEP_LINK 0x0342 |
| #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_FIRST_VF_OFFSET 0x0344 |
| #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_STRIDE 0x0346 |
| #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_DEVICE_ID 0x034a |
| #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_SUPPORTED_PAGE_SIZE 0x034c |
| #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_SYSTEM_PAGE_SIZE 0x0350 |
| #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_BASE_ADDR_0 0x0354 |
| #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_BASE_ADDR_1 0x0358 |
| #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_BASE_ADDR_2 0x035c |
| #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_BASE_ADDR_3 0x0360 |
| #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_BASE_ADDR_4 0x0364 |
| #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_BASE_ADDR_5 0x0368 |
| #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET 0x036c |
| #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV 0x0400 |
| #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV 0x0404 |
| #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW 0x0408 |
| #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE 0x040c |
| #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS 0x0410 |
| #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_RESET_CONTROL 0x0414 |
| #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0 0x0418 |
| #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1 0x041c |
| #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2 0x0420 |
| #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_CONTEXT 0x0424 |
| #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB 0x0428 |
| #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS 0x042c |
| #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF0_FB 0x0430 |
| #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF1_FB 0x0434 |
| #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF2_FB 0x0438 |
| #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF3_FB 0x043c |
| #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF4_FB 0x0440 |
| #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF5_FB 0x0444 |
| #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF6_FB 0x0448 |
| #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF7_FB 0x044c |
| #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF8_FB 0x0450 |
| #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF9_FB 0x0454 |
| #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF10_FB 0x0458 |
| #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF11_FB 0x045c |
| #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF12_FB 0x0460 |
| #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF13_FB 0x0464 |
| #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF14_FB 0x0468 |
| #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VF15_FB 0x046c |
| #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW0 0x0470 |
| #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW1 0x0474 |
| #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW2 0x0478 |
| #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW3 0x047c |
| #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW4 0x0480 |
| #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW5 0x0484 |
| #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW6 0x0488 |
| #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW7 0x048c |
| #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_UVDSCH_DW8 0x0490 |
| #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW0 0x04a0 |
| #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW1 0x04a4 |
| #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW2 0x04a8 |
| #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW3 0x04ac |
| #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW4 0x04b0 |
| #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW5 0x04b4 |
| #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW6 0x04b8 |
| #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW7 0x04bc |
| #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_VCESCH_DW8 0x04c0 |
| #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW0 0x04d0 |
| #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW1 0x04d4 |
| #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW2 0x04d8 |
| #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW3 0x04dc |
| #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW4 0x04e0 |
| #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW5 0x04e4 |
| #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW6 0x04e8 |
| #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW7 0x04ec |
| #define cfgBIF_CFG_DEV0_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_GFXSCH_DW8 0x04f0 |
| |
| |
| // addressBlock: nbio_nbif0_bif_cfg_dev0_epf2_bifcfgdecp |
| // base address: 0x0 |
| #define cfgBIF_CFG_DEV0_EPF2_0_VENDOR_ID 0x0000 |
| #define cfgBIF_CFG_DEV0_EPF2_0_DEVICE_ID 0x0002 |
| #define cfgBIF_CFG_DEV0_EPF2_0_COMMAND 0x0004 |
| #define cfgBIF_CFG_DEV0_EPF2_0_STATUS 0x0006 |
| #define cfgBIF_CFG_DEV0_EPF2_0_REVISION_ID 0x0008 |
| #define cfgBIF_CFG_DEV0_EPF2_0_PROG_INTERFACE 0x0009 |
| #define cfgBIF_CFG_DEV0_EPF2_0_SUB_CLASS 0x000a |
| #define cfgBIF_CFG_DEV0_EPF2_0_BASE_CLASS 0x000b |
| #define cfgBIF_CFG_DEV0_EPF2_0_CACHE_LINE 0x000c |
| #define cfgBIF_CFG_DEV0_EPF2_0_LATENCY 0x000d |
| #define cfgBIF_CFG_DEV0_EPF2_0_HEADER 0x000e |
| #define cfgBIF_CFG_DEV0_EPF2_0_BIST 0x000f |
| #define cfgBIF_CFG_DEV0_EPF2_0_BASE_ADDR_1 0x0010 |
| #define cfgBIF_CFG_DEV0_EPF2_0_BASE_ADDR_2 0x0014 |
| #define cfgBIF_CFG_DEV0_EPF2_0_BASE_ADDR_3 0x0018 |
| #define cfgBIF_CFG_DEV0_EPF2_0_BASE_ADDR_4 0x001c |
| #define cfgBIF_CFG_DEV0_EPF2_0_BASE_ADDR_5 0x0020 |
| #define cfgBIF_CFG_DEV0_EPF2_0_BASE_ADDR_6 0x0024 |
| #define cfgBIF_CFG_DEV0_EPF2_0_ADAPTER_ID 0x002c |
| #define cfgBIF_CFG_DEV0_EPF2_0_ROM_BASE_ADDR 0x0030 |
| #define cfgBIF_CFG_DEV0_EPF2_0_CAP_PTR 0x0034 |
| #define cfgBIF_CFG_DEV0_EPF2_0_INTERRUPT_LINE 0x003c |
| #define cfgBIF_CFG_DEV0_EPF2_0_INTERRUPT_PIN 0x003d |
| #define cfgBIF_CFG_DEV0_EPF2_0_MIN_GRANT 0x003e |
| #define cfgBIF_CFG_DEV0_EPF2_0_MAX_LATENCY 0x003f |
| #define cfgBIF_CFG_DEV0_EPF2_0_VENDOR_CAP_LIST 0x0048 |
| #define cfgBIF_CFG_DEV0_EPF2_0_ADAPTER_ID_W 0x004c |
| #define cfgBIF_CFG_DEV0_EPF2_0_PMI_CAP_LIST 0x0050 |
| #define cfgBIF_CFG_DEV0_EPF2_0_PMI_CAP 0x0052 |
| #define cfgBIF_CFG_DEV0_EPF2_0_PMI_STATUS_CNTL 0x0054 |
| #define cfgBIF_CFG_DEV0_EPF2_0_SBRN 0x0060 |
| #define cfgBIF_CFG_DEV0_EPF2_0_FLADJ 0x0061 |
| #define cfgBIF_CFG_DEV0_EPF2_0_DBESL_DBESLD 0x0062 |
| #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_CAP_LIST 0x0064 |
| #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_CAP 0x0066 |
| #define cfgBIF_CFG_DEV0_EPF2_0_DEVICE_CAP 0x0068 |
| #define cfgBIF_CFG_DEV0_EPF2_0_DEVICE_CNTL 0x006c |
| #define cfgBIF_CFG_DEV0_EPF2_0_DEVICE_STATUS 0x006e |
| #define cfgBIF_CFG_DEV0_EPF2_0_LINK_CAP 0x0070 |
| #define cfgBIF_CFG_DEV0_EPF2_0_LINK_CNTL 0x0074 |
| #define cfgBIF_CFG_DEV0_EPF2_0_LINK_STATUS 0x0076 |
| #define cfgBIF_CFG_DEV0_EPF2_0_DEVICE_CAP2 0x0088 |
| #define cfgBIF_CFG_DEV0_EPF2_0_DEVICE_CNTL2 0x008c |
| #define cfgBIF_CFG_DEV0_EPF2_0_DEVICE_STATUS2 0x008e |
| #define cfgBIF_CFG_DEV0_EPF2_0_LINK_CAP2 0x0090 |
| #define cfgBIF_CFG_DEV0_EPF2_0_LINK_CNTL2 0x0094 |
| #define cfgBIF_CFG_DEV0_EPF2_0_LINK_STATUS2 0x0096 |
| #define cfgBIF_CFG_DEV0_EPF2_0_SLOT_CAP2 0x0098 |
| #define cfgBIF_CFG_DEV0_EPF2_0_SLOT_CNTL2 0x009c |
| #define cfgBIF_CFG_DEV0_EPF2_0_SLOT_STATUS2 0x009e |
| #define cfgBIF_CFG_DEV0_EPF2_0_MSI_CAP_LIST 0x00a0 |
| #define cfgBIF_CFG_DEV0_EPF2_0_MSI_MSG_CNTL 0x00a2 |
| #define cfgBIF_CFG_DEV0_EPF2_0_MSI_MSG_ADDR_LO 0x00a4 |
| #define cfgBIF_CFG_DEV0_EPF2_0_MSI_MSG_ADDR_HI 0x00a8 |
| #define cfgBIF_CFG_DEV0_EPF2_0_MSI_MSG_DATA 0x00a8 |
| #define cfgBIF_CFG_DEV0_EPF2_0_MSI_MASK 0x00ac |
| #define cfgBIF_CFG_DEV0_EPF2_0_MSI_MSG_DATA_64 0x00ac |
| #define cfgBIF_CFG_DEV0_EPF2_0_MSI_MASK_64 0x00b0 |
| #define cfgBIF_CFG_DEV0_EPF2_0_MSI_PENDING 0x00b0 |
| #define cfgBIF_CFG_DEV0_EPF2_0_MSI_PENDING_64 0x00b4 |
| #define cfgBIF_CFG_DEV0_EPF2_0_MSIX_CAP_LIST 0x00c0 |
| #define cfgBIF_CFG_DEV0_EPF2_0_MSIX_MSG_CNTL 0x00c2 |
| #define cfgBIF_CFG_DEV0_EPF2_0_MSIX_TABLE 0x00c4 |
| #define cfgBIF_CFG_DEV0_EPF2_0_MSIX_PBA 0x00c8 |
| #define cfgBIF_CFG_DEV0_EPF2_0_SATA_CAP_0 0x00d0 |
| #define cfgBIF_CFG_DEV0_EPF2_0_SATA_CAP_1 0x00d4 |
| #define cfgBIF_CFG_DEV0_EPF2_0_SATA_IDP_INDEX 0x00d8 |
| #define cfgBIF_CFG_DEV0_EPF2_0_SATA_IDP_DATA 0x00dc |
| #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x0100 |
| #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_VENDOR_SPECIFIC_HDR 0x0104 |
| #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_VENDOR_SPECIFIC1 0x0108 |
| #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_VENDOR_SPECIFIC2 0x010c |
| #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x0150 |
| #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_STATUS 0x0154 |
| #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_MASK 0x0158 |
| #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_UNCORR_ERR_SEVERITY 0x015c |
| #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_CORR_ERR_STATUS 0x0160 |
| #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_CORR_ERR_MASK 0x0164 |
| #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_ADV_ERR_CAP_CNTL 0x0168 |
| #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_HDR_LOG0 0x016c |
| #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_HDR_LOG1 0x0170 |
| #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_HDR_LOG2 0x0174 |
| #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_HDR_LOG3 0x0178 |
| #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TLP_PREFIX_LOG0 0x0188 |
| #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TLP_PREFIX_LOG1 0x018c |
| #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TLP_PREFIX_LOG2 0x0190 |
| #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_TLP_PREFIX_LOG3 0x0194 |
| #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_BAR_ENH_CAP_LIST 0x0200 |
| #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_BAR1_CAP 0x0204 |
| #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_BAR1_CNTL 0x0208 |
| #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_BAR2_CAP 0x020c |
| #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_BAR2_CNTL 0x0210 |
| #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_BAR3_CAP 0x0214 |
| #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_BAR3_CNTL 0x0218 |
| #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_BAR4_CAP 0x021c |
| #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_BAR4_CNTL 0x0220 |
| #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_BAR5_CAP 0x0224 |
| #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_BAR5_CNTL 0x0228 |
| #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_BAR6_CAP 0x022c |
| #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_BAR6_CNTL 0x0230 |
| #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_PWR_BUDGET_ENH_CAP_LIST 0x0240 |
| #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_PWR_BUDGET_DATA_SELECT 0x0244 |
| #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_PWR_BUDGET_DATA 0x0248 |
| #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_PWR_BUDGET_CAP 0x024c |
| #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_DPA_ENH_CAP_LIST 0x0250 |
| #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_DPA_CAP 0x0254 |
| #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_DPA_LATENCY_INDICATOR 0x0258 |
| #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_DPA_STATUS 0x025c |
| #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_DPA_CNTL 0x025e |
| #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0 0x0260 |
| #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1 0x0261 |
| #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2 0x0262 |
| #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3 0x0263 |
| #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4 0x0264 |
| #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5 0x0265 |
| #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6 0x0266 |
| #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7 0x0267 |
| #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_ACS_ENH_CAP_LIST 0x02a0 |
| #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_ACS_CAP 0x02a4 |
| #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_ACS_CNTL 0x02a6 |
| #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_ARI_ENH_CAP_LIST 0x0328 |
| #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_ARI_CAP 0x032c |
| #define cfgBIF_CFG_DEV0_EPF2_0_PCIE_ARI_CNTL 0x032e |
| |
| |
| // addressBlock: nbio_nbif0_bif_cfg_dev0_epf3_bifcfgdecp |
| // base address: 0x0 |
| #define cfgBIF_CFG_DEV0_EPF3_0_VENDOR_ID 0x0000 |
| #define cfgBIF_CFG_DEV0_EPF3_0_DEVICE_ID 0x0002 |
| #define cfgBIF_CFG_DEV0_EPF3_0_COMMAND 0x0004 |
| #define cfgBIF_CFG_DEV0_EPF3_0_STATUS 0x0006 |
| #define cfgBIF_CFG_DEV0_EPF3_0_REVISION_ID 0x0008 |
| #define cfgBIF_CFG_DEV0_EPF3_0_PROG_INTERFACE 0x0009 |
| #define cfgBIF_CFG_DEV0_EPF3_0_SUB_CLASS 0x000a |
| #define cfgBIF_CFG_DEV0_EPF3_0_BASE_CLASS 0x000b |
| #define cfgBIF_CFG_DEV0_EPF3_0_CACHE_LINE 0x000c |
| #define cfgBIF_CFG_DEV0_EPF3_0_LATENCY 0x000d |
| #define cfgBIF_CFG_DEV0_EPF3_0_HEADER 0x000e |
| #define cfgBIF_CFG_DEV0_EPF3_0_BIST 0x000f |
| #define cfgBIF_CFG_DEV0_EPF3_0_BASE_ADDR_1 0x0010 |
| #define cfgBIF_CFG_DEV0_EPF3_0_BASE_ADDR_2 0x0014 |
| #define cfgBIF_CFG_DEV0_EPF3_0_BASE_ADDR_3 0x0018 |
| #define cfgBIF_CFG_DEV0_EPF3_0_BASE_ADDR_4 0x001c |
| #define cfgBIF_CFG_DEV0_EPF3_0_BASE_ADDR_5 0x0020 |
| #define cfgBIF_CFG_DEV0_EPF3_0_BASE_ADDR_6 0x0024 |
| #define cfgBIF_CFG_DEV0_EPF3_0_ADAPTER_ID 0x002c |
| #define cfgBIF_CFG_DEV0_EPF3_0_ROM_BASE_ADDR 0x0030 |
| #define cfgBIF_CFG_DEV0_EPF3_0_CAP_PTR 0x0034 |
| #define cfgBIF_CFG_DEV0_EPF3_0_INTERRUPT_LINE 0x003c |
| #define cfgBIF_CFG_DEV0_EPF3_0_INTERRUPT_PIN 0x003d |
| #define cfgBIF_CFG_DEV0_EPF3_0_MIN_GRANT 0x003e |
| #define cfgBIF_CFG_DEV0_EPF3_0_MAX_LATENCY 0x003f |
| #define cfgBIF_CFG_DEV0_EPF3_0_VENDOR_CAP_LIST 0x0048 |
| #define cfgBIF_CFG_DEV0_EPF3_0_ADAPTER_ID_W 0x004c |
| #define cfgBIF_CFG_DEV0_EPF3_0_PMI_CAP_LIST 0x0050 |
| #define cfgBIF_CFG_DEV0_EPF3_0_PMI_CAP 0x0052 |
| #define cfgBIF_CFG_DEV0_EPF3_0_PMI_STATUS_CNTL 0x0054 |
| #define cfgBIF_CFG_DEV0_EPF3_0_SBRN 0x0060 |
| #define cfgBIF_CFG_DEV0_EPF3_0_FLADJ 0x0061 |
| #define cfgBIF_CFG_DEV0_EPF3_0_DBESL_DBESLD 0x0062 |
| #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_CAP_LIST 0x0064 |
| #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_CAP 0x0066 |
| #define cfgBIF_CFG_DEV0_EPF3_0_DEVICE_CAP 0x0068 |
| #define cfgBIF_CFG_DEV0_EPF3_0_DEVICE_CNTL 0x006c |
| #define cfgBIF_CFG_DEV0_EPF3_0_DEVICE_STATUS 0x006e |
| #define cfgBIF_CFG_DEV0_EPF3_0_LINK_CAP 0x0070 |
| #define cfgBIF_CFG_DEV0_EPF3_0_LINK_CNTL 0x0074 |
| #define cfgBIF_CFG_DEV0_EPF3_0_LINK_STATUS 0x0076 |
| #define cfgBIF_CFG_DEV0_EPF3_0_DEVICE_CAP2 0x0088 |
| #define cfgBIF_CFG_DEV0_EPF3_0_DEVICE_CNTL2 0x008c |
| #define cfgBIF_CFG_DEV0_EPF3_0_DEVICE_STATUS2 0x008e |
| #define cfgBIF_CFG_DEV0_EPF3_0_LINK_CAP2 0x0090 |
| #define cfgBIF_CFG_DEV0_EPF3_0_LINK_CNTL2 0x0094 |
| #define cfgBIF_CFG_DEV0_EPF3_0_LINK_STATUS2 0x0096 |
| #define cfgBIF_CFG_DEV0_EPF3_0_SLOT_CAP2 0x0098 |
| #define cfgBIF_CFG_DEV0_EPF3_0_SLOT_CNTL2 0x009c |
| #define cfgBIF_CFG_DEV0_EPF3_0_SLOT_STATUS2 0x009e |
| #define cfgBIF_CFG_DEV0_EPF3_0_MSI_CAP_LIST 0x00a0 |
| #define cfgBIF_CFG_DEV0_EPF3_0_MSI_MSG_CNTL 0x00a2 |
| #define cfgBIF_CFG_DEV0_EPF3_0_MSI_MSG_ADDR_LO 0x00a4 |
| #define cfgBIF_CFG_DEV0_EPF3_0_MSI_MSG_ADDR_HI 0x00a8 |
| #define cfgBIF_CFG_DEV0_EPF3_0_MSI_MSG_DATA 0x00a8 |
| #define cfgBIF_CFG_DEV0_EPF3_0_MSI_MASK 0x00ac |
| #define cfgBIF_CFG_DEV0_EPF3_0_MSI_MSG_DATA_64 0x00ac |
| #define cfgBIF_CFG_DEV0_EPF3_0_MSI_MASK_64 0x00b0 |
| #define cfgBIF_CFG_DEV0_EPF3_0_MSI_PENDING 0x00b0 |
| #define cfgBIF_CFG_DEV0_EPF3_0_MSI_PENDING_64 0x00b4 |
| #define cfgBIF_CFG_DEV0_EPF3_0_MSIX_CAP_LIST 0x00c0 |
| #define cfgBIF_CFG_DEV0_EPF3_0_MSIX_MSG_CNTL 0x00c2 |
| #define cfgBIF_CFG_DEV0_EPF3_0_MSIX_TABLE 0x00c4 |
| #define cfgBIF_CFG_DEV0_EPF3_0_MSIX_PBA 0x00c8 |
| #define cfgBIF_CFG_DEV0_EPF3_0_SATA_CAP_0 0x00d0 |
| #define cfgBIF_CFG_DEV0_EPF3_0_SATA_CAP_1 0x00d4 |
| #define cfgBIF_CFG_DEV0_EPF3_0_SATA_IDP_INDEX 0x00d8 |
| #define cfgBIF_CFG_DEV0_EPF3_0_SATA_IDP_DATA 0x00dc |
| #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x0100 |
| #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_VENDOR_SPECIFIC_HDR 0x0104 |
| #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_VENDOR_SPECIFIC1 0x0108 |
| #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_VENDOR_SPECIFIC2 0x010c |
| #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x0150 |
| #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_STATUS 0x0154 |
| #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_MASK 0x0158 |
| #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_UNCORR_ERR_SEVERITY 0x015c |
| #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_CORR_ERR_STATUS 0x0160 |
| #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_CORR_ERR_MASK 0x0164 |
| #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_ADV_ERR_CAP_CNTL 0x0168 |
| #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_HDR_LOG0 0x016c |
| #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_HDR_LOG1 0x0170 |
| #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_HDR_LOG2 0x0174 |
| #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_HDR_LOG3 0x0178 |
| #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TLP_PREFIX_LOG0 0x0188 |
| #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TLP_PREFIX_LOG1 0x018c |
| #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TLP_PREFIX_LOG2 0x0190 |
| #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_TLP_PREFIX_LOG3 0x0194 |
| #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_BAR_ENH_CAP_LIST 0x0200 |
| #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_BAR1_CAP 0x0204 |
| #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_BAR1_CNTL 0x0208 |
| #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_BAR2_CAP 0x020c |
| #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_BAR2_CNTL 0x0210 |
| #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_BAR3_CAP 0x0214 |
| #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_BAR3_CNTL 0x0218 |
| #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_BAR4_CAP 0x021c |
| #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_BAR4_CNTL 0x0220 |
| #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_BAR5_CAP 0x0224 |
| #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_BAR5_CNTL 0x0228 |
| #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_BAR6_CAP 0x022c |
| #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_BAR6_CNTL 0x0230 |
| #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_PWR_BUDGET_ENH_CAP_LIST 0x0240 |
| #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_PWR_BUDGET_DATA_SELECT 0x0244 |
| #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_PWR_BUDGET_DATA 0x0248 |
| #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_PWR_BUDGET_CAP 0x024c |
| #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_DPA_ENH_CAP_LIST 0x0250 |
| #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_DPA_CAP 0x0254 |
| #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_DPA_LATENCY_INDICATOR 0x0258 |
| #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_DPA_STATUS 0x025c |
| #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_DPA_CNTL 0x025e |
| #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0 0x0260 |
| #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1 0x0261 |
| #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2 0x0262 |
| #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3 0x0263 |
| #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4 0x0264 |
| #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5 0x0265 |
| #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6 0x0266 |
| #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7 0x0267 |
| #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_ACS_ENH_CAP_LIST 0x02a0 |
| #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_ACS_CAP 0x02a4 |
| #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_ACS_CNTL 0x02a6 |
| #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_ARI_ENH_CAP_LIST 0x0328 |
| #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_ARI_CAP 0x032c |
| #define cfgBIF_CFG_DEV0_EPF3_0_PCIE_ARI_CNTL 0x032e |
| |
| |
| // addressBlock: nbio_nbif0_bif_cfg_dev0_epf4_bifcfgdecp |
| // base address: 0x0 |
| #define cfgBIF_CFG_DEV0_EPF4_0_VENDOR_ID 0x0000 |
| #define cfgBIF_CFG_DEV0_EPF4_0_DEVICE_ID 0x0002 |
| #define cfgBIF_CFG_DEV0_EPF4_0_COMMAND 0x0004 |
| #define cfgBIF_CFG_DEV0_EPF4_0_STATUS 0x0006 |
| #define cfgBIF_CFG_DEV0_EPF4_0_REVISION_ID 0x0008 |
| #define cfgBIF_CFG_DEV0_EPF4_0_PROG_INTERFACE 0x0009 |
| #define cfgBIF_CFG_DEV0_EPF4_0_SUB_CLASS 0x000a |
| #define cfgBIF_CFG_DEV0_EPF4_0_BASE_CLASS 0x000b |
| #define cfgBIF_CFG_DEV0_EPF4_0_CACHE_LINE 0x000c |
| #define cfgBIF_CFG_DEV0_EPF4_0_LATENCY 0x000d |
| #define cfgBIF_CFG_DEV0_EPF4_0_HEADER 0x000e |
| #define cfgBIF_CFG_DEV0_EPF4_0_BIST 0x000f |
| #define cfgBIF_CFG_DEV0_EPF4_0_BASE_ADDR_1 0x0010 |
| #define cfgBIF_CFG_DEV0_EPF4_0_BASE_ADDR_2 0x0014 |
| #define cfgBIF_CFG_DEV0_EPF4_0_BASE_ADDR_3 0x0018 |
| #define cfgBIF_CFG_DEV0_EPF4_0_BASE_ADDR_4 0x001c |
| #define cfgBIF_CFG_DEV0_EPF4_0_BASE_ADDR_5 0x0020 |
| #define cfgBIF_CFG_DEV0_EPF4_0_BASE_ADDR_6 0x0024 |
| #define cfgBIF_CFG_DEV0_EPF4_0_ADAPTER_ID 0x002c |
| #define cfgBIF_CFG_DEV0_EPF4_0_ROM_BASE_ADDR 0x0030 |
| #define cfgBIF_CFG_DEV0_EPF4_0_CAP_PTR 0x0034 |
| #define cfgBIF_CFG_DEV0_EPF4_0_INTERRUPT_LINE 0x003c |
| #define cfgBIF_CFG_DEV0_EPF4_0_INTERRUPT_PIN 0x003d |
| #define cfgBIF_CFG_DEV0_EPF4_0_MIN_GRANT 0x003e |
| #define cfgBIF_CFG_DEV0_EPF4_0_MAX_LATENCY 0x003f |
| #define cfgBIF_CFG_DEV0_EPF4_0_VENDOR_CAP_LIST 0x0048 |
| #define cfgBIF_CFG_DEV0_EPF4_0_ADAPTER_ID_W 0x004c |
| #define cfgBIF_CFG_DEV0_EPF4_0_PMI_CAP_LIST 0x0050 |
| #define cfgBIF_CFG_DEV0_EPF4_0_PMI_CAP 0x0052 |
| #define cfgBIF_CFG_DEV0_EPF4_0_PMI_STATUS_CNTL 0x0054 |
| #define cfgBIF_CFG_DEV0_EPF4_0_SBRN 0x0060 |
| #define cfgBIF_CFG_DEV0_EPF4_0_FLADJ 0x0061 |
| #define cfgBIF_CFG_DEV0_EPF4_0_DBESL_DBESLD 0x0062 |
| #define cfgBIF_CFG_DEV0_EPF4_0_PCIE_CAP_LIST 0x0064 |
| #define cfgBIF_CFG_DEV0_EPF4_0_PCIE_CAP 0x0066 |
| #define cfgBIF_CFG_DEV0_EPF4_0_DEVICE_CAP 0x0068 |
| #define cfgBIF_CFG_DEV0_EPF4_0_DEVICE_CNTL 0x006c |
| #define cfgBIF_CFG_DEV0_EPF4_0_DEVICE_STATUS 0x006e |
| #define cfgBIF_CFG_DEV0_EPF4_0_LINK_CAP 0x0070 |
| #define cfgBIF_CFG_DEV0_EPF4_0_LINK_CNTL 0x0074 |
| #define cfgBIF_CFG_DEV0_EPF4_0_LINK_STATUS 0x0076 |
| #define cfgBIF_CFG_DEV0_EPF4_0_DEVICE_CAP2 0x0088 |
| #define cfgBIF_CFG_DEV0_EPF4_0_DEVICE_CNTL2 0x008c |
| #define cfgBIF_CFG_DEV0_EPF4_0_DEVICE_STATUS2 0x008e |
| #define cfgBIF_CFG_DEV0_EPF4_0_LINK_CAP2 0x0090 |
| #define cfgBIF_CFG_DEV0_EPF4_0_LINK_CNTL2 0x0094 |
| #define cfgBIF_CFG_DEV0_EPF4_0_LINK_STATUS2 0x0096 |
| #define cfgBIF_CFG_DEV0_EPF4_0_SLOT_CAP2 0x0098 |
| #define cfgBIF_CFG_DEV0_EPF4_0_SLOT_CNTL2 0x009c |
| #define cfgBIF_CFG_DEV0_EPF4_0_SLOT_STATUS2 0x009e |
| #define cfgBIF_CFG_DEV0_EPF4_0_MSI_CAP_LIST 0x00a0 |
| #define cfgBIF_CFG_DEV0_EPF4_0_MSI_MSG_CNTL 0x00a2 |
| #define cfgBIF_CFG_DEV0_EPF4_0_MSI_MSG_ADDR_LO 0x00a4 |
| #define cfgBIF_CFG_DEV0_EPF4_0_MSI_MSG_ADDR_HI 0x00a8 |
| #define cfgBIF_CFG_DEV0_EPF4_0_MSI_MSG_DATA 0x00a8 |
| #define cfgBIF_CFG_DEV0_EPF4_0_MSI_MASK 0x00ac |
| #define cfgBIF_CFG_DEV0_EPF4_0_MSI_MSG_DATA_64 0x00ac |
| #define cfgBIF_CFG_DEV0_EPF4_0_MSI_MASK_64 0x00b0 |
| #define cfgBIF_CFG_DEV0_EPF4_0_MSI_PENDING 0x00b0 |
| #define cfgBIF_CFG_DEV0_EPF4_0_MSI_PENDING_64 0x00b4 |
| #define cfgBIF_CFG_DEV0_EPF4_0_MSIX_CAP_LIST 0x00c0 |
| #define cfgBIF_CFG_DEV0_EPF4_0_MSIX_MSG_CNTL 0x00c2 |
| #define cfgBIF_CFG_DEV0_EPF4_0_MSIX_TABLE 0x00c4 |
| #define cfgBIF_CFG_DEV0_EPF4_0_MSIX_PBA 0x00c8 |
| #define cfgBIF_CFG_DEV0_EPF4_0_SATA_CAP_0 0x00d0 |
| #define cfgBIF_CFG_DEV0_EPF4_0_SATA_CAP_1 0x00d4 |
| #define cfgBIF_CFG_DEV0_EPF4_0_SATA_IDP_INDEX 0x00d8 |
| #define cfgBIF_CFG_DEV0_EPF4_0_SATA_IDP_DATA 0x00dc |
| #define cfgBIF_CFG_DEV0_EPF4_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x0100 |
| #define cfgBIF_CFG_DEV0_EPF4_0_PCIE_VENDOR_SPECIFIC_HDR 0x0104 |
| #define cfgBIF_CFG_DEV0_EPF4_0_PCIE_VENDOR_SPECIFIC1 0x0108 |
| #define cfgBIF_CFG_DEV0_EPF4_0_PCIE_VENDOR_SPECIFIC2 0x010c |
| #define cfgBIF_CFG_DEV0_EPF4_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x0150 |
| #define cfgBIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_STATUS 0x0154 |
| #define cfgBIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_MASK 0x0158 |
| #define cfgBIF_CFG_DEV0_EPF4_0_PCIE_UNCORR_ERR_SEVERITY 0x015c |
| #define cfgBIF_CFG_DEV0_EPF4_0_PCIE_CORR_ERR_STATUS 0x0160 |
| #define cfgBIF_CFG_DEV0_EPF4_0_PCIE_CORR_ERR_MASK 0x0164 |
| #define cfgBIF_CFG_DEV0_EPF4_0_PCIE_ADV_ERR_CAP_CNTL 0x0168 |
| #define cfgBIF_CFG_DEV0_EPF4_0_PCIE_HDR_LOG0 0x016c |
| #define cfgBIF_CFG_DEV0_EPF4_0_PCIE_HDR_LOG1 0x0170 |
| #define cfgBIF_CFG_DEV0_EPF4_0_PCIE_HDR_LOG2 0x0174 |
| #define cfgBIF_CFG_DEV0_EPF4_0_PCIE_HDR_LOG3 0x0178 |
| #define cfgBIF_CFG_DEV0_EPF4_0_PCIE_TLP_PREFIX_LOG0 0x0188 |
| #define cfgBIF_CFG_DEV0_EPF4_0_PCIE_TLP_PREFIX_LOG1 0x018c |
| #define cfgBIF_CFG_DEV0_EPF4_0_PCIE_TLP_PREFIX_LOG2 0x0190 |
| #define cfgBIF_CFG_DEV0_EPF4_0_PCIE_TLP_PREFIX_LOG3 0x0194 |
| #define cfgBIF_CFG_DEV0_EPF4_0_PCIE_BAR_ENH_CAP_LIST 0x0200 |
| #define cfgBIF_CFG_DEV0_EPF4_0_PCIE_BAR1_CAP 0x0204 |
| #define cfgBIF_CFG_DEV0_EPF4_0_PCIE_BAR1_CNTL 0x0208 |
| #define cfgBIF_CFG_DEV0_EPF4_0_PCIE_BAR2_CAP 0x020c |
| #define cfgBIF_CFG_DEV0_EPF4_0_PCIE_BAR2_CNTL 0x0210 |
| #define cfgBIF_CFG_DEV0_EPF4_0_PCIE_BAR3_CAP 0x0214 |
| #define cfgBIF_CFG_DEV0_EPF4_0_PCIE_BAR3_CNTL 0x0218 |
| #define cfgBIF_CFG_DEV0_EPF4_0_PCIE_BAR4_CAP 0x021c |
| #define cfgBIF_CFG_DEV0_EPF4_0_PCIE_BAR4_CNTL 0x0220 |
| #define cfgBIF_CFG_DEV0_EPF4_0_PCIE_BAR5_CAP 0x0224 |
| #define cfgBIF_CFG_DEV0_EPF4_0_PCIE_BAR5_CNTL 0x0228 |
| #define cfgBIF_CFG_DEV0_EPF4_0_PCIE_BAR6_CAP 0x022c |
| #define cfgBIF_CFG_DEV0_EPF4_0_PCIE_BAR6_CNTL 0x0230 |
| #define cfgBIF_CFG_DEV0_EPF4_0_PCIE_PWR_BUDGET_ENH_CAP_LIST 0x0240 |
| #define cfgBIF_CFG_DEV0_EPF4_0_PCIE_PWR_BUDGET_DATA_SELECT 0x0244 |
| #define cfgBIF_CFG_DEV0_EPF4_0_PCIE_PWR_BUDGET_DATA 0x0248 |
| #define cfgBIF_CFG_DEV0_EPF4_0_PCIE_PWR_BUDGET_CAP 0x024c |
| #define cfgBIF_CFG_DEV0_EPF4_0_PCIE_DPA_ENH_CAP_LIST 0x0250 |
| #define cfgBIF_CFG_DEV0_EPF4_0_PCIE_DPA_CAP 0x0254 |
| #define cfgBIF_CFG_DEV0_EPF4_0_PCIE_DPA_LATENCY_INDICATOR 0x0258 |
| #define cfgBIF_CFG_DEV0_EPF4_0_PCIE_DPA_STATUS 0x025c |
| #define cfgBIF_CFG_DEV0_EPF4_0_PCIE_DPA_CNTL 0x025e |
| #define cfgBIF_CFG_DEV0_EPF4_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0 0x0260 |
| #define cfgBIF_CFG_DEV0_EPF4_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1 0x0261 |
| #define cfgBIF_CFG_DEV0_EPF4_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2 0x0262 |
| #define cfgBIF_CFG_DEV0_EPF4_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3 0x0263 |
| #define cfgBIF_CFG_DEV0_EPF4_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4 0x0264 |
| #define cfgBIF_CFG_DEV0_EPF4_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5 0x0265 |
| #define cfgBIF_CFG_DEV0_EPF4_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6 0x0266 |
| #define cfgBIF_CFG_DEV0_EPF4_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7 0x0267 |
| #define cfgBIF_CFG_DEV0_EPF4_0_PCIE_ACS_ENH_CAP_LIST 0x02a0 |
| #define cfgBIF_CFG_DEV0_EPF4_0_PCIE_ACS_CAP 0x02a4 |
| #define cfgBIF_CFG_DEV0_EPF4_0_PCIE_ACS_CNTL 0x02a6 |
| #define cfgBIF_CFG_DEV0_EPF4_0_PCIE_ARI_ENH_CAP_LIST 0x0328 |
| #define cfgBIF_CFG_DEV0_EPF4_0_PCIE_ARI_CAP 0x032c |
| #define cfgBIF_CFG_DEV0_EPF4_0_PCIE_ARI_CNTL 0x032e |
| |
| |
| // addressBlock: nbio_nbif0_bif_cfg_dev0_epf5_bifcfgdecp |
| // base address: 0x0 |
| #define cfgBIF_CFG_DEV0_EPF5_0_VENDOR_ID 0x0000 |
| #define cfgBIF_CFG_DEV0_EPF5_0_DEVICE_ID 0x0002 |
| #define cfgBIF_CFG_DEV0_EPF5_0_COMMAND 0x0004 |
| #define cfgBIF_CFG_DEV0_EPF5_0_STATUS 0x0006 |
| #define cfgBIF_CFG_DEV0_EPF5_0_REVISION_ID 0x0008 |
| #define cfgBIF_CFG_DEV0_EPF5_0_PROG_INTERFACE 0x0009 |
| #define cfgBIF_CFG_DEV0_EPF5_0_SUB_CLASS 0x000a |
| #define cfgBIF_CFG_DEV0_EPF5_0_BASE_CLASS 0x000b |
| #define cfgBIF_CFG_DEV0_EPF5_0_CACHE_LINE 0x000c |
| #define cfgBIF_CFG_DEV0_EPF5_0_LATENCY 0x000d |
| #define cfgBIF_CFG_DEV0_EPF5_0_HEADER 0x000e |
| #define cfgBIF_CFG_DEV0_EPF5_0_BIST 0x000f |
| #define cfgBIF_CFG_DEV0_EPF5_0_BASE_ADDR_1 0x0010 |
| #define cfgBIF_CFG_DEV0_EPF5_0_BASE_ADDR_2 0x0014 |
| #define cfgBIF_CFG_DEV0_EPF5_0_BASE_ADDR_3 0x0018 |
| #define cfgBIF_CFG_DEV0_EPF5_0_BASE_ADDR_4 0x001c |
| #define cfgBIF_CFG_DEV0_EPF5_0_BASE_ADDR_5 0x0020 |
| #define cfgBIF_CFG_DEV0_EPF5_0_BASE_ADDR_6 0x0024 |
| #define cfgBIF_CFG_DEV0_EPF5_0_ADAPTER_ID 0x002c |
| #define cfgBIF_CFG_DEV0_EPF5_0_ROM_BASE_ADDR 0x0030 |
| #define cfgBIF_CFG_DEV0_EPF5_0_CAP_PTR 0x0034 |
| #define cfgBIF_CFG_DEV0_EPF5_0_INTERRUPT_LINE 0x003c |
| #define cfgBIF_CFG_DEV0_EPF5_0_INTERRUPT_PIN 0x003d |
| #define cfgBIF_CFG_DEV0_EPF5_0_MIN_GRANT 0x003e |
| #define cfgBIF_CFG_DEV0_EPF5_0_MAX_LATENCY 0x003f |
| #define cfgBIF_CFG_DEV0_EPF5_0_VENDOR_CAP_LIST 0x0048 |
| #define cfgBIF_CFG_DEV0_EPF5_0_ADAPTER_ID_W 0x004c |
| #define cfgBIF_CFG_DEV0_EPF5_0_PMI_CAP_LIST 0x0050 |
| #define cfgBIF_CFG_DEV0_EPF5_0_PMI_CAP 0x0052 |
| #define cfgBIF_CFG_DEV0_EPF5_0_PMI_STATUS_CNTL 0x0054 |
| #define cfgBIF_CFG_DEV0_EPF5_0_SBRN 0x0060 |
| #define cfgBIF_CFG_DEV0_EPF5_0_FLADJ 0x0061 |
| #define cfgBIF_CFG_DEV0_EPF5_0_DBESL_DBESLD 0x0062 |
| #define cfgBIF_CFG_DEV0_EPF5_0_PCIE_CAP_LIST 0x0064 |
| #define cfgBIF_CFG_DEV0_EPF5_0_PCIE_CAP 0x0066 |
| #define cfgBIF_CFG_DEV0_EPF5_0_DEVICE_CAP 0x0068 |
| #define cfgBIF_CFG_DEV0_EPF5_0_DEVICE_CNTL 0x006c |
| #define cfgBIF_CFG_DEV0_EPF5_0_DEVICE_STATUS 0x006e |
| #define cfgBIF_CFG_DEV0_EPF5_0_LINK_CAP 0x0070 |
| #define cfgBIF_CFG_DEV0_EPF5_0_LINK_CNTL 0x0074 |
| #define cfgBIF_CFG_DEV0_EPF5_0_LINK_STATUS 0x0076 |
| #define cfgBIF_CFG_DEV0_EPF5_0_DEVICE_CAP2 0x0088 |
| #define cfgBIF_CFG_DEV0_EPF5_0_DEVICE_CNTL2 0x008c |
| #define cfgBIF_CFG_DEV0_EPF5_0_DEVICE_STATUS2 0x008e |
| #define cfgBIF_CFG_DEV0_EPF5_0_LINK_CAP2 0x0090 |
| #define cfgBIF_CFG_DEV0_EPF5_0_LINK_CNTL2 0x0094 |
| #define cfgBIF_CFG_DEV0_EPF5_0_LINK_STATUS2 0x0096 |
| #define cfgBIF_CFG_DEV0_EPF5_0_SLOT_CAP2 0x0098 |
| #define cfgBIF_CFG_DEV0_EPF5_0_SLOT_CNTL2 0x009c |
| #define cfgBIF_CFG_DEV0_EPF5_0_SLOT_STATUS2 0x009e |
| #define cfgBIF_CFG_DEV0_EPF5_0_MSI_CAP_LIST 0x00a0 |
| #define cfgBIF_CFG_DEV0_EPF5_0_MSI_MSG_CNTL 0x00a2 |
| #define cfgBIF_CFG_DEV0_EPF5_0_MSI_MSG_ADDR_LO 0x00a4 |
| #define cfgBIF_CFG_DEV0_EPF5_0_MSI_MSG_ADDR_HI 0x00a8 |
| #define cfgBIF_CFG_DEV0_EPF5_0_MSI_MSG_DATA 0x00a8 |
| #define cfgBIF_CFG_DEV0_EPF5_0_MSI_MASK 0x00ac |
| #define cfgBIF_CFG_DEV0_EPF5_0_MSI_MSG_DATA_64 0x00ac |
| #define cfgBIF_CFG_DEV0_EPF5_0_MSI_MASK_64 0x00b0 |
| #define cfgBIF_CFG_DEV0_EPF5_0_MSI_PENDING 0x00b0 |
| #define cfgBIF_CFG_DEV0_EPF5_0_MSI_PENDING_64 0x00b4 |
| #define cfgBIF_CFG_DEV0_EPF5_0_MSIX_CAP_LIST 0x00c0 |
| #define cfgBIF_CFG_DEV0_EPF5_0_MSIX_MSG_CNTL 0x00c2 |
| #define cfgBIF_CFG_DEV0_EPF5_0_MSIX_TABLE 0x00c4 |
| #define cfgBIF_CFG_DEV0_EPF5_0_MSIX_PBA 0x00c8 |
| #define cfgBIF_CFG_DEV0_EPF5_0_SATA_CAP_0 0x00d0 |
| #define cfgBIF_CFG_DEV0_EPF5_0_SATA_CAP_1 0x00d4 |
| #define cfgBIF_CFG_DEV0_EPF5_0_SATA_IDP_INDEX 0x00d8 |
| #define cfgBIF_CFG_DEV0_EPF5_0_SATA_IDP_DATA 0x00dc |
| #define cfgBIF_CFG_DEV0_EPF5_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x0100 |
| #define cfgBIF_CFG_DEV0_EPF5_0_PCIE_VENDOR_SPECIFIC_HDR 0x0104 |
| #define cfgBIF_CFG_DEV0_EPF5_0_PCIE_VENDOR_SPECIFIC1 0x0108 |
| #define cfgBIF_CFG_DEV0_EPF5_0_PCIE_VENDOR_SPECIFIC2 0x010c |
| #define cfgBIF_CFG_DEV0_EPF5_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x0150 |
| #define cfgBIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_STATUS 0x0154 |
| #define cfgBIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_MASK 0x0158 |
| #define cfgBIF_CFG_DEV0_EPF5_0_PCIE_UNCORR_ERR_SEVERITY 0x015c |
| #define cfgBIF_CFG_DEV0_EPF5_0_PCIE_CORR_ERR_STATUS 0x0160 |
| #define cfgBIF_CFG_DEV0_EPF5_0_PCIE_CORR_ERR_MASK 0x0164 |
| #define cfgBIF_CFG_DEV0_EPF5_0_PCIE_ADV_ERR_CAP_CNTL 0x0168 |
| #define cfgBIF_CFG_DEV0_EPF5_0_PCIE_HDR_LOG0 0x016c |
| #define cfgBIF_CFG_DEV0_EPF5_0_PCIE_HDR_LOG1 0x0170 |
| #define cfgBIF_CFG_DEV0_EPF5_0_PCIE_HDR_LOG2 0x0174 |
| #define cfgBIF_CFG_DEV0_EPF5_0_PCIE_HDR_LOG3 0x0178 |
| #define cfgBIF_CFG_DEV0_EPF5_0_PCIE_TLP_PREFIX_LOG0 0x0188 |
| #define cfgBIF_CFG_DEV0_EPF5_0_PCIE_TLP_PREFIX_LOG1 0x018c |
| #define cfgBIF_CFG_DEV0_EPF5_0_PCIE_TLP_PREFIX_LOG2 0x0190 |
| #define cfgBIF_CFG_DEV0_EPF5_0_PCIE_TLP_PREFIX_LOG3 0x0194 |
| #define cfgBIF_CFG_DEV0_EPF5_0_PCIE_BAR_ENH_CAP_LIST 0x0200 |
| #define cfgBIF_CFG_DEV0_EPF5_0_PCIE_BAR1_CAP 0x0204 |
| #define cfgBIF_CFG_DEV0_EPF5_0_PCIE_BAR1_CNTL 0x0208 |
| #define cfgBIF_CFG_DEV0_EPF5_0_PCIE_BAR2_CAP 0x020c |
| #define cfgBIF_CFG_DEV0_EPF5_0_PCIE_BAR2_CNTL 0x0210 |
| #define cfgBIF_CFG_DEV0_EPF5_0_PCIE_BAR3_CAP 0x0214 |
| #define cfgBIF_CFG_DEV0_EPF5_0_PCIE_BAR3_CNTL 0x0218 |
| #define cfgBIF_CFG_DEV0_EPF5_0_PCIE_BAR4_CAP 0x021c |
| #define cfgBIF_CFG_DEV0_EPF5_0_PCIE_BAR4_CNTL 0x0220 |
| #define cfgBIF_CFG_DEV0_EPF5_0_PCIE_BAR5_CAP 0x0224 |
| #define cfgBIF_CFG_DEV0_EPF5_0_PCIE_BAR5_CNTL 0x0228 |
| #define cfgBIF_CFG_DEV0_EPF5_0_PCIE_BAR6_CAP 0x022c |
| #define cfgBIF_CFG_DEV0_EPF5_0_PCIE_BAR6_CNTL 0x0230 |
| #define cfgBIF_CFG_DEV0_EPF5_0_PCIE_PWR_BUDGET_ENH_CAP_LIST 0x0240 |
| #define cfgBIF_CFG_DEV0_EPF5_0_PCIE_PWR_BUDGET_DATA_SELECT 0x0244 |
| #define cfgBIF_CFG_DEV0_EPF5_0_PCIE_PWR_BUDGET_DATA 0x0248 |
| #define cfgBIF_CFG_DEV0_EPF5_0_PCIE_PWR_BUDGET_CAP 0x024c |
| #define cfgBIF_CFG_DEV0_EPF5_0_PCIE_DPA_ENH_CAP_LIST 0x0250 |
| #define cfgBIF_CFG_DEV0_EPF5_0_PCIE_DPA_CAP 0x0254 |
| #define cfgBIF_CFG_DEV0_EPF5_0_PCIE_DPA_LATENCY_INDICATOR 0x0258 |
| #define cfgBIF_CFG_DEV0_EPF5_0_PCIE_DPA_STATUS 0x025c |
| #define cfgBIF_CFG_DEV0_EPF5_0_PCIE_DPA_CNTL 0x025e |
| #define cfgBIF_CFG_DEV0_EPF5_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0 0x0260 |
| #define cfgBIF_CFG_DEV0_EPF5_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1 0x0261 |
| #define cfgBIF_CFG_DEV0_EPF5_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2 0x0262 |
| #define cfgBIF_CFG_DEV0_EPF5_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3 0x0263 |
| #define cfgBIF_CFG_DEV0_EPF5_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4 0x0264 |
| #define cfgBIF_CFG_DEV0_EPF5_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5 0x0265 |
| #define cfgBIF_CFG_DEV0_EPF5_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6 0x0266 |
| #define cfgBIF_CFG_DEV0_EPF5_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7 0x0267 |
| #define cfgBIF_CFG_DEV0_EPF5_0_PCIE_ACS_ENH_CAP_LIST 0x02a0 |
| #define cfgBIF_CFG_DEV0_EPF5_0_PCIE_ACS_CAP 0x02a4 |
| #define cfgBIF_CFG_DEV0_EPF5_0_PCIE_ACS_CNTL 0x02a6 |
| #define cfgBIF_CFG_DEV0_EPF5_0_PCIE_ARI_ENH_CAP_LIST 0x0328 |
| #define cfgBIF_CFG_DEV0_EPF5_0_PCIE_ARI_CAP 0x032c |
| #define cfgBIF_CFG_DEV0_EPF5_0_PCIE_ARI_CNTL 0x032e |
| |
| |
| // addressBlock: nbio_nbif0_bif_cfg_dev0_epf6_bifcfgdecp |
| // base address: 0x0 |
| #define cfgBIF_CFG_DEV0_EPF6_0_VENDOR_ID 0x0000 |
| #define cfgBIF_CFG_DEV0_EPF6_0_DEVICE_ID 0x0002 |
| #define cfgBIF_CFG_DEV0_EPF6_0_COMMAND 0x0004 |
| #define cfgBIF_CFG_DEV0_EPF6_0_STATUS 0x0006 |
| #define cfgBIF_CFG_DEV0_EPF6_0_REVISION_ID 0x0008 |
| #define cfgBIF_CFG_DEV0_EPF6_0_PROG_INTERFACE 0x0009 |
| #define cfgBIF_CFG_DEV0_EPF6_0_SUB_CLASS 0x000a |
| #define cfgBIF_CFG_DEV0_EPF6_0_BASE_CLASS 0x000b |
| #define cfgBIF_CFG_DEV0_EPF6_0_CACHE_LINE 0x000c |
| #define cfgBIF_CFG_DEV0_EPF6_0_LATENCY 0x000d |
| #define cfgBIF_CFG_DEV0_EPF6_0_HEADER 0x000e |
| #define cfgBIF_CFG_DEV0_EPF6_0_BIST 0x000f |
| #define cfgBIF_CFG_DEV0_EPF6_0_BASE_ADDR_1 0x0010 |
| #define cfgBIF_CFG_DEV0_EPF6_0_BASE_ADDR_2 0x0014 |
| #define cfgBIF_CFG_DEV0_EPF6_0_BASE_ADDR_3 0x0018 |
| #define cfgBIF_CFG_DEV0_EPF6_0_BASE_ADDR_4 0x001c |
| #define cfgBIF_CFG_DEV0_EPF6_0_BASE_ADDR_5 0x0020 |
| #define cfgBIF_CFG_DEV0_EPF6_0_BASE_ADDR_6 0x0024 |
| #define cfgBIF_CFG_DEV0_EPF6_0_ADAPTER_ID 0x002c |
| #define cfgBIF_CFG_DEV0_EPF6_0_ROM_BASE_ADDR 0x0030 |
| #define cfgBIF_CFG_DEV0_EPF6_0_CAP_PTR 0x0034 |
| #define cfgBIF_CFG_DEV0_EPF6_0_INTERRUPT_LINE 0x003c |
| #define cfgBIF_CFG_DEV0_EPF6_0_INTERRUPT_PIN 0x003d |
| #define cfgBIF_CFG_DEV0_EPF6_0_MIN_GRANT 0x003e |
| #define cfgBIF_CFG_DEV0_EPF6_0_MAX_LATENCY 0x003f |
| #define cfgBIF_CFG_DEV0_EPF6_0_VENDOR_CAP_LIST 0x0048 |
| #define cfgBIF_CFG_DEV0_EPF6_0_ADAPTER_ID_W 0x004c |
| #define cfgBIF_CFG_DEV0_EPF6_0_PMI_CAP_LIST 0x0050 |
| #define cfgBIF_CFG_DEV0_EPF6_0_PMI_CAP 0x0052 |
| #define cfgBIF_CFG_DEV0_EPF6_0_PMI_STATUS_CNTL 0x0054 |
| #define cfgBIF_CFG_DEV0_EPF6_0_SBRN 0x0060 |
| #define cfgBIF_CFG_DEV0_EPF6_0_FLADJ 0x0061 |
| #define cfgBIF_CFG_DEV0_EPF6_0_DBESL_DBESLD 0x0062 |
| #define cfgBIF_CFG_DEV0_EPF6_0_PCIE_CAP_LIST 0x0064 |
| #define cfgBIF_CFG_DEV0_EPF6_0_PCIE_CAP 0x0066 |
| #define cfgBIF_CFG_DEV0_EPF6_0_DEVICE_CAP 0x0068 |
| #define cfgBIF_CFG_DEV0_EPF6_0_DEVICE_CNTL 0x006c |
| #define cfgBIF_CFG_DEV0_EPF6_0_DEVICE_STATUS 0x006e |
| #define cfgBIF_CFG_DEV0_EPF6_0_LINK_CAP 0x0070 |
| #define cfgBIF_CFG_DEV0_EPF6_0_LINK_CNTL 0x0074 |
| #define cfgBIF_CFG_DEV0_EPF6_0_LINK_STATUS 0x0076 |
| #define cfgBIF_CFG_DEV0_EPF6_0_DEVICE_CAP2 0x0088 |
| #define cfgBIF_CFG_DEV0_EPF6_0_DEVICE_CNTL2 0x008c |
| #define cfgBIF_CFG_DEV0_EPF6_0_DEVICE_STATUS2 0x008e |
| #define cfgBIF_CFG_DEV0_EPF6_0_LINK_CAP2 0x0090 |
| #define cfgBIF_CFG_DEV0_EPF6_0_LINK_CNTL2 0x0094 |
| #define cfgBIF_CFG_DEV0_EPF6_0_LINK_STATUS2 0x0096 |
| #define cfgBIF_CFG_DEV0_EPF6_0_SLOT_CAP2 0x0098 |
| #define cfgBIF_CFG_DEV0_EPF6_0_SLOT_CNTL2 0x009c |
| #define cfgBIF_CFG_DEV0_EPF6_0_SLOT_STATUS2 0x009e |
| #define cfgBIF_CFG_DEV0_EPF6_0_MSI_CAP_LIST 0x00a0 |
| #define cfgBIF_CFG_DEV0_EPF6_0_MSI_MSG_CNTL 0x00a2 |
| #define cfgBIF_CFG_DEV0_EPF6_0_MSI_MSG_ADDR_LO 0x00a4 |
| #define cfgBIF_CFG_DEV0_EPF6_0_MSI_MSG_ADDR_HI 0x00a8 |
| #define cfgBIF_CFG_DEV0_EPF6_0_MSI_MSG_DATA 0x00a8 |
| #define cfgBIF_CFG_DEV0_EPF6_0_MSI_MASK 0x00ac |
| #define cfgBIF_CFG_DEV0_EPF6_0_MSI_MSG_DATA_64 0x00ac |
| #define cfgBIF_CFG_DEV0_EPF6_0_MSI_MASK_64 0x00b0 |
| #define cfgBIF_CFG_DEV0_EPF6_0_MSI_PENDING 0x00b0 |
| #define cfgBIF_CFG_DEV0_EPF6_0_MSI_PENDING_64 0x00b4 |
| #define cfgBIF_CFG_DEV0_EPF6_0_MSIX_CAP_LIST 0x00c0 |
| #define cfgBIF_CFG_DEV0_EPF6_0_MSIX_MSG_CNTL 0x00c2 |
| #define cfgBIF_CFG_DEV0_EPF6_0_MSIX_TABLE 0x00c4 |
| #define cfgBIF_CFG_DEV0_EPF6_0_MSIX_PBA 0x00c8 |
| #define cfgBIF_CFG_DEV0_EPF6_0_SATA_CAP_0 0x00d0 |
| #define cfgBIF_CFG_DEV0_EPF6_0_SATA_CAP_1 0x00d4 |
| #define cfgBIF_CFG_DEV0_EPF6_0_SATA_IDP_INDEX 0x00d8 |
| #define cfgBIF_CFG_DEV0_EPF6_0_SATA_IDP_DATA 0x00dc |
| #define cfgBIF_CFG_DEV0_EPF6_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x0100 |
| #define cfgBIF_CFG_DEV0_EPF6_0_PCIE_VENDOR_SPECIFIC_HDR 0x0104 |
| #define cfgBIF_CFG_DEV0_EPF6_0_PCIE_VENDOR_SPECIFIC1 0x0108 |
| #define cfgBIF_CFG_DEV0_EPF6_0_PCIE_VENDOR_SPECIFIC2 0x010c |
| #define cfgBIF_CFG_DEV0_EPF6_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x0150 |
| #define cfgBIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_STATUS 0x0154 |
| #define cfgBIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_MASK 0x0158 |
| #define cfgBIF_CFG_DEV0_EPF6_0_PCIE_UNCORR_ERR_SEVERITY 0x015c |
| #define cfgBIF_CFG_DEV0_EPF6_0_PCIE_CORR_ERR_STATUS 0x0160 |
| #define cfgBIF_CFG_DEV0_EPF6_0_PCIE_CORR_ERR_MASK 0x0164 |
| #define cfgBIF_CFG_DEV0_EPF6_0_PCIE_ADV_ERR_CAP_CNTL 0x0168 |
| #define cfgBIF_CFG_DEV0_EPF6_0_PCIE_HDR_LOG0 0x016c |
| #define cfgBIF_CFG_DEV0_EPF6_0_PCIE_HDR_LOG1 0x0170 |
| #define cfgBIF_CFG_DEV0_EPF6_0_PCIE_HDR_LOG2 0x0174 |
| #define cfgBIF_CFG_DEV0_EPF6_0_PCIE_HDR_LOG3 0x0178 |
| #define cfgBIF_CFG_DEV0_EPF6_0_PCIE_TLP_PREFIX_LOG0 0x0188 |
| #define cfgBIF_CFG_DEV0_EPF6_0_PCIE_TLP_PREFIX_LOG1 0x018c |
| #define cfgBIF_CFG_DEV0_EPF6_0_PCIE_TLP_PREFIX_LOG2 0x0190 |
| #define cfgBIF_CFG_DEV0_EPF6_0_PCIE_TLP_PREFIX_LOG3 0x0194 |
| #define cfgBIF_CFG_DEV0_EPF6_0_PCIE_BAR_ENH_CAP_LIST 0x0200 |
| #define cfgBIF_CFG_DEV0_EPF6_0_PCIE_BAR1_CAP 0x0204 |
| #define cfgBIF_CFG_DEV0_EPF6_0_PCIE_BAR1_CNTL 0x0208 |
| #define cfgBIF_CFG_DEV0_EPF6_0_PCIE_BAR2_CAP 0x020c |
| #define cfgBIF_CFG_DEV0_EPF6_0_PCIE_BAR2_CNTL 0x0210 |
| #define cfgBIF_CFG_DEV0_EPF6_0_PCIE_BAR3_CAP 0x0214 |
| #define cfgBIF_CFG_DEV0_EPF6_0_PCIE_BAR3_CNTL 0x0218 |
| #define cfgBIF_CFG_DEV0_EPF6_0_PCIE_BAR4_CAP 0x021c |
| #define cfgBIF_CFG_DEV0_EPF6_0_PCIE_BAR4_CNTL 0x0220 |
| #define cfgBIF_CFG_DEV0_EPF6_0_PCIE_BAR5_CAP 0x0224 |
| #define cfgBIF_CFG_DEV0_EPF6_0_PCIE_BAR5_CNTL 0x0228 |
| #define cfgBIF_CFG_DEV0_EPF6_0_PCIE_BAR6_CAP 0x022c |
| #define cfgBIF_CFG_DEV0_EPF6_0_PCIE_BAR6_CNTL 0x0230 |
| #define cfgBIF_CFG_DEV0_EPF6_0_PCIE_PWR_BUDGET_ENH_CAP_LIST 0x0240 |
| #define cfgBIF_CFG_DEV0_EPF6_0_PCIE_PWR_BUDGET_DATA_SELECT 0x0244 |
| #define cfgBIF_CFG_DEV0_EPF6_0_PCIE_PWR_BUDGET_DATA 0x0248 |
| #define cfgBIF_CFG_DEV0_EPF6_0_PCIE_PWR_BUDGET_CAP 0x024c |
| #define cfgBIF_CFG_DEV0_EPF6_0_PCIE_DPA_ENH_CAP_LIST 0x0250 |
| #define cfgBIF_CFG_DEV0_EPF6_0_PCIE_DPA_CAP 0x0254 |
| #define cfgBIF_CFG_DEV0_EPF6_0_PCIE_DPA_LATENCY_INDICATOR 0x0258 |
| #define cfgBIF_CFG_DEV0_EPF6_0_PCIE_DPA_STATUS 0x025c |
| #define cfgBIF_CFG_DEV0_EPF6_0_PCIE_DPA_CNTL 0x025e |
| #define cfgBIF_CFG_DEV0_EPF6_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0 0x0260 |
| #define cfgBIF_CFG_DEV0_EPF6_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1 0x0261 |
| #define cfgBIF_CFG_DEV0_EPF6_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2 0x0262 |
| #define cfgBIF_CFG_DEV0_EPF6_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3 0x0263 |
| #define cfgBIF_CFG_DEV0_EPF6_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4 0x0264 |
| #define cfgBIF_CFG_DEV0_EPF6_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5 0x0265 |
| #define cfgBIF_CFG_DEV0_EPF6_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6 0x0266 |
| #define cfgBIF_CFG_DEV0_EPF6_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7 0x0267 |
| #define cfgBIF_CFG_DEV0_EPF6_0_PCIE_ACS_ENH_CAP_LIST 0x02a0 |
| #define cfgBIF_CFG_DEV0_EPF6_0_PCIE_ACS_CAP 0x02a4 |
| #define cfgBIF_CFG_DEV0_EPF6_0_PCIE_ACS_CNTL 0x02a6 |
| #define cfgBIF_CFG_DEV0_EPF6_0_PCIE_ARI_ENH_CAP_LIST 0x0328 |
| #define cfgBIF_CFG_DEV0_EPF6_0_PCIE_ARI_CAP 0x032c |
| #define cfgBIF_CFG_DEV0_EPF6_0_PCIE_ARI_CNTL 0x032e |
| |
| |
| // addressBlock: nbio_nbif0_bif_cfg_dev0_epf7_bifcfgdecp |
| // base address: 0x0 |
| #define cfgBIF_CFG_DEV0_EPF7_0_VENDOR_ID 0x0000 |
| #define cfgBIF_CFG_DEV0_EPF7_0_DEVICE_ID 0x0002 |
| #define cfgBIF_CFG_DEV0_EPF7_0_COMMAND 0x0004 |
| #define cfgBIF_CFG_DEV0_EPF7_0_STATUS 0x0006 |
| #define cfgBIF_CFG_DEV0_EPF7_0_REVISION_ID 0x0008 |
| #define cfgBIF_CFG_DEV0_EPF7_0_PROG_INTERFACE 0x0009 |
| #define cfgBIF_CFG_DEV0_EPF7_0_SUB_CLASS 0x000a |
| #define cfgBIF_CFG_DEV0_EPF7_0_BASE_CLASS 0x000b |
| #define cfgBIF_CFG_DEV0_EPF7_0_CACHE_LINE 0x000c |
| #define cfgBIF_CFG_DEV0_EPF7_0_LATENCY 0x000d |
| #define cfgBIF_CFG_DEV0_EPF7_0_HEADER 0x000e |
| #define cfgBIF_CFG_DEV0_EPF7_0_BIST 0x000f |
| #define cfgBIF_CFG_DEV0_EPF7_0_BASE_ADDR_1 0x0010 |
| #define cfgBIF_CFG_DEV0_EPF7_0_BASE_ADDR_2 0x0014 |
| #define cfgBIF_CFG_DEV0_EPF7_0_BASE_ADDR_3 0x0018 |
| #define cfgBIF_CFG_DEV0_EPF7_0_BASE_ADDR_4 0x001c |
| #define cfgBIF_CFG_DEV0_EPF7_0_BASE_ADDR_5 0x0020 |
| #define cfgBIF_CFG_DEV0_EPF7_0_BASE_ADDR_6 0x0024 |
| #define cfgBIF_CFG_DEV0_EPF7_0_ADAPTER_ID 0x002c |
| #define cfgBIF_CFG_DEV0_EPF7_0_ROM_BASE_ADDR 0x0030 |
| #define cfgBIF_CFG_DEV0_EPF7_0_CAP_PTR 0x0034 |
| #define cfgBIF_CFG_DEV0_EPF7_0_INTERRUPT_LINE 0x003c |
| #define cfgBIF_CFG_DEV0_EPF7_0_INTERRUPT_PIN 0x003d |
| #define cfgBIF_CFG_DEV0_EPF7_0_MIN_GRANT 0x003e |
| #define cfgBIF_CFG_DEV0_EPF7_0_MAX_LATENCY 0x003f |
| #define cfgBIF_CFG_DEV0_EPF7_0_VENDOR_CAP_LIST 0x0048 |
| #define cfgBIF_CFG_DEV0_EPF7_0_ADAPTER_ID_W 0x004c |
| #define cfgBIF_CFG_DEV0_EPF7_0_PMI_CAP_LIST 0x0050 |
| #define cfgBIF_CFG_DEV0_EPF7_0_PMI_CAP 0x0052 |
| #define cfgBIF_CFG_DEV0_EPF7_0_PMI_STATUS_CNTL 0x0054 |
| #define cfgBIF_CFG_DEV0_EPF7_0_SBRN 0x0060 |
| #define cfgBIF_CFG_DEV0_EPF7_0_FLADJ 0x0061 |
| #define cfgBIF_CFG_DEV0_EPF7_0_DBESL_DBESLD 0x0062 |
| #define cfgBIF_CFG_DEV0_EPF7_0_PCIE_CAP_LIST 0x0064 |
| #define cfgBIF_CFG_DEV0_EPF7_0_PCIE_CAP 0x0066 |
| #define cfgBIF_CFG_DEV0_EPF7_0_DEVICE_CAP 0x0068 |
| #define cfgBIF_CFG_DEV0_EPF7_0_DEVICE_CNTL 0x006c |
| #define cfgBIF_CFG_DEV0_EPF7_0_DEVICE_STATUS 0x006e |
| #define cfgBIF_CFG_DEV0_EPF7_0_LINK_CAP 0x0070 |
| #define cfgBIF_CFG_DEV0_EPF7_0_LINK_CNTL 0x0074 |
| #define cfgBIF_CFG_DEV0_EPF7_0_LINK_STATUS 0x0076 |
| #define cfgBIF_CFG_DEV0_EPF7_0_DEVICE_CAP2 0x0088 |
| #define cfgBIF_CFG_DEV0_EPF7_0_DEVICE_CNTL2 0x008c |
| #define cfgBIF_CFG_DEV0_EPF7_0_DEVICE_STATUS2 0x008e |
| #define cfgBIF_CFG_DEV0_EPF7_0_LINK_CAP2 0x0090 |
| #define cfgBIF_CFG_DEV0_EPF7_0_LINK_CNTL2 0x0094 |
| #define cfgBIF_CFG_DEV0_EPF7_0_LINK_STATUS2 0x0096 |
| #define cfgBIF_CFG_DEV0_EPF7_0_SLOT_CAP2 0x0098 |
| #define cfgBIF_CFG_DEV0_EPF7_0_SLOT_CNTL2 0x009c |
| #define cfgBIF_CFG_DEV0_EPF7_0_SLOT_STATUS2 0x009e |
| #define cfgBIF_CFG_DEV0_EPF7_0_MSI_CAP_LIST 0x00a0 |
| #define cfgBIF_CFG_DEV0_EPF7_0_MSI_MSG_CNTL 0x00a2 |
| #define cfgBIF_CFG_DEV0_EPF7_0_MSI_MSG_ADDR_LO 0x00a4 |
| #define cfgBIF_CFG_DEV0_EPF7_0_MSI_MSG_ADDR_HI 0x00a8 |
| #define cfgBIF_CFG_DEV0_EPF7_0_MSI_MSG_DATA 0x00a8 |
| #define cfgBIF_CFG_DEV0_EPF7_0_MSI_MASK 0x00ac |
| #define cfgBIF_CFG_DEV0_EPF7_0_MSI_MSG_DATA_64 0x00ac |
| #define cfgBIF_CFG_DEV0_EPF7_0_MSI_MASK_64 0x00b0 |
| #define cfgBIF_CFG_DEV0_EPF7_0_MSI_PENDING 0x00b0 |
| #define cfgBIF_CFG_DEV0_EPF7_0_MSI_PENDING_64 0x00b4 |
| #define cfgBIF_CFG_DEV0_EPF7_0_MSIX_CAP_LIST 0x00c0 |
| #define cfgBIF_CFG_DEV0_EPF7_0_MSIX_MSG_CNTL 0x00c2 |
| #define cfgBIF_CFG_DEV0_EPF7_0_MSIX_TABLE 0x00c4 |
| #define cfgBIF_CFG_DEV0_EPF7_0_MSIX_PBA 0x00c8 |
| #define cfgBIF_CFG_DEV0_EPF7_0_SATA_CAP_0 0x00d0 |
| #define cfgBIF_CFG_DEV0_EPF7_0_SATA_CAP_1 0x00d4 |
| #define cfgBIF_CFG_DEV0_EPF7_0_SATA_IDP_INDEX 0x00d8 |
| #define cfgBIF_CFG_DEV0_EPF7_0_SATA_IDP_DATA 0x00dc |
| #define cfgBIF_CFG_DEV0_EPF7_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x0100 |
| #define cfgBIF_CFG_DEV0_EPF7_0_PCIE_VENDOR_SPECIFIC_HDR 0x0104 |
| #define cfgBIF_CFG_DEV0_EPF7_0_PCIE_VENDOR_SPECIFIC1 0x0108 |
| #define cfgBIF_CFG_DEV0_EPF7_0_PCIE_VENDOR_SPECIFIC2 0x010c |
| #define cfgBIF_CFG_DEV0_EPF7_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x0150 |
| #define cfgBIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_STATUS 0x0154 |
| #define cfgBIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_MASK 0x0158 |
| #define cfgBIF_CFG_DEV0_EPF7_0_PCIE_UNCORR_ERR_SEVERITY 0x015c |
| #define cfgBIF_CFG_DEV0_EPF7_0_PCIE_CORR_ERR_STATUS 0x0160 |
| #define cfgBIF_CFG_DEV0_EPF7_0_PCIE_CORR_ERR_MASK 0x0164 |
| #define cfgBIF_CFG_DEV0_EPF7_0_PCIE_ADV_ERR_CAP_CNTL 0x0168 |
| #define cfgBIF_CFG_DEV0_EPF7_0_PCIE_HDR_LOG0 0x016c |
| #define cfgBIF_CFG_DEV0_EPF7_0_PCIE_HDR_LOG1 0x0170 |
| #define cfgBIF_CFG_DEV0_EPF7_0_PCIE_HDR_LOG2 0x0174 |
| #define cfgBIF_CFG_DEV0_EPF7_0_PCIE_HDR_LOG3 0x0178 |
| #define cfgBIF_CFG_DEV0_EPF7_0_PCIE_TLP_PREFIX_LOG0 0x0188 |
| #define cfgBIF_CFG_DEV0_EPF7_0_PCIE_TLP_PREFIX_LOG1 0x018c |
| #define cfgBIF_CFG_DEV0_EPF7_0_PCIE_TLP_PREFIX_LOG2 0x0190 |
| #define cfgBIF_CFG_DEV0_EPF7_0_PCIE_TLP_PREFIX_LOG3 0x0194 |
| #define cfgBIF_CFG_DEV0_EPF7_0_PCIE_BAR_ENH_CAP_LIST 0x0200 |
| #define cfgBIF_CFG_DEV0_EPF7_0_PCIE_BAR1_CAP 0x0204 |
| #define cfgBIF_CFG_DEV0_EPF7_0_PCIE_BAR1_CNTL 0x0208 |
| #define cfgBIF_CFG_DEV0_EPF7_0_PCIE_BAR2_CAP 0x020c |
| #define cfgBIF_CFG_DEV0_EPF7_0_PCIE_BAR2_CNTL 0x0210 |
| #define cfgBIF_CFG_DEV0_EPF7_0_PCIE_BAR3_CAP 0x0214 |
| #define cfgBIF_CFG_DEV0_EPF7_0_PCIE_BAR3_CNTL 0x0218 |
| #define cfgBIF_CFG_DEV0_EPF7_0_PCIE_BAR4_CAP 0x021c |
| #define cfgBIF_CFG_DEV0_EPF7_0_PCIE_BAR4_CNTL 0x0220 |
| #define cfgBIF_CFG_DEV0_EPF7_0_PCIE_BAR5_CAP 0x0224 |
| #define cfgBIF_CFG_DEV0_EPF7_0_PCIE_BAR5_CNTL 0x0228 |
| #define cfgBIF_CFG_DEV0_EPF7_0_PCIE_BAR6_CAP 0x022c |
| #define cfgBIF_CFG_DEV0_EPF7_0_PCIE_BAR6_CNTL 0x0230 |
| #define cfgBIF_CFG_DEV0_EPF7_0_PCIE_PWR_BUDGET_ENH_CAP_LIST 0x0240 |
| #define cfgBIF_CFG_DEV0_EPF7_0_PCIE_PWR_BUDGET_DATA_SELECT 0x0244 |
| #define cfgBIF_CFG_DEV0_EPF7_0_PCIE_PWR_BUDGET_DATA 0x0248 |
| #define cfgBIF_CFG_DEV0_EPF7_0_PCIE_PWR_BUDGET_CAP 0x024c |
| #define cfgBIF_CFG_DEV0_EPF7_0_PCIE_DPA_ENH_CAP_LIST 0x0250 |
| #define cfgBIF_CFG_DEV0_EPF7_0_PCIE_DPA_CAP 0x0254 |
| #define cfgBIF_CFG_DEV0_EPF7_0_PCIE_DPA_LATENCY_INDICATOR 0x0258 |
| #define cfgBIF_CFG_DEV0_EPF7_0_PCIE_DPA_STATUS 0x025c |
| #define cfgBIF_CFG_DEV0_EPF7_0_PCIE_DPA_CNTL 0x025e |
| #define cfgBIF_CFG_DEV0_EPF7_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0 0x0260 |
| #define cfgBIF_CFG_DEV0_EPF7_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1 0x0261 |
| #define cfgBIF_CFG_DEV0_EPF7_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2 0x0262 |
| #define cfgBIF_CFG_DEV0_EPF7_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3 0x0263 |
| #define cfgBIF_CFG_DEV0_EPF7_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4 0x0264 |
| #define cfgBIF_CFG_DEV0_EPF7_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5 0x0265 |
| #define cfgBIF_CFG_DEV0_EPF7_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6 0x0266 |
| #define cfgBIF_CFG_DEV0_EPF7_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7 0x0267 |
| #define cfgBIF_CFG_DEV0_EPF7_0_PCIE_ACS_ENH_CAP_LIST 0x02a0 |
| #define cfgBIF_CFG_DEV0_EPF7_0_PCIE_ACS_CAP 0x02a4 |
| #define cfgBIF_CFG_DEV0_EPF7_0_PCIE_ACS_CNTL 0x02a6 |
| #define cfgBIF_CFG_DEV0_EPF7_0_PCIE_ARI_ENH_CAP_LIST 0x0328 |
| #define cfgBIF_CFG_DEV0_EPF7_0_PCIE_ARI_CAP 0x032c |
| #define cfgBIF_CFG_DEV0_EPF7_0_PCIE_ARI_CNTL 0x032e |
| |
| |
| // addressBlock: nbio_nbif0_bif_cfg_dev1_epf0_bifcfgdecp |
| // base address: 0x0 |
| #define cfgBIF_CFG_DEV1_EPF0_0_VENDOR_ID 0x0000 |
| #define cfgBIF_CFG_DEV1_EPF0_0_DEVICE_ID 0x0002 |
| #define cfgBIF_CFG_DEV1_EPF0_0_COMMAND 0x0004 |
| #define cfgBIF_CFG_DEV1_EPF0_0_STATUS 0x0006 |
| #define cfgBIF_CFG_DEV1_EPF0_0_REVISION_ID 0x0008 |
| #define cfgBIF_CFG_DEV1_EPF0_0_PROG_INTERFACE 0x0009 |
| #define cfgBIF_CFG_DEV1_EPF0_0_SUB_CLASS 0x000a |
| #define cfgBIF_CFG_DEV1_EPF0_0_BASE_CLASS 0x000b |
| #define cfgBIF_CFG_DEV1_EPF0_0_CACHE_LINE 0x000c |
| #define cfgBIF_CFG_DEV1_EPF0_0_LATENCY 0x000d |
| #define cfgBIF_CFG_DEV1_EPF0_0_HEADER 0x000e |
| #define cfgBIF_CFG_DEV1_EPF0_0_BIST 0x000f |
| #define cfgBIF_CFG_DEV1_EPF0_0_BASE_ADDR_1 0x0010 |
| #define cfgBIF_CFG_DEV1_EPF0_0_BASE_ADDR_2 0x0014 |
| #define cfgBIF_CFG_DEV1_EPF0_0_BASE_ADDR_3 0x0018 |
| #define cfgBIF_CFG_DEV1_EPF0_0_BASE_ADDR_4 0x001c |
| #define cfgBIF_CFG_DEV1_EPF0_0_BASE_ADDR_5 0x0020 |
| #define cfgBIF_CFG_DEV1_EPF0_0_BASE_ADDR_6 0x0024 |
| #define cfgBIF_CFG_DEV1_EPF0_0_ADAPTER_ID 0x002c |
| #define cfgBIF_CFG_DEV1_EPF0_0_ROM_BASE_ADDR 0x0030 |
| #define cfgBIF_CFG_DEV1_EPF0_0_CAP_PTR 0x0034 |
| #define cfgBIF_CFG_DEV1_EPF0_0_INTERRUPT_LINE 0x003c |
| #define cfgBIF_CFG_DEV1_EPF0_0_INTERRUPT_PIN 0x003d |
| #define cfgBIF_CFG_DEV1_EPF0_0_MIN_GRANT 0x003e |
| #define cfgBIF_CFG_DEV1_EPF0_0_MAX_LATENCY 0x003f |
| #define cfgBIF_CFG_DEV1_EPF0_0_VENDOR_CAP_LIST 0x0048 |
| #define cfgBIF_CFG_DEV1_EPF0_0_ADAPTER_ID_W 0x004c |
| #define cfgBIF_CFG_DEV1_EPF0_0_PMI_CAP_LIST 0x0050 |
| #define cfgBIF_CFG_DEV1_EPF0_0_PMI_CAP 0x0052 |
| #define cfgBIF_CFG_DEV1_EPF0_0_PMI_STATUS_CNTL 0x0054 |
| #define cfgBIF_CFG_DEV1_EPF0_0_PCIE_CAP_LIST 0x0064 |
| #define cfgBIF_CFG_DEV1_EPF0_0_PCIE_CAP 0x0066 |
| #define cfgBIF_CFG_DEV1_EPF0_0_DEVICE_CAP 0x0068 |
| #define cfgBIF_CFG_DEV1_EPF0_0_DEVICE_CNTL 0x006c |
| #define cfgBIF_CFG_DEV1_EPF0_0_DEVICE_STATUS 0x006e |
| #define cfgBIF_CFG_DEV1_EPF0_0_LINK_CAP 0x0070 |
| #define cfgBIF_CFG_DEV1_EPF0_0_LINK_CNTL 0x0074 |
| #define cfgBIF_CFG_DEV1_EPF0_0_LINK_STATUS 0x0076 |
| #define cfgBIF_CFG_DEV1_EPF0_0_DEVICE_CAP2 0x0088 |
| #define cfgBIF_CFG_DEV1_EPF0_0_DEVICE_CNTL2 0x008c |
| #define cfgBIF_CFG_DEV1_EPF0_0_DEVICE_STATUS2 0x008e |
| #define cfgBIF_CFG_DEV1_EPF0_0_LINK_CAP2 0x0090 |
| #define cfgBIF_CFG_DEV1_EPF0_0_LINK_CNTL2 0x0094 |
| #define cfgBIF_CFG_DEV1_EPF0_0_LINK_STATUS2 0x0096 |
| #define cfgBIF_CFG_DEV1_EPF0_0_SLOT_CAP2 0x0098 |
| #define cfgBIF_CFG_DEV1_EPF0_0_SLOT_CNTL2 0x009c |
| #define cfgBIF_CFG_DEV1_EPF0_0_SLOT_STATUS2 0x009e |
| #define cfgBIF_CFG_DEV1_EPF0_0_MSI_CAP_LIST 0x00a0 |
| #define cfgBIF_CFG_DEV1_EPF0_0_MSI_MSG_CNTL 0x00a2 |
| #define cfgBIF_CFG_DEV1_EPF0_0_MSI_MSG_ADDR_LO 0x00a4 |
| #define cfgBIF_CFG_DEV1_EPF0_0_MSI_MSG_ADDR_HI 0x00a8 |
| #define cfgBIF_CFG_DEV1_EPF0_0_MSI_MSG_DATA 0x00a8 |
| #define cfgBIF_CFG_DEV1_EPF0_0_MSI_MASK 0x00ac |
| #define cfgBIF_CFG_DEV1_EPF0_0_MSI_MSG_DATA_64 0x00ac |
| #define cfgBIF_CFG_DEV1_EPF0_0_MSI_MASK_64 0x00b0 |
| #define cfgBIF_CFG_DEV1_EPF0_0_MSI_PENDING 0x00b0 |
| #define cfgBIF_CFG_DEV1_EPF0_0_MSI_PENDING_64 0x00b4 |
| #define cfgBIF_CFG_DEV1_EPF0_0_MSIX_CAP_LIST 0x00c0 |
| #define cfgBIF_CFG_DEV1_EPF0_0_MSIX_MSG_CNTL 0x00c2 |
| #define cfgBIF_CFG_DEV1_EPF0_0_MSIX_TABLE 0x00c4 |
| #define cfgBIF_CFG_DEV1_EPF0_0_MSIX_PBA 0x00c8 |
| #define cfgBIF_CFG_DEV1_EPF0_0_SATA_CAP_0 0x00d0 |
| #define cfgBIF_CFG_DEV1_EPF0_0_SATA_CAP_1 0x00d4 |
| #define cfgBIF_CFG_DEV1_EPF0_0_SATA_IDP_INDEX 0x00d8 |
| #define cfgBIF_CFG_DEV1_EPF0_0_SATA_IDP_DATA 0x00dc |
| #define cfgBIF_CFG_DEV1_EPF0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x0100 |
| #define cfgBIF_CFG_DEV1_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR 0x0104 |
| #define cfgBIF_CFG_DEV1_EPF0_0_PCIE_VENDOR_SPECIFIC1 0x0108 |
| #define cfgBIF_CFG_DEV1_EPF0_0_PCIE_VENDOR_SPECIFIC2 0x010c |
| #define cfgBIF_CFG_DEV1_EPF0_0_PCIE_VC_ENH_CAP_LIST 0x0110 |
| #define cfgBIF_CFG_DEV1_EPF0_0_PCIE_PORT_VC_CAP_REG1 0x0114 |
| #define cfgBIF_CFG_DEV1_EPF0_0_PCIE_PORT_VC_CAP_REG2 0x0118 |
| #define cfgBIF_CFG_DEV1_EPF0_0_PCIE_PORT_VC_CNTL 0x011c |
| #define cfgBIF_CFG_DEV1_EPF0_0_PCIE_PORT_VC_STATUS 0x011e |
| #define cfgBIF_CFG_DEV1_EPF0_0_PCIE_VC0_RESOURCE_CAP 0x0120 |
| #define cfgBIF_CFG_DEV1_EPF0_0_PCIE_VC0_RESOURCE_CNTL 0x0124 |
| #define cfgBIF_CFG_DEV1_EPF0_0_PCIE_VC0_RESOURCE_STATUS 0x012a |
| #define cfgBIF_CFG_DEV1_EPF0_0_PCIE_VC1_RESOURCE_CAP 0x012c |
| #define cfgBIF_CFG_DEV1_EPF0_0_PCIE_VC1_RESOURCE_CNTL 0x0130 |
| #define cfgBIF_CFG_DEV1_EPF0_0_PCIE_VC1_RESOURCE_STATUS 0x0136 |
| #define cfgBIF_CFG_DEV1_EPF0_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x0150 |
| #define cfgBIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_STATUS 0x0154 |
| #define cfgBIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_MASK 0x0158 |
| #define cfgBIF_CFG_DEV1_EPF0_0_PCIE_UNCORR_ERR_SEVERITY 0x015c |
| #define cfgBIF_CFG_DEV1_EPF0_0_PCIE_CORR_ERR_STATUS 0x0160 |
| #define cfgBIF_CFG_DEV1_EPF0_0_PCIE_CORR_ERR_MASK 0x0164 |
| #define cfgBIF_CFG_DEV1_EPF0_0_PCIE_ADV_ERR_CAP_CNTL 0x0168 |
| #define cfgBIF_CFG_DEV1_EPF0_0_PCIE_HDR_LOG0 0x016c |
| #define cfgBIF_CFG_DEV1_EPF0_0_PCIE_HDR_LOG1 0x0170 |
| #define cfgBIF_CFG_DEV1_EPF0_0_PCIE_HDR_LOG2 0x0174 |
| #define cfgBIF_CFG_DEV1_EPF0_0_PCIE_HDR_LOG3 0x0178 |
| #define cfgBIF_CFG_DEV1_EPF0_0_PCIE_TLP_PREFIX_LOG0 0x0188 |
| #define cfgBIF_CFG_DEV1_EPF0_0_PCIE_TLP_PREFIX_LOG1 0x018c |
| #define cfgBIF_CFG_DEV1_EPF0_0_PCIE_TLP_PREFIX_LOG2 0x0190 |
| #define cfgBIF_CFG_DEV1_EPF0_0_PCIE_TLP_PREFIX_LOG3 0x0194 |
| #define cfgBIF_CFG_DEV1_EPF0_0_PCIE_BAR_ENH_CAP_LIST 0x0200 |
| #define cfgBIF_CFG_DEV1_EPF0_0_PCIE_BAR1_CAP 0x0204 |
| #define cfgBIF_CFG_DEV1_EPF0_0_PCIE_BAR1_CNTL 0x0208 |
| #define cfgBIF_CFG_DEV1_EPF0_0_PCIE_BAR2_CAP 0x020c |
| #define cfgBIF_CFG_DEV1_EPF0_0_PCIE_BAR2_CNTL 0x0210 |
| #define cfgBIF_CFG_DEV1_EPF0_0_PCIE_BAR3_CAP 0x0214 |
| #define cfgBIF_CFG_DEV1_EPF0_0_PCIE_BAR3_CNTL 0x0218 |
| #define cfgBIF_CFG_DEV1_EPF0_0_PCIE_BAR4_CAP 0x021c |
| #define cfgBIF_CFG_DEV1_EPF0_0_PCIE_BAR4_CNTL 0x0220 |
| #define cfgBIF_CFG_DEV1_EPF0_0_PCIE_BAR5_CAP 0x0224 |
| #define cfgBIF_CFG_DEV1_EPF0_0_PCIE_BAR5_CNTL 0x0228 |
| #define cfgBIF_CFG_DEV1_EPF0_0_PCIE_BAR6_CAP 0x022c |
| #define cfgBIF_CFG_DEV1_EPF0_0_PCIE_BAR6_CNTL 0x0230 |
| #define cfgBIF_CFG_DEV1_EPF0_0_PCIE_PWR_BUDGET_ENH_CAP_LIST 0x0240 |
| #define cfgBIF_CFG_DEV1_EPF0_0_PCIE_PWR_BUDGET_DATA_SELECT 0x0244 |
| #define cfgBIF_CFG_DEV1_EPF0_0_PCIE_PWR_BUDGET_DATA 0x0248 |
| #define cfgBIF_CFG_DEV1_EPF0_0_PCIE_PWR_BUDGET_CAP 0x024c |
| #define cfgBIF_CFG_DEV1_EPF0_0_PCIE_DPA_ENH_CAP_LIST 0x0250 |
| #define cfgBIF_CFG_DEV1_EPF0_0_PCIE_DPA_CAP 0x0254 |
| #define cfgBIF_CFG_DEV1_EPF0_0_PCIE_DPA_LATENCY_INDICATOR 0x0258 |
| #define cfgBIF_CFG_DEV1_EPF0_0_PCIE_DPA_STATUS 0x025c |
| #define cfgBIF_CFG_DEV1_EPF0_0_PCIE_DPA_CNTL 0x025e |
| #define cfgBIF_CFG_DEV1_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0 0x0260 |
| #define cfgBIF_CFG_DEV1_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1 0x0261 |
| #define cfgBIF_CFG_DEV1_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2 0x0262 |
| #define cfgBIF_CFG_DEV1_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3 0x0263 |
| #define cfgBIF_CFG_DEV1_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4 0x0264 |
| #define cfgBIF_CFG_DEV1_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5 0x0265 |
| #define cfgBIF_CFG_DEV1_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6 0x0266 |
| #define cfgBIF_CFG_DEV1_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7 0x0267 |
| #define cfgBIF_CFG_DEV1_EPF0_0_PCIE_SECONDARY_ENH_CAP_LIST 0x0270 |
| #define cfgBIF_CFG_DEV1_EPF0_0_PCIE_LINK_CNTL3 0x0274 |
| #define cfgBIF_CFG_DEV1_EPF0_0_PCIE_LANE_ERROR_STATUS 0x0278 |
| #define cfgBIF_CFG_DEV1_EPF0_0_PCIE_LANE_0_EQUALIZATION_CNTL 0x027c |
| #define cfgBIF_CFG_DEV1_EPF0_0_PCIE_LANE_1_EQUALIZATION_CNTL 0x027e |
| #define cfgBIF_CFG_DEV1_EPF0_0_PCIE_LANE_2_EQUALIZATION_CNTL 0x0280 |
| #define cfgBIF_CFG_DEV1_EPF0_0_PCIE_LANE_3_EQUALIZATION_CNTL 0x0282 |
| #define cfgBIF_CFG_DEV1_EPF0_0_PCIE_LANE_4_EQUALIZATION_CNTL 0x0284 |
| #define cfgBIF_CFG_DEV1_EPF0_0_PCIE_LANE_5_EQUALIZATION_CNTL 0x0286 |
| #define cfgBIF_CFG_DEV1_EPF0_0_PCIE_LANE_6_EQUALIZATION_CNTL 0x0288 |
| #define cfgBIF_CFG_DEV1_EPF0_0_PCIE_LANE_7_EQUALIZATION_CNTL 0x028a |
| #define cfgBIF_CFG_DEV1_EPF0_0_PCIE_LANE_8_EQUALIZATION_CNTL 0x028c |
| #define cfgBIF_CFG_DEV1_EPF0_0_PCIE_LANE_9_EQUALIZATION_CNTL 0x028e |
| #define cfgBIF_CFG_DEV1_EPF0_0_PCIE_LANE_10_EQUALIZATION_CNTL 0x0290 |
| #define cfgBIF_CFG_DEV1_EPF0_0_PCIE_LANE_11_EQUALIZATION_CNTL 0x0292 |
| #define cfgBIF_CFG_DEV1_EPF0_0_PCIE_LANE_12_EQUALIZATION_CNTL 0x0294 |
| #define cfgBIF_CFG_DEV1_EPF0_0_PCIE_LANE_13_EQUALIZATION_CNTL 0x0296 |
| #define cfgBIF_CFG_DEV1_EPF0_0_PCIE_LANE_14_EQUALIZATION_CNTL 0x0298 |
| #define cfgBIF_CFG_DEV1_EPF0_0_PCIE_LANE_15_EQUALIZATION_CNTL 0x029a |
| #define cfgBIF_CFG_DEV1_EPF0_0_PCIE_ACS_ENH_CAP_LIST 0x02a0 |
| #define cfgBIF_CFG_DEV1_EPF0_0_PCIE_ACS_CAP 0x02a4 |
| #define cfgBIF_CFG_DEV1_EPF0_0_PCIE_ACS_CNTL 0x02a6 |
| #define cfgBIF_CFG_DEV1_EPF0_0_PCIE_LTR_ENH_CAP_LIST 0x0320 |
| #define cfgBIF_CFG_DEV1_EPF0_0_PCIE_LTR_CAP 0x0324 |
| #define cfgBIF_CFG_DEV1_EPF0_0_PCIE_ARI_ENH_CAP_LIST 0x0328 |
| #define cfgBIF_CFG_DEV1_EPF0_0_PCIE_ARI_CAP 0x032c |
| #define cfgBIF_CFG_DEV1_EPF0_0_PCIE_ARI_CNTL 0x032e |
| |
| |
| // addressBlock: nbio_nbif0_bif_cfg_dev1_epf1_bifcfgdecp |
| // base address: 0x0 |
| #define cfgBIF_CFG_DEV1_EPF1_0_VENDOR_ID 0x0000 |
| #define cfgBIF_CFG_DEV1_EPF1_0_DEVICE_ID 0x0002 |
| #define cfgBIF_CFG_DEV1_EPF1_0_COMMAND 0x0004 |
| #define cfgBIF_CFG_DEV1_EPF1_0_STATUS 0x0006 |
| #define cfgBIF_CFG_DEV1_EPF1_0_REVISION_ID 0x0008 |
| #define cfgBIF_CFG_DEV1_EPF1_0_PROG_INTERFACE 0x0009 |
| #define cfgBIF_CFG_DEV1_EPF1_0_SUB_CLASS 0x000a |
| #define cfgBIF_CFG_DEV1_EPF1_0_BASE_CLASS 0x000b |
| #define cfgBIF_CFG_DEV1_EPF1_0_CACHE_LINE 0x000c |
| #define cfgBIF_CFG_DEV1_EPF1_0_LATENCY 0x000d |
| #define cfgBIF_CFG_DEV1_EPF1_0_HEADER 0x000e |
| #define cfgBIF_CFG_DEV1_EPF1_0_BIST 0x000f |
| #define cfgBIF_CFG_DEV1_EPF1_0_BASE_ADDR_1 0x0010 |
| #define cfgBIF_CFG_DEV1_EPF1_0_BASE_ADDR_2 0x0014 |
| #define cfgBIF_CFG_DEV1_EPF1_0_BASE_ADDR_3 0x0018 |
| #define cfgBIF_CFG_DEV1_EPF1_0_BASE_ADDR_4 0x001c |
| #define cfgBIF_CFG_DEV1_EPF1_0_BASE_ADDR_5 0x0020 |
| #define cfgBIF_CFG_DEV1_EPF1_0_BASE_ADDR_6 0x0024 |
| #define cfgBIF_CFG_DEV1_EPF1_0_ADAPTER_ID 0x002c |
| #define cfgBIF_CFG_DEV1_EPF1_0_ROM_BASE_ADDR 0x0030 |
| #define cfgBIF_CFG_DEV1_EPF1_0_CAP_PTR 0x0034 |
| #define cfgBIF_CFG_DEV1_EPF1_0_INTERRUPT_LINE 0x003c |
| #define cfgBIF_CFG_DEV1_EPF1_0_INTERRUPT_PIN 0x003d |
| #define cfgBIF_CFG_DEV1_EPF1_0_MIN_GRANT 0x003e |
| #define cfgBIF_CFG_DEV1_EPF1_0_MAX_LATENCY 0x003f |
| #define cfgBIF_CFG_DEV1_EPF1_0_VENDOR_CAP_LIST 0x0048 |
| #define cfgBIF_CFG_DEV1_EPF1_0_ADAPTER_ID_W 0x004c |
| #define cfgBIF_CFG_DEV1_EPF1_0_PMI_CAP_LIST 0x0050 |
| #define cfgBIF_CFG_DEV1_EPF1_0_PMI_CAP 0x0052 |
| #define cfgBIF_CFG_DEV1_EPF1_0_PMI_STATUS_CNTL 0x0054 |
| #define cfgBIF_CFG_DEV1_EPF1_0_SBRN 0x0060 |
| #define cfgBIF_CFG_DEV1_EPF1_0_FLADJ 0x0061 |
| #define cfgBIF_CFG_DEV1_EPF1_0_DBESL_DBESLD 0x0062 |
| #define cfgBIF_CFG_DEV1_EPF1_0_PCIE_CAP_LIST 0x0064 |
| #define cfgBIF_CFG_DEV1_EPF1_0_PCIE_CAP 0x0066 |
| #define cfgBIF_CFG_DEV1_EPF1_0_DEVICE_CAP 0x0068 |
| #define cfgBIF_CFG_DEV1_EPF1_0_DEVICE_CNTL 0x006c |
| #define cfgBIF_CFG_DEV1_EPF1_0_DEVICE_STATUS 0x006e |
| #define cfgBIF_CFG_DEV1_EPF1_0_LINK_CAP 0x0070 |
| #define cfgBIF_CFG_DEV1_EPF1_0_LINK_CNTL 0x0074 |
| #define cfgBIF_CFG_DEV1_EPF1_0_LINK_STATUS 0x0076 |
| #define cfgBIF_CFG_DEV1_EPF1_0_DEVICE_CAP2 0x0088 |
| #define cfgBIF_CFG_DEV1_EPF1_0_DEVICE_CNTL2 0x008c |
| #define cfgBIF_CFG_DEV1_EPF1_0_DEVICE_STATUS2 0x008e |
| #define cfgBIF_CFG_DEV1_EPF1_0_LINK_CAP2 0x0090 |
| #define cfgBIF_CFG_DEV1_EPF1_0_LINK_CNTL2 0x0094 |
| #define cfgBIF_CFG_DEV1_EPF1_0_LINK_STATUS2 0x0096 |
| #define cfgBIF_CFG_DEV1_EPF1_0_SLOT_CAP2 0x0098 |
| #define cfgBIF_CFG_DEV1_EPF1_0_SLOT_CNTL2 0x009c |
| #define cfgBIF_CFG_DEV1_EPF1_0_SLOT_STATUS2 0x009e |
| #define cfgBIF_CFG_DEV1_EPF1_0_MSI_CAP_LIST 0x00a0 |
| #define cfgBIF_CFG_DEV1_EPF1_0_MSI_MSG_CNTL 0x00a2 |
| #define cfgBIF_CFG_DEV1_EPF1_0_MSI_MSG_ADDR_LO 0x00a4 |
| #define cfgBIF_CFG_DEV1_EPF1_0_MSI_MSG_ADDR_HI 0x00a8 |
| #define cfgBIF_CFG_DEV1_EPF1_0_MSI_MSG_DATA 0x00a8 |
| #define cfgBIF_CFG_DEV1_EPF1_0_MSI_MASK 0x00ac |
| #define cfgBIF_CFG_DEV1_EPF1_0_MSI_MSG_DATA_64 0x00ac |
| #define cfgBIF_CFG_DEV1_EPF1_0_MSI_MASK_64 0x00b0 |
| #define cfgBIF_CFG_DEV1_EPF1_0_MSI_PENDING 0x00b0 |
| #define cfgBIF_CFG_DEV1_EPF1_0_MSI_PENDING_64 0x00b4 |
| #define cfgBIF_CFG_DEV1_EPF1_0_MSIX_CAP_LIST 0x00c0 |
| #define cfgBIF_CFG_DEV1_EPF1_0_MSIX_MSG_CNTL 0x00c2 |
| #define cfgBIF_CFG_DEV1_EPF1_0_MSIX_TABLE 0x00c4 |
| #define cfgBIF_CFG_DEV1_EPF1_0_MSIX_PBA 0x00c8 |
| #define cfgBIF_CFG_DEV1_EPF1_0_SATA_CAP_0 0x00d0 |
| #define cfgBIF_CFG_DEV1_EPF1_0_SATA_CAP_1 0x00d4 |
| #define cfgBIF_CFG_DEV1_EPF1_0_SATA_IDP_INDEX 0x00d8 |
| #define cfgBIF_CFG_DEV1_EPF1_0_SATA_IDP_DATA 0x00dc |
| #define cfgBIF_CFG_DEV1_EPF1_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x0100 |
| #define cfgBIF_CFG_DEV1_EPF1_0_PCIE_VENDOR_SPECIFIC_HDR 0x0104 |
| #define cfgBIF_CFG_DEV1_EPF1_0_PCIE_VENDOR_SPECIFIC1 0x0108 |
| #define cfgBIF_CFG_DEV1_EPF1_0_PCIE_VENDOR_SPECIFIC2 0x010c |
| #define cfgBIF_CFG_DEV1_EPF1_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x0150 |
| #define cfgBIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_STATUS 0x0154 |
| #define cfgBIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_MASK 0x0158 |
| #define cfgBIF_CFG_DEV1_EPF1_0_PCIE_UNCORR_ERR_SEVERITY 0x015c |
| #define cfgBIF_CFG_DEV1_EPF1_0_PCIE_CORR_ERR_STATUS 0x0160 |
| #define cfgBIF_CFG_DEV1_EPF1_0_PCIE_CORR_ERR_MASK 0x0164 |
| #define cfgBIF_CFG_DEV1_EPF1_0_PCIE_ADV_ERR_CAP_CNTL 0x0168 |
| #define cfgBIF_CFG_DEV1_EPF1_0_PCIE_HDR_LOG0 0x016c |
| #define cfgBIF_CFG_DEV1_EPF1_0_PCIE_HDR_LOG1 0x0170 |
| #define cfgBIF_CFG_DEV1_EPF1_0_PCIE_HDR_LOG2 0x0174 |
| #define cfgBIF_CFG_DEV1_EPF1_0_PCIE_HDR_LOG3 0x0178 |
| #define cfgBIF_CFG_DEV1_EPF1_0_PCIE_TLP_PREFIX_LOG0 0x0188 |
| #define cfgBIF_CFG_DEV1_EPF1_0_PCIE_TLP_PREFIX_LOG1 0x018c |
| #define cfgBIF_CFG_DEV1_EPF1_0_PCIE_TLP_PREFIX_LOG2 0x0190 |
| #define cfgBIF_CFG_DEV1_EPF1_0_PCIE_TLP_PREFIX_LOG3 0x0194 |
| #define cfgBIF_CFG_DEV1_EPF1_0_PCIE_BAR_ENH_CAP_LIST 0x0200 |
| #define cfgBIF_CFG_DEV1_EPF1_0_PCIE_BAR1_CAP 0x0204 |
| #define cfgBIF_CFG_DEV1_EPF1_0_PCIE_BAR1_CNTL 0x0208 |
| #define cfgBIF_CFG_DEV1_EPF1_0_PCIE_BAR2_CAP 0x020c |
| #define cfgBIF_CFG_DEV1_EPF1_0_PCIE_BAR2_CNTL 0x0210 |
| #define cfgBIF_CFG_DEV1_EPF1_0_PCIE_BAR3_CAP 0x0214 |
| #define cfgBIF_CFG_DEV1_EPF1_0_PCIE_BAR3_CNTL 0x0218 |
| #define cfgBIF_CFG_DEV1_EPF1_0_PCIE_BAR4_CAP 0x021c |
| #define cfgBIF_CFG_DEV1_EPF1_0_PCIE_BAR4_CNTL 0x0220 |
| #define cfgBIF_CFG_DEV1_EPF1_0_PCIE_BAR5_CAP 0x0224 |
| #define cfgBIF_CFG_DEV1_EPF1_0_PCIE_BAR5_CNTL 0x0228 |
| #define cfgBIF_CFG_DEV1_EPF1_0_PCIE_BAR6_CAP 0x022c |
| #define cfgBIF_CFG_DEV1_EPF1_0_PCIE_BAR6_CNTL 0x0230 |
| #define cfgBIF_CFG_DEV1_EPF1_0_PCIE_PWR_BUDGET_ENH_CAP_LIST 0x0240 |
| #define cfgBIF_CFG_DEV1_EPF1_0_PCIE_PWR_BUDGET_DATA_SELECT 0x0244 |
| #define cfgBIF_CFG_DEV1_EPF1_0_PCIE_PWR_BUDGET_DATA 0x0248 |
| #define cfgBIF_CFG_DEV1_EPF1_0_PCIE_PWR_BUDGET_CAP 0x024c |
| #define cfgBIF_CFG_DEV1_EPF1_0_PCIE_DPA_ENH_CAP_LIST 0x0250 |
| #define cfgBIF_CFG_DEV1_EPF1_0_PCIE_DPA_CAP 0x0254 |
| #define cfgBIF_CFG_DEV1_EPF1_0_PCIE_DPA_LATENCY_INDICATOR 0x0258 |
| #define cfgBIF_CFG_DEV1_EPF1_0_PCIE_DPA_STATUS 0x025c |
| #define cfgBIF_CFG_DEV1_EPF1_0_PCIE_DPA_CNTL 0x025e |
| #define cfgBIF_CFG_DEV1_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0 0x0260 |
| #define cfgBIF_CFG_DEV1_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1 0x0261 |
| #define cfgBIF_CFG_DEV1_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2 0x0262 |
| #define cfgBIF_CFG_DEV1_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3 0x0263 |
| #define cfgBIF_CFG_DEV1_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4 0x0264 |
| #define cfgBIF_CFG_DEV1_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5 0x0265 |
| #define cfgBIF_CFG_DEV1_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6 0x0266 |
| #define cfgBIF_CFG_DEV1_EPF1_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7 0x0267 |
| #define cfgBIF_CFG_DEV1_EPF1_0_PCIE_ACS_ENH_CAP_LIST 0x02a0 |
| #define cfgBIF_CFG_DEV1_EPF1_0_PCIE_ACS_CAP 0x02a4 |
| #define cfgBIF_CFG_DEV1_EPF1_0_PCIE_ACS_CNTL 0x02a6 |
| #define cfgBIF_CFG_DEV1_EPF1_0_PCIE_ARI_ENH_CAP_LIST 0x0328 |
| #define cfgBIF_CFG_DEV1_EPF1_0_PCIE_ARI_CAP 0x032c |
| #define cfgBIF_CFG_DEV1_EPF1_0_PCIE_ARI_CNTL 0x032e |
| |
| |
| // addressBlock: nbio_nbif0_bif_cfg_dev1_epf2_bifcfgdecp |
| // base address: 0x0 |
| #define cfgBIF_CFG_DEV1_EPF2_0_VENDOR_ID 0x0000 |
| #define cfgBIF_CFG_DEV1_EPF2_0_DEVICE_ID 0x0002 |
| #define cfgBIF_CFG_DEV1_EPF2_0_COMMAND 0x0004 |
| #define cfgBIF_CFG_DEV1_EPF2_0_STATUS 0x0006 |
| #define cfgBIF_CFG_DEV1_EPF2_0_REVISION_ID 0x0008 |
| #define cfgBIF_CFG_DEV1_EPF2_0_PROG_INTERFACE 0x0009 |
| #define cfgBIF_CFG_DEV1_EPF2_0_SUB_CLASS 0x000a |
| #define cfgBIF_CFG_DEV1_EPF2_0_BASE_CLASS 0x000b |
| #define cfgBIF_CFG_DEV1_EPF2_0_CACHE_LINE 0x000c |
| #define cfgBIF_CFG_DEV1_EPF2_0_LATENCY 0x000d |
| #define cfgBIF_CFG_DEV1_EPF2_0_HEADER 0x000e |
| #define cfgBIF_CFG_DEV1_EPF2_0_BIST 0x000f |
| #define cfgBIF_CFG_DEV1_EPF2_0_BASE_ADDR_1 0x0010 |
| #define cfgBIF_CFG_DEV1_EPF2_0_BASE_ADDR_2 0x0014 |
| #define cfgBIF_CFG_DEV1_EPF2_0_BASE_ADDR_3 0x0018 |
| #define cfgBIF_CFG_DEV1_EPF2_0_BASE_ADDR_4 0x001c |
| #define cfgBIF_CFG_DEV1_EPF2_0_BASE_ADDR_5 0x0020 |
| #define cfgBIF_CFG_DEV1_EPF2_0_BASE_ADDR_6 0x0024 |
| #define cfgBIF_CFG_DEV1_EPF2_0_ADAPTER_ID 0x002c |
| #define cfgBIF_CFG_DEV1_EPF2_0_ROM_BASE_ADDR 0x0030 |
| #define cfgBIF_CFG_DEV1_EPF2_0_CAP_PTR 0x0034 |
| #define cfgBIF_CFG_DEV1_EPF2_0_INTERRUPT_LINE 0x003c |
| #define cfgBIF_CFG_DEV1_EPF2_0_INTERRUPT_PIN 0x003d |
| #define cfgBIF_CFG_DEV1_EPF2_0_MIN_GRANT 0x003e |
| #define cfgBIF_CFG_DEV1_EPF2_0_MAX_LATENCY 0x003f |
| #define cfgBIF_CFG_DEV1_EPF2_0_VENDOR_CAP_LIST 0x0048 |
| #define cfgBIF_CFG_DEV1_EPF2_0_ADAPTER_ID_W 0x004c |
| #define cfgBIF_CFG_DEV1_EPF2_0_PMI_CAP_LIST 0x0050 |
| #define cfgBIF_CFG_DEV1_EPF2_0_PMI_CAP 0x0052 |
| #define cfgBIF_CFG_DEV1_EPF2_0_PMI_STATUS_CNTL 0x0054 |
| #define cfgBIF_CFG_DEV1_EPF2_0_SBRN 0x0060 |
| #define cfgBIF_CFG_DEV1_EPF2_0_FLADJ 0x0061 |
| #define cfgBIF_CFG_DEV1_EPF2_0_DBESL_DBESLD 0x0062 |
| #define cfgBIF_CFG_DEV1_EPF2_0_PCIE_CAP_LIST 0x0064 |
| #define cfgBIF_CFG_DEV1_EPF2_0_PCIE_CAP 0x0066 |
| #define cfgBIF_CFG_DEV1_EPF2_0_DEVICE_CAP 0x0068 |
| #define cfgBIF_CFG_DEV1_EPF2_0_DEVICE_CNTL 0x006c |
| #define cfgBIF_CFG_DEV1_EPF2_0_DEVICE_STATUS 0x006e |
| #define cfgBIF_CFG_DEV1_EPF2_0_LINK_CAP 0x0070 |
| #define cfgBIF_CFG_DEV1_EPF2_0_LINK_CNTL 0x0074 |
| #define cfgBIF_CFG_DEV1_EPF2_0_LINK_STATUS 0x0076 |
| #define cfgBIF_CFG_DEV1_EPF2_0_DEVICE_CAP2 0x0088 |
| #define cfgBIF_CFG_DEV1_EPF2_0_DEVICE_CNTL2 0x008c |
| #define cfgBIF_CFG_DEV1_EPF2_0_DEVICE_STATUS2 0x008e |
| #define cfgBIF_CFG_DEV1_EPF2_0_LINK_CAP2 0x0090 |
| #define cfgBIF_CFG_DEV1_EPF2_0_LINK_CNTL2 0x0094 |
| #define cfgBIF_CFG_DEV1_EPF2_0_LINK_STATUS2 0x0096 |
| #define cfgBIF_CFG_DEV1_EPF2_0_SLOT_CAP2 0x0098 |
| #define cfgBIF_CFG_DEV1_EPF2_0_SLOT_CNTL2 0x009c |
| #define cfgBIF_CFG_DEV1_EPF2_0_SLOT_STATUS2 0x009e |
| #define cfgBIF_CFG_DEV1_EPF2_0_MSI_CAP_LIST 0x00a0 |
| #define cfgBIF_CFG_DEV1_EPF2_0_MSI_MSG_CNTL 0x00a2 |
| #define cfgBIF_CFG_DEV1_EPF2_0_MSI_MSG_ADDR_LO 0x00a4 |
| #define cfgBIF_CFG_DEV1_EPF2_0_MSI_MSG_ADDR_HI 0x00a8 |
| #define cfgBIF_CFG_DEV1_EPF2_0_MSI_MSG_DATA 0x00a8 |
| #define cfgBIF_CFG_DEV1_EPF2_0_MSI_MASK 0x00ac |
| #define cfgBIF_CFG_DEV1_EPF2_0_MSI_MSG_DATA_64 0x00ac |
| #define cfgBIF_CFG_DEV1_EPF2_0_MSI_MASK_64 0x00b0 |
| #define cfgBIF_CFG_DEV1_EPF2_0_MSI_PENDING 0x00b0 |
| #define cfgBIF_CFG_DEV1_EPF2_0_MSI_PENDING_64 0x00b4 |
| #define cfgBIF_CFG_DEV1_EPF2_0_MSIX_CAP_LIST 0x00c0 |
| #define cfgBIF_CFG_DEV1_EPF2_0_MSIX_MSG_CNTL 0x00c2 |
| #define cfgBIF_CFG_DEV1_EPF2_0_MSIX_TABLE 0x00c4 |
| #define cfgBIF_CFG_DEV1_EPF2_0_MSIX_PBA 0x00c8 |
| #define cfgBIF_CFG_DEV1_EPF2_0_SATA_CAP_0 0x00d0 |
| #define cfgBIF_CFG_DEV1_EPF2_0_SATA_CAP_1 0x00d4 |
| #define cfgBIF_CFG_DEV1_EPF2_0_SATA_IDP_INDEX 0x00d8 |
| #define cfgBIF_CFG_DEV1_EPF2_0_SATA_IDP_DATA 0x00dc |
| #define cfgBIF_CFG_DEV1_EPF2_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x0100 |
| #define cfgBIF_CFG_DEV1_EPF2_0_PCIE_VENDOR_SPECIFIC_HDR 0x0104 |
| #define cfgBIF_CFG_DEV1_EPF2_0_PCIE_VENDOR_SPECIFIC1 0x0108 |
| #define cfgBIF_CFG_DEV1_EPF2_0_PCIE_VENDOR_SPECIFIC2 0x010c |
| #define cfgBIF_CFG_DEV1_EPF2_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x0150 |
| #define cfgBIF_CFG_DEV1_EPF2_0_PCIE_UNCORR_ERR_STATUS 0x0154 |
| #define cfgBIF_CFG_DEV1_EPF2_0_PCIE_UNCORR_ERR_MASK 0x0158 |
| #define cfgBIF_CFG_DEV1_EPF2_0_PCIE_UNCORR_ERR_SEVERITY 0x015c |
| #define cfgBIF_CFG_DEV1_EPF2_0_PCIE_CORR_ERR_STATUS 0x0160 |
| #define cfgBIF_CFG_DEV1_EPF2_0_PCIE_CORR_ERR_MASK 0x0164 |
| #define cfgBIF_CFG_DEV1_EPF2_0_PCIE_ADV_ERR_CAP_CNTL 0x0168 |
| #define cfgBIF_CFG_DEV1_EPF2_0_PCIE_HDR_LOG0 0x016c |
| #define cfgBIF_CFG_DEV1_EPF2_0_PCIE_HDR_LOG1 0x0170 |
| #define cfgBIF_CFG_DEV1_EPF2_0_PCIE_HDR_LOG2 0x0174 |
| #define cfgBIF_CFG_DEV1_EPF2_0_PCIE_HDR_LOG3 0x0178 |
| #define cfgBIF_CFG_DEV1_EPF2_0_PCIE_TLP_PREFIX_LOG0 0x0188 |
| #define cfgBIF_CFG_DEV1_EPF2_0_PCIE_TLP_PREFIX_LOG1 0x018c |
| #define cfgBIF_CFG_DEV1_EPF2_0_PCIE_TLP_PREFIX_LOG2 0x0190 |
| #define cfgBIF_CFG_DEV1_EPF2_0_PCIE_TLP_PREFIX_LOG3 0x0194 |
| #define cfgBIF_CFG_DEV1_EPF2_0_PCIE_BAR_ENH_CAP_LIST 0x0200 |
| #define cfgBIF_CFG_DEV1_EPF2_0_PCIE_BAR1_CAP 0x0204 |
| #define cfgBIF_CFG_DEV1_EPF2_0_PCIE_BAR1_CNTL 0x0208 |
| #define cfgBIF_CFG_DEV1_EPF2_0_PCIE_BAR2_CAP 0x020c |
| #define cfgBIF_CFG_DEV1_EPF2_0_PCIE_BAR2_CNTL 0x0210 |
| #define cfgBIF_CFG_DEV1_EPF2_0_PCIE_BAR3_CAP 0x0214 |
| #define cfgBIF_CFG_DEV1_EPF2_0_PCIE_BAR3_CNTL 0x0218 |
| #define cfgBIF_CFG_DEV1_EPF2_0_PCIE_BAR4_CAP 0x021c |
| #define cfgBIF_CFG_DEV1_EPF2_0_PCIE_BAR4_CNTL 0x0220 |
| #define cfgBIF_CFG_DEV1_EPF2_0_PCIE_BAR5_CAP 0x0224 |
| #define cfgBIF_CFG_DEV1_EPF2_0_PCIE_BAR5_CNTL 0x0228 |
| #define cfgBIF_CFG_DEV1_EPF2_0_PCIE_BAR6_CAP 0x022c |
| #define cfgBIF_CFG_DEV1_EPF2_0_PCIE_BAR6_CNTL 0x0230 |
| #define cfgBIF_CFG_DEV1_EPF2_0_PCIE_PWR_BUDGET_ENH_CAP_LIST 0x0240 |
| #define cfgBIF_CFG_DEV1_EPF2_0_PCIE_PWR_BUDGET_DATA_SELECT 0x0244 |
| #define cfgBIF_CFG_DEV1_EPF2_0_PCIE_PWR_BUDGET_DATA 0x0248 |
| #define cfgBIF_CFG_DEV1_EPF2_0_PCIE_PWR_BUDGET_CAP 0x024c |
| #define cfgBIF_CFG_DEV1_EPF2_0_PCIE_DPA_ENH_CAP_LIST 0x0250 |
| #define cfgBIF_CFG_DEV1_EPF2_0_PCIE_DPA_CAP 0x0254 |
| #define cfgBIF_CFG_DEV1_EPF2_0_PCIE_DPA_LATENCY_INDICATOR 0x0258 |
| #define cfgBIF_CFG_DEV1_EPF2_0_PCIE_DPA_STATUS 0x025c |
| #define cfgBIF_CFG_DEV1_EPF2_0_PCIE_DPA_CNTL 0x025e |
| #define cfgBIF_CFG_DEV1_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0 0x0260 |
| #define cfgBIF_CFG_DEV1_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1 0x0261 |
| #define cfgBIF_CFG_DEV1_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2 0x0262 |
| #define cfgBIF_CFG_DEV1_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3 0x0263 |
| #define cfgBIF_CFG_DEV1_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4 0x0264 |
| #define cfgBIF_CFG_DEV1_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5 0x0265 |
| #define cfgBIF_CFG_DEV1_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6 0x0266 |
| #define cfgBIF_CFG_DEV1_EPF2_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7 0x0267 |
| #define cfgBIF_CFG_DEV1_EPF2_0_PCIE_ACS_ENH_CAP_LIST 0x02a0 |
| #define cfgBIF_CFG_DEV1_EPF2_0_PCIE_ACS_CAP 0x02a4 |
| #define cfgBIF_CFG_DEV1_EPF2_0_PCIE_ACS_CNTL 0x02a6 |
| #define cfgBIF_CFG_DEV1_EPF2_0_PCIE_ARI_ENH_CAP_LIST 0x0328 |
| #define cfgBIF_CFG_DEV1_EPF2_0_PCIE_ARI_CAP 0x032c |
| #define cfgBIF_CFG_DEV1_EPF2_0_PCIE_ARI_CNTL 0x032e |
| |
| |
| // addressBlock: nbio_pcie0_bifplr0_cfgdecp |
| // base address: 0x0 |
| #define cfgBIFPLR0_0_VENDOR_ID 0x0000 |
| #define cfgBIFPLR0_0_DEVICE_ID 0x0002 |
| #define cfgBIFPLR0_0_COMMAND 0x0004 |
| #define cfgBIFPLR0_0_STATUS 0x0006 |
| #define cfgBIFPLR0_0_REVISION_ID 0x0008 |
| #define cfgBIFPLR0_0_PROG_INTERFACE 0x0009 |
| #define cfgBIFPLR0_0_SUB_CLASS 0x000a |
| #define cfgBIFPLR0_0_BASE_CLASS 0x000b |
| #define cfgBIFPLR0_0_CACHE_LINE 0x000c |
| #define cfgBIFPLR0_0_LATENCY 0x000d |
| #define cfgBIFPLR0_0_HEADER 0x000e |
| #define cfgBIFPLR0_0_BIST 0x000f |
| #define cfgBIFPLR0_0_SUB_BUS_NUMBER_LATENCY 0x0018 |
| #define cfgBIFPLR0_0_IO_BASE_LIMIT 0x001c |
| #define cfgBIFPLR0_0_SECONDARY_STATUS 0x001e |
| #define cfgBIFPLR0_0_MEM_BASE_LIMIT 0x0020 |
| #define cfgBIFPLR0_0_PREF_BASE_LIMIT 0x0024 |
| #define cfgBIFPLR0_0_PREF_BASE_UPPER 0x0028 |
| #define cfgBIFPLR0_0_PREF_LIMIT_UPPER 0x002c |
| #define cfgBIFPLR0_0_IO_BASE_LIMIT_HI 0x0030 |
| #define cfgBIFPLR0_0_CAP_PTR 0x0034 |
| #define cfgBIFPLR0_0_INTERRUPT_LINE 0x003c |
| #define cfgBIFPLR0_0_INTERRUPT_PIN 0x003d |
| #define cfgBIFPLR0_0_IRQ_BRIDGE_CNTL 0x003e |
| #define cfgBIFPLR0_0_EXT_BRIDGE_CNTL 0x0040 |
| #define cfgBIFPLR0_0_PMI_CAP_LIST 0x0050 |
| #define cfgBIFPLR0_0_PMI_CAP 0x0052 |
| #define cfgBIFPLR0_0_PMI_STATUS_CNTL 0x0054 |
| #define cfgBIFPLR0_0_PCIE_CAP_LIST 0x0058 |
| #define cfgBIFPLR0_0_PCIE_CAP 0x005a |
| #define cfgBIFPLR0_0_DEVICE_CAP 0x005c |
| #define cfgBIFPLR0_0_DEVICE_CNTL 0x0060 |
| #define cfgBIFPLR0_0_DEVICE_STATUS 0x0062 |
| #define cfgBIFPLR0_0_LINK_CAP 0x0064 |
| #define cfgBIFPLR0_0_LINK_CNTL 0x0068 |
| #define cfgBIFPLR0_0_LINK_STATUS 0x006a |
| #define cfgBIFPLR0_0_SLOT_CAP 0x006c |
| #define cfgBIFPLR0_0_SLOT_CNTL 0x0070 |
| #define cfgBIFPLR0_0_SLOT_STATUS 0x0072 |
| #define cfgBIFPLR0_0_ROOT_CNTL 0x0074 |
| #define cfgBIFPLR0_0_ROOT_CAP 0x0076 |
| #define cfgBIFPLR0_0_ROOT_STATUS 0x0078 |
| #define cfgBIFPLR0_0_DEVICE_CAP2 0x007c |
| #define cfgBIFPLR0_0_DEVICE_CNTL2 0x0080 |
| #define cfgBIFPLR0_0_DEVICE_STATUS2 0x0082 |
| #define cfgBIFPLR0_0_LINK_CAP2 0x0084 |
| #define cfgBIFPLR0_0_LINK_CNTL2 0x0088 |
| #define cfgBIFPLR0_0_LINK_STATUS2 0x008a |
| #define cfgBIFPLR0_0_SLOT_CAP2 0x008c |
| #define cfgBIFPLR0_0_SLOT_CNTL2 0x0090 |
| #define cfgBIFPLR0_0_SLOT_STATUS2 0x0092 |
| #define cfgBIFPLR0_0_MSI_CAP_LIST 0x00a0 |
| #define cfgBIFPLR0_0_MSI_MSG_CNTL 0x00a2 |
| #define cfgBIFPLR0_0_MSI_MSG_ADDR_LO 0x00a4 |
| #define cfgBIFPLR0_0_MSI_MSG_ADDR_HI 0x00a8 |
| #define cfgBIFPLR0_0_MSI_MSG_DATA 0x00a8 |
| #define cfgBIFPLR0_0_MSI_MSG_DATA_64 0x00ac |
| #define cfgBIFPLR0_0_SSID_CAP_LIST 0x00c0 |
| #define cfgBIFPLR0_0_SSID_CAP 0x00c4 |
| #define cfgBIFPLR0_0_MSI_MAP_CAP_LIST 0x00c8 |
| #define cfgBIFPLR0_0_MSI_MAP_CAP 0x00ca |
| #define cfgBIFPLR0_0_MSI_MAP_ADDR_LO 0x00cc |
| #define cfgBIFPLR0_0_MSI_MAP_ADDR_HI 0x00d0 |
| #define cfgBIFPLR0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x0100 |
| #define cfgBIFPLR0_0_PCIE_VENDOR_SPECIFIC_HDR 0x0104 |
| #define cfgBIFPLR0_0_PCIE_VENDOR_SPECIFIC1 0x0108 |
| #define cfgBIFPLR0_0_PCIE_VENDOR_SPECIFIC2 0x010c |
| #define cfgBIFPLR0_0_PCIE_VC_ENH_CAP_LIST 0x0110 |
| #define cfgBIFPLR0_0_PCIE_PORT_VC_CAP_REG1 0x0114 |
| #define cfgBIFPLR0_0_PCIE_PORT_VC_CAP_REG2 0x0118 |
| #define cfgBIFPLR0_0_PCIE_PORT_VC_CNTL 0x011c |
| #define cfgBIFPLR0_0_PCIE_PORT_VC_STATUS 0x011e |
| #define cfgBIFPLR0_0_PCIE_VC0_RESOURCE_CAP 0x0120 |
| #define cfgBIFPLR0_0_PCIE_VC0_RESOURCE_CNTL 0x0124 |
| #define cfgBIFPLR0_0_PCIE_VC0_RESOURCE_STATUS 0x012a |
| #define cfgBIFPLR0_0_PCIE_VC1_RESOURCE_CAP 0x012c |
| #define cfgBIFPLR0_0_PCIE_VC1_RESOURCE_CNTL 0x0130 |
| #define cfgBIFPLR0_0_PCIE_VC1_RESOURCE_STATUS 0x0136 |
| #define cfgBIFPLR0_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST 0x0140 |
| #define cfgBIFPLR0_0_PCIE_DEV_SERIAL_NUM_DW1 0x0144 |
| #define cfgBIFPLR0_0_PCIE_DEV_SERIAL_NUM_DW2 0x0148 |
| #define cfgBIFPLR0_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x0150 |
| #define cfgBIFPLR0_0_PCIE_UNCORR_ERR_STATUS 0x0154 |
| #define cfgBIFPLR0_0_PCIE_UNCORR_ERR_MASK 0x0158 |
| #define cfgBIFPLR0_0_PCIE_UNCORR_ERR_SEVERITY 0x015c |
| #define cfgBIFPLR0_0_PCIE_CORR_ERR_STATUS 0x0160 |
| #define cfgBIFPLR0_0_PCIE_CORR_ERR_MASK 0x0164 |
| #define cfgBIFPLR0_0_PCIE_ADV_ERR_CAP_CNTL 0x0168 |
| #define cfgBIFPLR0_0_PCIE_HDR_LOG0 0x016c |
| #define cfgBIFPLR0_0_PCIE_HDR_LOG1 0x0170 |
| #define cfgBIFPLR0_0_PCIE_HDR_LOG2 0x0174 |
| #define cfgBIFPLR0_0_PCIE_HDR_LOG3 0x0178 |
| #define cfgBIFPLR0_0_PCIE_ROOT_ERR_CMD 0x017c |
| #define cfgBIFPLR0_0_PCIE_ROOT_ERR_STATUS 0x0180 |
| #define cfgBIFPLR0_0_PCIE_ERR_SRC_ID 0x0184 |
| #define cfgBIFPLR0_0_PCIE_TLP_PREFIX_LOG0 0x0188 |
| #define cfgBIFPLR0_0_PCIE_TLP_PREFIX_LOG1 0x018c |
| #define cfgBIFPLR0_0_PCIE_TLP_PREFIX_LOG2 0x0190 |
| #define cfgBIFPLR0_0_PCIE_TLP_PREFIX_LOG3 0x0194 |
| #define cfgBIFPLR0_0_PCIE_SECONDARY_ENH_CAP_LIST 0x0270 |
| #define cfgBIFPLR0_0_PCIE_LINK_CNTL3 0x0274 |
| #define cfgBIFPLR0_0_PCIE_LANE_ERROR_STATUS 0x0278 |
| #define cfgBIFPLR0_0_PCIE_LANE_0_EQUALIZATION_CNTL 0x027c |
| #define cfgBIFPLR0_0_PCIE_LANE_1_EQUALIZATION_CNTL 0x027e |
| #define cfgBIFPLR0_0_PCIE_LANE_2_EQUALIZATION_CNTL 0x0280 |
| #define cfgBIFPLR0_0_PCIE_LANE_3_EQUALIZATION_CNTL 0x0282 |
| #define cfgBIFPLR0_0_PCIE_LANE_4_EQUALIZATION_CNTL 0x0284 |
| #define cfgBIFPLR0_0_PCIE_LANE_5_EQUALIZATION_CNTL 0x0286 |
| #define cfgBIFPLR0_0_PCIE_LANE_6_EQUALIZATION_CNTL 0x0288 |
| #define cfgBIFPLR0_0_PCIE_LANE_7_EQUALIZATION_CNTL 0x028a |
| #define cfgBIFPLR0_0_PCIE_LANE_8_EQUALIZATION_CNTL 0x028c |
| #define cfgBIFPLR0_0_PCIE_LANE_9_EQUALIZATION_CNTL 0x028e |
| #define cfgBIFPLR0_0_PCIE_LANE_10_EQUALIZATION_CNTL 0x0290 |
| #define cfgBIFPLR0_0_PCIE_LANE_11_EQUALIZATION_CNTL 0x0292 |
| #define cfgBIFPLR0_0_PCIE_LANE_12_EQUALIZATION_CNTL 0x0294 |
| #define cfgBIFPLR0_0_PCIE_LANE_13_EQUALIZATION_CNTL 0x0296 |
| #define cfgBIFPLR0_0_PCIE_LANE_14_EQUALIZATION_CNTL 0x0298 |
| #define cfgBIFPLR0_0_PCIE_LANE_15_EQUALIZATION_CNTL 0x029a |
| #define cfgBIFPLR0_0_PCIE_ACS_ENH_CAP_LIST 0x02a0 |
| #define cfgBIFPLR0_0_PCIE_ACS_CAP 0x02a4 |
| #define cfgBIFPLR0_0_PCIE_ACS_CNTL 0x02a6 |
| #define cfgBIFPLR0_0_PCIE_MC_ENH_CAP_LIST 0x02f0 |
| #define cfgBIFPLR0_0_PCIE_MC_CAP 0x02f4 |
| #define cfgBIFPLR0_0_PCIE_MC_CNTL 0x02f6 |
| #define cfgBIFPLR0_0_PCIE_MC_ADDR0 0x02f8 |
| #define cfgBIFPLR0_0_PCIE_MC_ADDR1 0x02fc |
| #define cfgBIFPLR0_0_PCIE_MC_RCV0 0x0300 |
| #define cfgBIFPLR0_0_PCIE_MC_RCV1 0x0304 |
| #define cfgBIFPLR0_0_PCIE_MC_BLOCK_ALL0 0x0308 |
| #define cfgBIFPLR0_0_PCIE_MC_BLOCK_ALL1 0x030c |
| #define cfgBIFPLR0_0_PCIE_MC_BLOCK_UNTRANSLATED_0 0x0310 |
| #define cfgBIFPLR0_0_PCIE_MC_BLOCK_UNTRANSLATED_1 0x0314 |
| #define cfgBIFPLR0_0_PCIE_MC_OVERLAY_BAR0 0x0318 |
| #define cfgBIFPLR0_0_PCIE_MC_OVERLAY_BAR1 0x031c |
| #define cfgBIFPLR0_0_PCIE_L1_PM_SUB_CAP_LIST 0x0370 |
| #define cfgBIFPLR0_0_PCIE_L1_PM_SUB_CAP 0x0374 |
| #define cfgBIFPLR0_0_PCIE_L1_PM_SUB_CNTL 0x0378 |
| #define cfgBIFPLR0_0_PCIE_L1_PM_SUB_CNTL2 0x037c |
| #define cfgBIFPLR0_0_PCIE_DPC_ENH_CAP_LIST 0x0380 |
| #define cfgBIFPLR0_0_PCIE_DPC_CAP_LIST 0x0384 |
| #define cfgBIFPLR0_0_PCIE_DPC_CNTL 0x0386 |
| #define cfgBIFPLR0_0_PCIE_DPC_STATUS 0x0388 |
| #define cfgBIFPLR0_0_PCIE_DPC_ERROR_SOURCE_ID 0x038a |
| #define cfgBIFPLR0_0_PCIE_RP_PIO_STATUS 0x038c |
| #define cfgBIFPLR0_0_PCIE_RP_PIO_MASK 0x0390 |
| #define cfgBIFPLR0_0_PCIE_RP_PIO_SEVERITY 0x0394 |
| #define cfgBIFPLR0_0_PCIE_RP_PIO_SYSERROR 0x0398 |
| #define cfgBIFPLR0_0_PCIE_RP_PIO_EXCEPTION 0x039c |
| #define cfgBIFPLR0_0_PCIE_RP_PIO_HDR_LOG0 0x03a0 |
| #define cfgBIFPLR0_0_PCIE_RP_PIO_HDR_LOG1 0x03a4 |
| #define cfgBIFPLR0_0_PCIE_RP_PIO_HDR_LOG2 0x03a8 |
| #define cfgBIFPLR0_0_PCIE_RP_PIO_HDR_LOG3 0x03ac |
| #define cfgBIFPLR0_0_PCIE_RP_PIO_IMPSPEC_LOG 0x03b0 |
| #define cfgBIFPLR0_0_PCIE_RP_PIO_PREFIX_LOG0 0x03b4 |
| #define cfgBIFPLR0_0_PCIE_RP_PIO_PREFIX_LOG1 0x03b8 |
| #define cfgBIFPLR0_0_PCIE_RP_PIO_PREFIX_LOG2 0x03bc |
| #define cfgBIFPLR0_0_PCIE_RP_PIO_PREFIX_LOG3 0x03c0 |
| #define cfgBIFPLR0_0_PCIE_ESM_CAP_LIST 0x03c4 |
| #define cfgBIFPLR0_0_PCIE_ESM_HEADER_1 0x03c8 |
| #define cfgBIFPLR0_0_PCIE_ESM_HEADER_2 0x03cc |
| #define cfgBIFPLR0_0_PCIE_ESM_STATUS 0x03ce |
| #define cfgBIFPLR0_0_PCIE_ESM_CTRL 0x03d0 |
| #define cfgBIFPLR0_0_PCIE_ESM_CAP_1 0x03d4 |
| #define cfgBIFPLR0_0_PCIE_ESM_CAP_2 0x03d8 |
| #define cfgBIFPLR0_0_PCIE_ESM_CAP_3 0x03dc |
| #define cfgBIFPLR0_0_PCIE_ESM_CAP_4 0x03e0 |
| #define cfgBIFPLR0_0_PCIE_ESM_CAP_5 0x03e4 |
| #define cfgBIFPLR0_0_PCIE_ESM_CAP_6 0x03e8 |
| #define cfgBIFPLR0_0_PCIE_ESM_CAP_7 0x03ec |
| |
| |
| // addressBlock: nbio_pcie0_bifplr1_cfgdecp |
| // base address: 0x0 |
| #define cfgBIFPLR1_0_VENDOR_ID 0x0000 |
| #define cfgBIFPLR1_0_DEVICE_ID 0x0002 |
| #define cfgBIFPLR1_0_COMMAND 0x0004 |
| #define cfgBIFPLR1_0_STATUS 0x0006 |
| #define cfgBIFPLR1_0_REVISION_ID 0x0008 |
| #define cfgBIFPLR1_0_PROG_INTERFACE 0x0009 |
| #define cfgBIFPLR1_0_SUB_CLASS 0x000a |
| #define cfgBIFPLR1_0_BASE_CLASS 0x000b |
| #define cfgBIFPLR1_0_CACHE_LINE 0x000c |
| #define cfgBIFPLR1_0_LATENCY 0x000d |
| #define cfgBIFPLR1_0_HEADER 0x000e |
| #define cfgBIFPLR1_0_BIST 0x000f |
| #define cfgBIFPLR1_0_SUB_BUS_NUMBER_LATENCY 0x0018 |
| #define cfgBIFPLR1_0_IO_BASE_LIMIT 0x001c |
| #define cfgBIFPLR1_0_SECONDARY_STATUS 0x001e |
| #define cfgBIFPLR1_0_MEM_BASE_LIMIT 0x0020 |
| #define cfgBIFPLR1_0_PREF_BASE_LIMIT 0x0024 |
| #define cfgBIFPLR1_0_PREF_BASE_UPPER 0x0028 |
| #define cfgBIFPLR1_0_PREF_LIMIT_UPPER 0x002c |
| #define cfgBIFPLR1_0_IO_BASE_LIMIT_HI 0x0030 |
| #define cfgBIFPLR1_0_CAP_PTR 0x0034 |
| #define cfgBIFPLR1_0_INTERRUPT_LINE 0x003c |
| #define cfgBIFPLR1_0_INTERRUPT_PIN 0x003d |
| #define cfgBIFPLR1_0_IRQ_BRIDGE_CNTL 0x003e |
| #define cfgBIFPLR1_0_EXT_BRIDGE_CNTL 0x0040 |
| #define cfgBIFPLR1_0_PMI_CAP_LIST 0x0050 |
| #define cfgBIFPLR1_0_PMI_CAP 0x0052 |
| #define cfgBIFPLR1_0_PMI_STATUS_CNTL 0x0054 |
| #define cfgBIFPLR1_0_PCIE_CAP_LIST 0x0058 |
| #define cfgBIFPLR1_0_PCIE_CAP 0x005a |
| #define cfgBIFPLR1_0_DEVICE_CAP 0x005c |
| #define cfgBIFPLR1_0_DEVICE_CNTL 0x0060 |
| #define cfgBIFPLR1_0_DEVICE_STATUS 0x0062 |
| #define cfgBIFPLR1_0_LINK_CAP 0x0064 |
| #define cfgBIFPLR1_0_LINK_CNTL 0x0068 |
| #define cfgBIFPLR1_0_LINK_STATUS 0x006a |
| #define cfgBIFPLR1_0_SLOT_CAP 0x006c |
| #define cfgBIFPLR1_0_SLOT_CNTL 0x0070 |
| #define cfgBIFPLR1_0_SLOT_STATUS 0x0072 |
| #define cfgBIFPLR1_0_ROOT_CNTL 0x0074 |
| #define cfgBIFPLR1_0_ROOT_CAP 0x0076 |
| #define cfgBIFPLR1_0_ROOT_STATUS 0x0078 |
| #define cfgBIFPLR1_0_DEVICE_CAP2 0x007c |
| #define cfgBIFPLR1_0_DEVICE_CNTL2 0x0080 |
| #define cfgBIFPLR1_0_DEVICE_STATUS2 0x0082 |
| #define cfgBIFPLR1_0_LINK_CAP2 0x0084 |
| #define cfgBIFPLR1_0_LINK_CNTL2 0x0088 |
| #define cfgBIFPLR1_0_LINK_STATUS2 0x008a |
| #define cfgBIFPLR1_0_SLOT_CAP2 0x008c |
| #define cfgBIFPLR1_0_SLOT_CNTL2 0x0090 |
| #define cfgBIFPLR1_0_SLOT_STATUS2 0x0092 |
| #define cfgBIFPLR1_0_MSI_CAP_LIST 0x00a0 |
| #define cfgBIFPLR1_0_MSI_MSG_CNTL 0x00a2 |
| #define cfgBIFPLR1_0_MSI_MSG_ADDR_LO 0x00a4 |
| #define cfgBIFPLR1_0_MSI_MSG_ADDR_HI 0x00a8 |
| #define cfgBIFPLR1_0_MSI_MSG_DATA 0x00a8 |
| #define cfgBIFPLR1_0_MSI_MSG_DATA_64 0x00ac |
| #define cfgBIFPLR1_0_SSID_CAP_LIST 0x00c0 |
| #define cfgBIFPLR1_0_SSID_CAP 0x00c4 |
| #define cfgBIFPLR1_0_MSI_MAP_CAP_LIST 0x00c8 |
| #define cfgBIFPLR1_0_MSI_MAP_CAP 0x00ca |
| #define cfgBIFPLR1_0_MSI_MAP_ADDR_LO 0x00cc |
| #define cfgBIFPLR1_0_MSI_MAP_ADDR_HI 0x00d0 |
| #define cfgBIFPLR1_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x0100 |
| #define cfgBIFPLR1_0_PCIE_VENDOR_SPECIFIC_HDR 0x0104 |
| #define cfgBIFPLR1_0_PCIE_VENDOR_SPECIFIC1 0x0108 |
| #define cfgBIFPLR1_0_PCIE_VENDOR_SPECIFIC2 0x010c |
| #define cfgBIFPLR1_0_PCIE_VC_ENH_CAP_LIST 0x0110 |
| #define cfgBIFPLR1_0_PCIE_PORT_VC_CAP_REG1 0x0114 |
| #define cfgBIFPLR1_0_PCIE_PORT_VC_CAP_REG2 0x0118 |
| #define cfgBIFPLR1_0_PCIE_PORT_VC_CNTL 0x011c |
| #define cfgBIFPLR1_0_PCIE_PORT_VC_STATUS 0x011e |
| #define cfgBIFPLR1_0_PCIE_VC0_RESOURCE_CAP 0x0120 |
| #define cfgBIFPLR1_0_PCIE_VC0_RESOURCE_CNTL 0x0124 |
| #define cfgBIFPLR1_0_PCIE_VC0_RESOURCE_STATUS 0x012a |
| #define cfgBIFPLR1_0_PCIE_VC1_RESOURCE_CAP 0x012c |
| #define cfgBIFPLR1_0_PCIE_VC1_RESOURCE_CNTL 0x0130 |
| #define cfgBIFPLR1_0_PCIE_VC1_RESOURCE_STATUS 0x0136 |
| #define cfgBIFPLR1_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST 0x0140 |
| #define cfgBIFPLR1_0_PCIE_DEV_SERIAL_NUM_DW1 0x0144 |
| #define cfgBIFPLR1_0_PCIE_DEV_SERIAL_NUM_DW2 0x0148 |
| #define cfgBIFPLR1_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x0150 |
| #define cfgBIFPLR1_0_PCIE_UNCORR_ERR_STATUS 0x0154 |
| #define cfgBIFPLR1_0_PCIE_UNCORR_ERR_MASK 0x0158 |
| #define cfgBIFPLR1_0_PCIE_UNCORR_ERR_SEVERITY 0x015c |
| #define cfgBIFPLR1_0_PCIE_CORR_ERR_STATUS 0x0160 |
| #define cfgBIFPLR1_0_PCIE_CORR_ERR_MASK 0x0164 |
| #define cfgBIFPLR1_0_PCIE_ADV_ERR_CAP_CNTL 0x0168 |
| #define cfgBIFPLR1_0_PCIE_HDR_LOG0 0x016c |
| #define cfgBIFPLR1_0_PCIE_HDR_LOG1 0x0170 |
| #define cfgBIFPLR1_0_PCIE_HDR_LOG2 0x0174 |
| #define cfgBIFPLR1_0_PCIE_HDR_LOG3 0x0178 |
| #define cfgBIFPLR1_0_PCIE_ROOT_ERR_CMD 0x017c |
| #define cfgBIFPLR1_0_PCIE_ROOT_ERR_STATUS 0x0180 |
| #define cfgBIFPLR1_0_PCIE_ERR_SRC_ID 0x0184 |
| #define cfgBIFPLR1_0_PCIE_TLP_PREFIX_LOG0 0x0188 |
| #define cfgBIFPLR1_0_PCIE_TLP_PREFIX_LOG1 0x018c |
| #define cfgBIFPLR1_0_PCIE_TLP_PREFIX_LOG2 0x0190 |
| #define cfgBIFPLR1_0_PCIE_TLP_PREFIX_LOG3 0x0194 |
| #define cfgBIFPLR1_0_PCIE_SECONDARY_ENH_CAP_LIST 0x0270 |
| #define cfgBIFPLR1_0_PCIE_LINK_CNTL3 0x0274 |
| #define cfgBIFPLR1_0_PCIE_LANE_ERROR_STATUS 0x0278 |
| #define cfgBIFPLR1_0_PCIE_LANE_0_EQUALIZATION_CNTL 0x027c |
| #define cfgBIFPLR1_0_PCIE_LANE_1_EQUALIZATION_CNTL 0x027e |
| #define cfgBIFPLR1_0_PCIE_LANE_2_EQUALIZATION_CNTL 0x0280 |
| #define cfgBIFPLR1_0_PCIE_LANE_3_EQUALIZATION_CNTL 0x0282 |
| #define cfgBIFPLR1_0_PCIE_LANE_4_EQUALIZATION_CNTL 0x0284 |
| #define cfgBIFPLR1_0_PCIE_LANE_5_EQUALIZATION_CNTL 0x0286 |
| #define cfgBIFPLR1_0_PCIE_LANE_6_EQUALIZATION_CNTL 0x0288 |
| #define cfgBIFPLR1_0_PCIE_LANE_7_EQUALIZATION_CNTL 0x028a |
| #define cfgBIFPLR1_0_PCIE_LANE_8_EQUALIZATION_CNTL 0x028c |
| #define cfgBIFPLR1_0_PCIE_LANE_9_EQUALIZATION_CNTL 0x028e |
| #define cfgBIFPLR1_0_PCIE_LANE_10_EQUALIZATION_CNTL 0x0290 |
| #define cfgBIFPLR1_0_PCIE_LANE_11_EQUALIZATION_CNTL 0x0292 |
| #define cfgBIFPLR1_0_PCIE_LANE_12_EQUALIZATION_CNTL 0x0294 |
| #define cfgBIFPLR1_0_PCIE_LANE_13_EQUALIZATION_CNTL 0x0296 |
| #define cfgBIFPLR1_0_PCIE_LANE_14_EQUALIZATION_CNTL 0x0298 |
| #define cfgBIFPLR1_0_PCIE_LANE_15_EQUALIZATION_CNTL 0x029a |
| #define cfgBIFPLR1_0_PCIE_ACS_ENH_CAP_LIST 0x02a0 |
| #define cfgBIFPLR1_0_PCIE_ACS_CAP 0x02a4 |
| #define cfgBIFPLR1_0_PCIE_ACS_CNTL 0x02a6 |
| #define cfgBIFPLR1_0_PCIE_MC_ENH_CAP_LIST 0x02f0 |
| #define cfgBIFPLR1_0_PCIE_MC_CAP 0x02f4 |
| #define cfgBIFPLR1_0_PCIE_MC_CNTL 0x02f6 |
| #define cfgBIFPLR1_0_PCIE_MC_ADDR0 0x02f8 |
| #define cfgBIFPLR1_0_PCIE_MC_ADDR1 0x02fc |
| #define cfgBIFPLR1_0_PCIE_MC_RCV0 0x0300 |
| #define cfgBIFPLR1_0_PCIE_MC_RCV1 0x0304 |
| #define cfgBIFPLR1_0_PCIE_MC_BLOCK_ALL0 0x0308 |
| #define cfgBIFPLR1_0_PCIE_MC_BLOCK_ALL1 0x030c |
| #define cfgBIFPLR1_0_PCIE_MC_BLOCK_UNTRANSLATED_0 0x0310 |
| #define cfgBIFPLR1_0_PCIE_MC_BLOCK_UNTRANSLATED_1 0x0314 |
| #define cfgBIFPLR1_0_PCIE_MC_OVERLAY_BAR0 0x0318 |
| #define cfgBIFPLR1_0_PCIE_MC_OVERLAY_BAR1 0x031c |
| #define cfgBIFPLR1_0_PCIE_L1_PM_SUB_CAP_LIST 0x0370 |
| #define cfgBIFPLR1_0_PCIE_L1_PM_SUB_CAP 0x0374 |
| #define cfgBIFPLR1_0_PCIE_L1_PM_SUB_CNTL 0x0378 |
| #define cfgBIFPLR1_0_PCIE_L1_PM_SUB_CNTL2 0x037c |
| #define cfgBIFPLR1_0_PCIE_DPC_ENH_CAP_LIST 0x0380 |
| #define cfgBIFPLR1_0_PCIE_DPC_CAP_LIST 0x0384 |
| #define cfgBIFPLR1_0_PCIE_DPC_CNTL 0x0386 |
| #define cfgBIFPLR1_0_PCIE_DPC_STATUS 0x0388 |
| #define cfgBIFPLR1_0_PCIE_DPC_ERROR_SOURCE_ID 0x038a |
| #define cfgBIFPLR1_0_PCIE_RP_PIO_STATUS 0x038c |
| #define cfgBIFPLR1_0_PCIE_RP_PIO_MASK 0x0390 |
| #define cfgBIFPLR1_0_PCIE_RP_PIO_SEVERITY 0x0394 |
| #define cfgBIFPLR1_0_PCIE_RP_PIO_SYSERROR 0x0398 |
| #define cfgBIFPLR1_0_PCIE_RP_PIO_EXCEPTION 0x039c |
| #define cfgBIFPLR1_0_PCIE_RP_PIO_HDR_LOG0 0x03a0 |
| #define cfgBIFPLR1_0_PCIE_RP_PIO_HDR_LOG1 0x03a4 |
| #define cfgBIFPLR1_0_PCIE_RP_PIO_HDR_LOG2 0x03a8 |
| #define cfgBIFPLR1_0_PCIE_RP_PIO_HDR_LOG3 0x03ac |
| #define cfgBIFPLR1_0_PCIE_RP_PIO_IMPSPEC_LOG 0x03b0 |
| #define cfgBIFPLR1_0_PCIE_RP_PIO_PREFIX_LOG0 0x03b4 |
| #define cfgBIFPLR1_0_PCIE_RP_PIO_PREFIX_LOG1 0x03b8 |
| #define cfgBIFPLR1_0_PCIE_RP_PIO_PREFIX_LOG2 0x03bc |
| #define cfgBIFPLR1_0_PCIE_RP_PIO_PREFIX_LOG3 0x03c0 |
| #define cfgBIFPLR1_0_PCIE_ESM_CAP_LIST 0x03c4 |
| #define cfgBIFPLR1_0_PCIE_ESM_HEADER_1 0x03c8 |
| #define cfgBIFPLR1_0_PCIE_ESM_HEADER_2 0x03cc |
| #define cfgBIFPLR1_0_PCIE_ESM_STATUS 0x03ce |
| #define cfgBIFPLR1_0_PCIE_ESM_CTRL 0x03d0 |
| #define cfgBIFPLR1_0_PCIE_ESM_CAP_1 0x03d4 |
| #define cfgBIFPLR1_0_PCIE_ESM_CAP_2 0x03d8 |
| #define cfgBIFPLR1_0_PCIE_ESM_CAP_3 0x03dc |
| #define cfgBIFPLR1_0_PCIE_ESM_CAP_4 0x03e0 |
| #define cfgBIFPLR1_0_PCIE_ESM_CAP_5 0x03e4 |
| #define cfgBIFPLR1_0_PCIE_ESM_CAP_6 0x03e8 |
| #define cfgBIFPLR1_0_PCIE_ESM_CAP_7 0x03ec |
| |
| |
| // addressBlock: nbio_pcie0_bifplr2_cfgdecp |
| // base address: 0x0 |
| #define cfgBIFPLR2_0_VENDOR_ID 0x0000 |
| #define cfgBIFPLR2_0_DEVICE_ID 0x0002 |
| #define cfgBIFPLR2_0_COMMAND 0x0004 |
| #define cfgBIFPLR2_0_STATUS 0x0006 |
| #define cfgBIFPLR2_0_REVISION_ID 0x0008 |
| #define cfgBIFPLR2_0_PROG_INTERFACE 0x0009 |
| #define cfgBIFPLR2_0_SUB_CLASS 0x000a |
| #define cfgBIFPLR2_0_BASE_CLASS 0x000b |
| #define cfgBIFPLR2_0_CACHE_LINE 0x000c |
| #define cfgBIFPLR2_0_LATENCY 0x000d |
| #define cfgBIFPLR2_0_HEADER 0x000e |
| #define cfgBIFPLR2_0_BIST 0x000f |
| #define cfgBIFPLR2_0_SUB_BUS_NUMBER_LATENCY 0x0018 |
| #define cfgBIFPLR2_0_IO_BASE_LIMIT 0x001c |
| #define cfgBIFPLR2_0_SECONDARY_STATUS 0x001e |
| #define cfgBIFPLR2_0_MEM_BASE_LIMIT 0x0020 |
| #define cfgBIFPLR2_0_PREF_BASE_LIMIT 0x0024 |
| #define cfgBIFPLR2_0_PREF_BASE_UPPER 0x0028 |
| #define cfgBIFPLR2_0_PREF_LIMIT_UPPER 0x002c |
| #define cfgBIFPLR2_0_IO_BASE_LIMIT_HI 0x0030 |
| #define cfgBIFPLR2_0_CAP_PTR 0x0034 |
| #define cfgBIFPLR2_0_INTERRUPT_LINE 0x003c |
| #define cfgBIFPLR2_0_INTERRUPT_PIN 0x003d |
| #define cfgBIFPLR2_0_IRQ_BRIDGE_CNTL 0x003e |
| #define cfgBIFPLR2_0_EXT_BRIDGE_CNTL 0x0040 |
| #define cfgBIFPLR2_0_PMI_CAP_LIST 0x0050 |
| #define cfgBIFPLR2_0_PMI_CAP 0x0052 |
| #define cfgBIFPLR2_0_PMI_STATUS_CNTL 0x0054 |
| #define cfgBIFPLR2_0_PCIE_CAP_LIST 0x0058 |
| #define cfgBIFPLR2_0_PCIE_CAP 0x005a |
| #define cfgBIFPLR2_0_DEVICE_CAP 0x005c |
| #define cfgBIFPLR2_0_DEVICE_CNTL 0x0060 |
| #define cfgBIFPLR2_0_DEVICE_STATUS 0x0062 |
| #define cfgBIFPLR2_0_LINK_CAP 0x0064 |
| #define cfgBIFPLR2_0_LINK_CNTL 0x0068 |
| #define cfgBIFPLR2_0_LINK_STATUS 0x006a |
| #define cfgBIFPLR2_0_SLOT_CAP 0x006c |
| #define cfgBIFPLR2_0_SLOT_CNTL 0x0070 |
| #define cfgBIFPLR2_0_SLOT_STATUS 0x0072 |
| #define cfgBIFPLR2_0_ROOT_CNTL 0x0074 |
| #define cfgBIFPLR2_0_ROOT_CAP 0x0076 |
| #define cfgBIFPLR2_0_ROOT_STATUS 0x0078 |
| #define cfgBIFPLR2_0_DEVICE_CAP2 0x007c |
| #define cfgBIFPLR2_0_DEVICE_CNTL2 0x0080 |
| #define cfgBIFPLR2_0_DEVICE_STATUS2 0x0082 |
| #define cfgBIFPLR2_0_LINK_CAP2 0x0084 |
| #define cfgBIFPLR2_0_LINK_CNTL2 0x0088 |
| #define cfgBIFPLR2_0_LINK_STATUS2 0x008a |
| #define cfgBIFPLR2_0_SLOT_CAP2 0x008c |
| #define cfgBIFPLR2_0_SLOT_CNTL2 0x0090 |
| #define cfgBIFPLR2_0_SLOT_STATUS2 0x0092 |
| #define cfgBIFPLR2_0_MSI_CAP_LIST 0x00a0 |
| #define cfgBIFPLR2_0_MSI_MSG_CNTL 0x00a2 |
| #define cfgBIFPLR2_0_MSI_MSG_ADDR_LO 0x00a4 |
| #define cfgBIFPLR2_0_MSI_MSG_ADDR_HI 0x00a8 |
| #define cfgBIFPLR2_0_MSI_MSG_DATA 0x00a8 |
| #define cfgBIFPLR2_0_MSI_MSG_DATA_64 0x00ac |
| #define cfgBIFPLR2_0_SSID_CAP_LIST 0x00c0 |
| #define cfgBIFPLR2_0_SSID_CAP 0x00c4 |
| #define cfgBIFPLR2_0_MSI_MAP_CAP_LIST 0x00c8 |
| #define cfgBIFPLR2_0_MSI_MAP_CAP 0x00ca |
| #define cfgBIFPLR2_0_MSI_MAP_ADDR_LO 0x00cc |
| #define cfgBIFPLR2_0_MSI_MAP_ADDR_HI 0x00d0 |
| #define cfgBIFPLR2_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x0100 |
| #define cfgBIFPLR2_0_PCIE_VENDOR_SPECIFIC_HDR 0x0104 |
| #define cfgBIFPLR2_0_PCIE_VENDOR_SPECIFIC1 0x0108 |
| #define cfgBIFPLR2_0_PCIE_VENDOR_SPECIFIC2 0x010c |
| #define cfgBIFPLR2_0_PCIE_VC_ENH_CAP_LIST 0x0110 |
| #define cfgBIFPLR2_0_PCIE_PORT_VC_CAP_REG1 0x0114 |
| #define cfgBIFPLR2_0_PCIE_PORT_VC_CAP_REG2 0x0118 |
| #define cfgBIFPLR2_0_PCIE_PORT_VC_CNTL 0x011c |
| #define cfgBIFPLR2_0_PCIE_PORT_VC_STATUS 0x011e |
| #define cfgBIFPLR2_0_PCIE_VC0_RESOURCE_CAP 0x0120 |
| #define cfgBIFPLR2_0_PCIE_VC0_RESOURCE_CNTL 0x0124 |
| #define cfgBIFPLR2_0_PCIE_VC0_RESOURCE_STATUS 0x012a |
| #define cfgBIFPLR2_0_PCIE_VC1_RESOURCE_CAP 0x012c |
| #define cfgBIFPLR2_0_PCIE_VC1_RESOURCE_CNTL 0x0130 |
| #define cfgBIFPLR2_0_PCIE_VC1_RESOURCE_STATUS 0x0136 |
| #define cfgBIFPLR2_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST 0x0140 |
| #define cfgBIFPLR2_0_PCIE_DEV_SERIAL_NUM_DW1 0x0144 |
| #define cfgBIFPLR2_0_PCIE_DEV_SERIAL_NUM_DW2 0x0148 |
| #define cfgBIFPLR2_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x0150 |
| #define cfgBIFPLR2_0_PCIE_UNCORR_ERR_STATUS 0x0154 |
| #define cfgBIFPLR2_0_PCIE_UNCORR_ERR_MASK 0x0158 |
| #define cfgBIFPLR2_0_PCIE_UNCORR_ERR_SEVERITY 0x015c |
| #define cfgBIFPLR2_0_PCIE_CORR_ERR_STATUS 0x0160 |
| #define cfgBIFPLR2_0_PCIE_CORR_ERR_MASK 0x0164 |
| #define cfgBIFPLR2_0_PCIE_ADV_ERR_CAP_CNTL 0x0168 |
| #define cfgBIFPLR2_0_PCIE_HDR_LOG0 0x016c |
| #define cfgBIFPLR2_0_PCIE_HDR_LOG1 0x0170 |
| #define cfgBIFPLR2_0_PCIE_HDR_LOG2 0x0174 |
| #define cfgBIFPLR2_0_PCIE_HDR_LOG3 0x0178 |
| #define cfgBIFPLR2_0_PCIE_ROOT_ERR_CMD 0x017c |
| #define cfgBIFPLR2_0_PCIE_ROOT_ERR_STATUS 0x0180 |
| #define cfgBIFPLR2_0_PCIE_ERR_SRC_ID 0x0184 |
| #define cfgBIFPLR2_0_PCIE_TLP_PREFIX_LOG0 0x0188 |
| #define cfgBIFPLR2_0_PCIE_TLP_PREFIX_LOG1 0x018c |
| #define cfgBIFPLR2_0_PCIE_TLP_PREFIX_LOG2 0x0190 |
| #define cfgBIFPLR2_0_PCIE_TLP_PREFIX_LOG3 0x0194 |
| #define cfgBIFPLR2_0_PCIE_SECONDARY_ENH_CAP_LIST 0x0270 |
| #define cfgBIFPLR2_0_PCIE_LINK_CNTL3 0x0274 |
| #define cfgBIFPLR2_0_PCIE_LANE_ERROR_STATUS 0x0278 |
| #define cfgBIFPLR2_0_PCIE_LANE_0_EQUALIZATION_CNTL 0x027c |
| #define cfgBIFPLR2_0_PCIE_LANE_1_EQUALIZATION_CNTL 0x027e |
| #define cfgBIFPLR2_0_PCIE_LANE_2_EQUALIZATION_CNTL 0x0280 |
| #define cfgBIFPLR2_0_PCIE_LANE_3_EQUALIZATION_CNTL 0x0282 |
| #define cfgBIFPLR2_0_PCIE_LANE_4_EQUALIZATION_CNTL 0x0284 |
| #define cfgBIFPLR2_0_PCIE_LANE_5_EQUALIZATION_CNTL 0x0286 |
| #define cfgBIFPLR2_0_PCIE_LANE_6_EQUALIZATION_CNTL 0x0288 |
| #define cfgBIFPLR2_0_PCIE_LANE_7_EQUALIZATION_CNTL 0x028a |
| #define cfgBIFPLR2_0_PCIE_LANE_8_EQUALIZATION_CNTL 0x028c |
| #define cfgBIFPLR2_0_PCIE_LANE_9_EQUALIZATION_CNTL 0x028e |
| #define cfgBIFPLR2_0_PCIE_LANE_10_EQUALIZATION_CNTL 0x0290 |
| #define cfgBIFPLR2_0_PCIE_LANE_11_EQUALIZATION_CNTL 0x0292 |
| #define cfgBIFPLR2_0_PCIE_LANE_12_EQUALIZATION_CNTL 0x0294 |
| #define cfgBIFPLR2_0_PCIE_LANE_13_EQUALIZATION_CNTL 0x0296 |
| #define cfgBIFPLR2_0_PCIE_LANE_14_EQUALIZATION_CNTL 0x0298 |
| #define cfgBIFPLR2_0_PCIE_LANE_15_EQUALIZATION_CNTL 0x029a |
| #define cfgBIFPLR2_0_PCIE_ACS_ENH_CAP_LIST 0x02a0 |
| #define cfgBIFPLR2_0_PCIE_ACS_CAP 0x02a4 |
| #define cfgBIFPLR2_0_PCIE_ACS_CNTL 0x02a6 |
| #define cfgBIFPLR2_0_PCIE_MC_ENH_CAP_LIST 0x02f0 |
| #define cfgBIFPLR2_0_PCIE_MC_CAP 0x02f4 |
| #define cfgBIFPLR2_0_PCIE_MC_CNTL 0x02f6 |
| #define cfgBIFPLR2_0_PCIE_MC_ADDR0 0x02f8 |
| #define cfgBIFPLR2_0_PCIE_MC_ADDR1 0x02fc |
| #define cfgBIFPLR2_0_PCIE_MC_RCV0 0x0300 |
| #define cfgBIFPLR2_0_PCIE_MC_RCV1 0x0304 |
| #define cfgBIFPLR2_0_PCIE_MC_BLOCK_ALL0 0x0308 |
| #define cfgBIFPLR2_0_PCIE_MC_BLOCK_ALL1 0x030c |
| #define cfgBIFPLR2_0_PCIE_MC_BLOCK_UNTRANSLATED_0 0x0310 |
| #define cfgBIFPLR2_0_PCIE_MC_BLOCK_UNTRANSLATED_1 0x0314 |
| #define cfgBIFPLR2_0_PCIE_MC_OVERLAY_BAR0 0x0318 |
| #define cfgBIFPLR2_0_PCIE_MC_OVERLAY_BAR1 0x031c |
| #define cfgBIFPLR2_0_PCIE_L1_PM_SUB_CAP_LIST 0x0370 |
| #define cfgBIFPLR2_0_PCIE_L1_PM_SUB_CAP 0x0374 |
| #define cfgBIFPLR2_0_PCIE_L1_PM_SUB_CNTL 0x0378 |
| #define cfgBIFPLR2_0_PCIE_L1_PM_SUB_CNTL2 0x037c |
| #define cfgBIFPLR2_0_PCIE_DPC_ENH_CAP_LIST 0x0380 |
| #define cfgBIFPLR2_0_PCIE_DPC_CAP_LIST 0x0384 |
| #define cfgBIFPLR2_0_PCIE_DPC_CNTL 0x0386 |
| #define cfgBIFPLR2_0_PCIE_DPC_STATUS 0x0388 |
| #define cfgBIFPLR2_0_PCIE_DPC_ERROR_SOURCE_ID 0x038a |
| #define cfgBIFPLR2_0_PCIE_RP_PIO_STATUS 0x038c |
| #define cfgBIFPLR2_0_PCIE_RP_PIO_MASK 0x0390 |
| #define cfgBIFPLR2_0_PCIE_RP_PIO_SEVERITY 0x0394 |
| #define cfgBIFPLR2_0_PCIE_RP_PIO_SYSERROR 0x0398 |
| #define cfgBIFPLR2_0_PCIE_RP_PIO_EXCEPTION 0x039c |
| #define cfgBIFPLR2_0_PCIE_RP_PIO_HDR_LOG0 0x03a0 |
| #define cfgBIFPLR2_0_PCIE_RP_PIO_HDR_LOG1 0x03a4 |
| #define cfgBIFPLR2_0_PCIE_RP_PIO_HDR_LOG2 0x03a8 |
| #define cfgBIFPLR2_0_PCIE_RP_PIO_HDR_LOG3 0x03ac |
| #define cfgBIFPLR2_0_PCIE_RP_PIO_IMPSPEC_LOG 0x03b0 |
| #define cfgBIFPLR2_0_PCIE_RP_PIO_PREFIX_LOG0 0x03b4 |
| #define cfgBIFPLR2_0_PCIE_RP_PIO_PREFIX_LOG1 0x03b8 |
| #define cfgBIFPLR2_0_PCIE_RP_PIO_PREFIX_LOG2 0x03bc |
| #define cfgBIFPLR2_0_PCIE_RP_PIO_PREFIX_LOG3 0x03c0 |
| #define cfgBIFPLR2_0_PCIE_ESM_CAP_LIST 0x03c4 |
| #define cfgBIFPLR2_0_PCIE_ESM_HEADER_1 0x03c8 |
| #define cfgBIFPLR2_0_PCIE_ESM_HEADER_2 0x03cc |
| #define cfgBIFPLR2_0_PCIE_ESM_STATUS 0x03ce |
| #define cfgBIFPLR2_0_PCIE_ESM_CTRL 0x03d0 |
| #define cfgBIFPLR2_0_PCIE_ESM_CAP_1 0x03d4 |
| #define cfgBIFPLR2_0_PCIE_ESM_CAP_2 0x03d8 |
| #define cfgBIFPLR2_0_PCIE_ESM_CAP_3 0x03dc |
| #define cfgBIFPLR2_0_PCIE_ESM_CAP_4 0x03e0 |
| #define cfgBIFPLR2_0_PCIE_ESM_CAP_5 0x03e4 |
| #define cfgBIFPLR2_0_PCIE_ESM_CAP_6 0x03e8 |
| #define cfgBIFPLR2_0_PCIE_ESM_CAP_7 0x03ec |
| |
| |
| // addressBlock: nbio_pcie0_bifplr3_cfgdecp |
| // base address: 0x0 |
| #define cfgBIFPLR3_0_VENDOR_ID 0x0000 |
| #define cfgBIFPLR3_0_DEVICE_ID 0x0002 |
| #define cfgBIFPLR3_0_COMMAND 0x0004 |
| #define cfgBIFPLR3_0_STATUS 0x0006 |
| #define cfgBIFPLR3_0_REVISION_ID 0x0008 |
| #define cfgBIFPLR3_0_PROG_INTERFACE 0x0009 |
| #define cfgBIFPLR3_0_SUB_CLASS 0x000a |
| #define cfgBIFPLR3_0_BASE_CLASS 0x000b |
| #define cfgBIFPLR3_0_CACHE_LINE 0x000c |
| #define cfgBIFPLR3_0_LATENCY 0x000d |
| #define cfgBIFPLR3_0_HEADER 0x000e |
| #define cfgBIFPLR3_0_BIST 0x000f |
| #define cfgBIFPLR3_0_SUB_BUS_NUMBER_LATENCY 0x0018 |
| #define cfgBIFPLR3_0_IO_BASE_LIMIT 0x001c |
| #define cfgBIFPLR3_0_SECONDARY_STATUS 0x001e |
| #define cfgBIFPLR3_0_MEM_BASE_LIMIT 0x0020 |
| #define cfgBIFPLR3_0_PREF_BASE_LIMIT 0x0024 |
| #define cfgBIFPLR3_0_PREF_BASE_UPPER 0x0028 |
| #define cfgBIFPLR3_0_PREF_LIMIT_UPPER 0x002c |
| #define cfgBIFPLR3_0_IO_BASE_LIMIT_HI 0x0030 |
| #define cfgBIFPLR3_0_CAP_PTR 0x0034 |
| #define cfgBIFPLR3_0_INTERRUPT_LINE 0x003c |
| #define cfgBIFPLR3_0_INTERRUPT_PIN 0x003d |
| #define cfgBIFPLR3_0_IRQ_BRIDGE_CNTL 0x003e |
| #define cfgBIFPLR3_0_EXT_BRIDGE_CNTL 0x0040 |
| #define cfgBIFPLR3_0_PMI_CAP_LIST 0x0050 |
| #define cfgBIFPLR3_0_PMI_CAP 0x0052 |
| #define cfgBIFPLR3_0_PMI_STATUS_CNTL 0x0054 |
| #define cfgBIFPLR3_0_PCIE_CAP_LIST 0x0058 |
| #define cfgBIFPLR3_0_PCIE_CAP 0x005a |
| #define cfgBIFPLR3_0_DEVICE_CAP 0x005c |
| #define cfgBIFPLR3_0_DEVICE_CNTL 0x0060 |
| #define cfgBIFPLR3_0_DEVICE_STATUS 0x0062 |
| #define cfgBIFPLR3_0_LINK_CAP 0x0064 |
| #define cfgBIFPLR3_0_LINK_CNTL 0x0068 |
| #define cfgBIFPLR3_0_LINK_STATUS 0x006a |
| #define cfgBIFPLR3_0_SLOT_CAP 0x006c |
| #define cfgBIFPLR3_0_SLOT_CNTL 0x0070 |
| #define cfgBIFPLR3_0_SLOT_STATUS 0x0072 |
| #define cfgBIFPLR3_0_ROOT_CNTL 0x0074 |
| #define cfgBIFPLR3_0_ROOT_CAP 0x0076 |
| #define cfgBIFPLR3_0_ROOT_STATUS 0x0078 |
| #define cfgBIFPLR3_0_DEVICE_CAP2 0x007c |
| #define cfgBIFPLR3_0_DEVICE_CNTL2 0x0080 |
| #define cfgBIFPLR3_0_DEVICE_STATUS2 0x0082 |
| #define cfgBIFPLR3_0_LINK_CAP2 0x0084 |
| #define cfgBIFPLR3_0_LINK_CNTL2 0x0088 |
| #define cfgBIFPLR3_0_LINK_STATUS2 0x008a |
| #define cfgBIFPLR3_0_SLOT_CAP2 0x008c |
| #define cfgBIFPLR3_0_SLOT_CNTL2 0x0090 |
| #define cfgBIFPLR3_0_SLOT_STATUS2 0x0092 |
| #define cfgBIFPLR3_0_MSI_CAP_LIST 0x00a0 |
| #define cfgBIFPLR3_0_MSI_MSG_CNTL 0x00a2 |
| #define cfgBIFPLR3_0_MSI_MSG_ADDR_LO 0x00a4 |
| #define cfgBIFPLR3_0_MSI_MSG_ADDR_HI 0x00a8 |
| #define cfgBIFPLR3_0_MSI_MSG_DATA 0x00a8 |
| #define cfgBIFPLR3_0_MSI_MSG_DATA_64 0x00ac |
| #define cfgBIFPLR3_0_SSID_CAP_LIST 0x00c0 |
| #define cfgBIFPLR3_0_SSID_CAP 0x00c4 |
| #define cfgBIFPLR3_0_MSI_MAP_CAP_LIST 0x00c8 |
| #define cfgBIFPLR3_0_MSI_MAP_CAP 0x00ca |
| #define cfgBIFPLR3_0_MSI_MAP_ADDR_LO 0x00cc |
| #define cfgBIFPLR3_0_MSI_MAP_ADDR_HI 0x00d0 |
| #define cfgBIFPLR3_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x0100 |
| #define cfgBIFPLR3_0_PCIE_VENDOR_SPECIFIC_HDR 0x0104 |
| #define cfgBIFPLR3_0_PCIE_VENDOR_SPECIFIC1 0x0108 |
| #define cfgBIFPLR3_0_PCIE_VENDOR_SPECIFIC2 0x010c |
| #define cfgBIFPLR3_0_PCIE_VC_ENH_CAP_LIST 0x0110 |
| #define cfgBIFPLR3_0_PCIE_PORT_VC_CAP_REG1 0x0114 |
| #define cfgBIFPLR3_0_PCIE_PORT_VC_CAP_REG2 0x0118 |
| #define cfgBIFPLR3_0_PCIE_PORT_VC_CNTL 0x011c |
| #define cfgBIFPLR3_0_PCIE_PORT_VC_STATUS 0x011e |
| #define cfgBIFPLR3_0_PCIE_VC0_RESOURCE_CAP 0x0120 |
| #define cfgBIFPLR3_0_PCIE_VC0_RESOURCE_CNTL 0x0124 |
| #define cfgBIFPLR3_0_PCIE_VC0_RESOURCE_STATUS 0x012a |
| #define cfgBIFPLR3_0_PCIE_VC1_RESOURCE_CAP 0x012c |
| #define cfgBIFPLR3_0_PCIE_VC1_RESOURCE_CNTL 0x0130 |
| #define cfgBIFPLR3_0_PCIE_VC1_RESOURCE_STATUS 0x0136 |
| #define cfgBIFPLR3_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST 0x0140 |
| #define cfgBIFPLR3_0_PCIE_DEV_SERIAL_NUM_DW1 0x0144 |
| #define cfgBIFPLR3_0_PCIE_DEV_SERIAL_NUM_DW2 0x0148 |
| #define cfgBIFPLR3_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x0150 |
| #define cfgBIFPLR3_0_PCIE_UNCORR_ERR_STATUS 0x0154 |
| #define cfgBIFPLR3_0_PCIE_UNCORR_ERR_MASK 0x0158 |
| #define cfgBIFPLR3_0_PCIE_UNCORR_ERR_SEVERITY 0x015c |
| #define cfgBIFPLR3_0_PCIE_CORR_ERR_STATUS 0x0160 |
| #define cfgBIFPLR3_0_PCIE_CORR_ERR_MASK 0x0164 |
| #define cfgBIFPLR3_0_PCIE_ADV_ERR_CAP_CNTL 0x0168 |
| #define cfgBIFPLR3_0_PCIE_HDR_LOG0 0x016c |
| #define cfgBIFPLR3_0_PCIE_HDR_LOG1 0x0170 |
| #define cfgBIFPLR3_0_PCIE_HDR_LOG2 0x0174 |
| #define cfgBIFPLR3_0_PCIE_HDR_LOG3 0x0178 |
| #define cfgBIFPLR3_0_PCIE_ROOT_ERR_CMD 0x017c |
| #define cfgBIFPLR3_0_PCIE_ROOT_ERR_STATUS 0x0180 |
| #define cfgBIFPLR3_0_PCIE_ERR_SRC_ID 0x0184 |
| #define cfgBIFPLR3_0_PCIE_TLP_PREFIX_LOG0 0x0188 |
| #define cfgBIFPLR3_0_PCIE_TLP_PREFIX_LOG1 0x018c |
| #define cfgBIFPLR3_0_PCIE_TLP_PREFIX_LOG2 0x0190 |
| #define cfgBIFPLR3_0_PCIE_TLP_PREFIX_LOG3 0x0194 |
| #define cfgBIFPLR3_0_PCIE_SECONDARY_ENH_CAP_LIST 0x0270 |
| #define cfgBIFPLR3_0_PCIE_LINK_CNTL3 0x0274 |
| #define cfgBIFPLR3_0_PCIE_LANE_ERROR_STATUS 0x0278 |
| #define cfgBIFPLR3_0_PCIE_LANE_0_EQUALIZATION_CNTL 0x027c |
| #define cfgBIFPLR3_0_PCIE_LANE_1_EQUALIZATION_CNTL 0x027e |
| #define cfgBIFPLR3_0_PCIE_LANE_2_EQUALIZATION_CNTL 0x0280 |
| #define cfgBIFPLR3_0_PCIE_LANE_3_EQUALIZATION_CNTL 0x0282 |
| #define cfgBIFPLR3_0_PCIE_LANE_4_EQUALIZATION_CNTL 0x0284 |
| #define cfgBIFPLR3_0_PCIE_LANE_5_EQUALIZATION_CNTL 0x0286 |
| #define cfgBIFPLR3_0_PCIE_LANE_6_EQUALIZATION_CNTL 0x0288 |
| #define cfgBIFPLR3_0_PCIE_LANE_7_EQUALIZATION_CNTL 0x028a |
| #define cfgBIFPLR3_0_PCIE_LANE_8_EQUALIZATION_CNTL 0x028c |
| #define cfgBIFPLR3_0_PCIE_LANE_9_EQUALIZATION_CNTL 0x028e |
| #define cfgBIFPLR3_0_PCIE_LANE_10_EQUALIZATION_CNTL 0x0290 |
| #define cfgBIFPLR3_0_PCIE_LANE_11_EQUALIZATION_CNTL 0x0292 |
| #define cfgBIFPLR3_0_PCIE_LANE_12_EQUALIZATION_CNTL 0x0294 |
| #define cfgBIFPLR3_0_PCIE_LANE_13_EQUALIZATION_CNTL 0x0296 |
| #define cfgBIFPLR3_0_PCIE_LANE_14_EQUALIZATION_CNTL 0x0298 |
| #define cfgBIFPLR3_0_PCIE_LANE_15_EQUALIZATION_CNTL 0x029a |
| #define cfgBIFPLR3_0_PCIE_ACS_ENH_CAP_LIST 0x02a0 |
| #define cfgBIFPLR3_0_PCIE_ACS_CAP 0x02a4 |
| #define cfgBIFPLR3_0_PCIE_ACS_CNTL 0x02a6 |
| #define cfgBIFPLR3_0_PCIE_MC_ENH_CAP_LIST 0x02f0 |
| #define cfgBIFPLR3_0_PCIE_MC_CAP 0x02f4 |
| #define cfgBIFPLR3_0_PCIE_MC_CNTL 0x02f6 |
| #define cfgBIFPLR3_0_PCIE_MC_ADDR0 0x02f8 |
| #define cfgBIFPLR3_0_PCIE_MC_ADDR1 0x02fc |
| #define cfgBIFPLR3_0_PCIE_MC_RCV0 0x0300 |
| #define cfgBIFPLR3_0_PCIE_MC_RCV1 0x0304 |
| #define cfgBIFPLR3_0_PCIE_MC_BLOCK_ALL0 0x0308 |
| #define cfgBIFPLR3_0_PCIE_MC_BLOCK_ALL1 0x030c |
| #define cfgBIFPLR3_0_PCIE_MC_BLOCK_UNTRANSLATED_0 0x0310 |
| #define cfgBIFPLR3_0_PCIE_MC_BLOCK_UNTRANSLATED_1 0x0314 |
| #define cfgBIFPLR3_0_PCIE_MC_OVERLAY_BAR0 0x0318 |
| #define cfgBIFPLR3_0_PCIE_MC_OVERLAY_BAR1 0x031c |
| #define cfgBIFPLR3_0_PCIE_L1_PM_SUB_CAP_LIST 0x0370 |
| #define cfgBIFPLR3_0_PCIE_L1_PM_SUB_CAP 0x0374 |
| #define cfgBIFPLR3_0_PCIE_L1_PM_SUB_CNTL 0x0378 |
| #define cfgBIFPLR3_0_PCIE_L1_PM_SUB_CNTL2 0x037c |
| #define cfgBIFPLR3_0_PCIE_DPC_ENH_CAP_LIST 0x0380 |
| #define cfgBIFPLR3_0_PCIE_DPC_CAP_LIST 0x0384 |
| #define cfgBIFPLR3_0_PCIE_DPC_CNTL 0x0386 |
| #define cfgBIFPLR3_0_PCIE_DPC_STATUS 0x0388 |
| #define cfgBIFPLR3_0_PCIE_DPC_ERROR_SOURCE_ID 0x038a |
| #define cfgBIFPLR3_0_PCIE_RP_PIO_STATUS 0x038c |
| #define cfgBIFPLR3_0_PCIE_RP_PIO_MASK 0x0390 |
| #define cfgBIFPLR3_0_PCIE_RP_PIO_SEVERITY 0x0394 |
| #define cfgBIFPLR3_0_PCIE_RP_PIO_SYSERROR 0x0398 |
| #define cfgBIFPLR3_0_PCIE_RP_PIO_EXCEPTION 0x039c |
| #define cfgBIFPLR3_0_PCIE_RP_PIO_HDR_LOG0 0x03a0 |
| #define cfgBIFPLR3_0_PCIE_RP_PIO_HDR_LOG1 0x03a4 |
| #define cfgBIFPLR3_0_PCIE_RP_PIO_HDR_LOG2 0x03a8 |
| #define cfgBIFPLR3_0_PCIE_RP_PIO_HDR_LOG3 0x03ac |
| #define cfgBIFPLR3_0_PCIE_RP_PIO_IMPSPEC_LOG 0x03b0 |
| #define cfgBIFPLR3_0_PCIE_RP_PIO_PREFIX_LOG0 0x03b4 |
| #define cfgBIFPLR3_0_PCIE_RP_PIO_PREFIX_LOG1 0x03b8 |
| #define cfgBIFPLR3_0_PCIE_RP_PIO_PREFIX_LOG2 0x03bc |
| #define cfgBIFPLR3_0_PCIE_RP_PIO_PREFIX_LOG3 0x03c0 |
| #define cfgBIFPLR3_0_PCIE_ESM_CAP_LIST 0x03c4 |
| #define cfgBIFPLR3_0_PCIE_ESM_HEADER_1 0x03c8 |
| #define cfgBIFPLR3_0_PCIE_ESM_HEADER_2 0x03cc |
| #define cfgBIFPLR3_0_PCIE_ESM_STATUS 0x03ce |
| #define cfgBIFPLR3_0_PCIE_ESM_CTRL 0x03d0 |
| #define cfgBIFPLR3_0_PCIE_ESM_CAP_1 0x03d4 |
| #define cfgBIFPLR3_0_PCIE_ESM_CAP_2 0x03d8 |
| #define cfgBIFPLR3_0_PCIE_ESM_CAP_3 0x03dc |
| #define cfgBIFPLR3_0_PCIE_ESM_CAP_4 0x03e0 |
| #define cfgBIFPLR3_0_PCIE_ESM_CAP_5 0x03e4 |
| #define cfgBIFPLR3_0_PCIE_ESM_CAP_6 0x03e8 |
| #define cfgBIFPLR3_0_PCIE_ESM_CAP_7 0x03ec |
| |
| |
| // addressBlock: nbio_pcie0_bifplr4_cfgdecp |
| // base address: 0x0 |
| #define cfgBIFPLR4_0_VENDOR_ID 0x0000 |
| #define cfgBIFPLR4_0_DEVICE_ID 0x0002 |
| #define cfgBIFPLR4_0_COMMAND 0x0004 |
| #define cfgBIFPLR4_0_STATUS 0x0006 |
| #define cfgBIFPLR4_0_REVISION_ID 0x0008 |
| #define cfgBIFPLR4_0_PROG_INTERFACE 0x0009 |
| #define cfgBIFPLR4_0_SUB_CLASS 0x000a |
| #define cfgBIFPLR4_0_BASE_CLASS 0x000b |
| #define cfgBIFPLR4_0_CACHE_LINE 0x000c |
| #define cfgBIFPLR4_0_LATENCY 0x000d |
| #define cfgBIFPLR4_0_HEADER 0x000e |
| #define cfgBIFPLR4_0_BIST 0x000f |
| #define cfgBIFPLR4_0_SUB_BUS_NUMBER_LATENCY 0x0018 |
| #define cfgBIFPLR4_0_IO_BASE_LIMIT 0x001c |
| #define cfgBIFPLR4_0_SECONDARY_STATUS 0x001e |
| #define cfgBIFPLR4_0_MEM_BASE_LIMIT 0x0020 |
| #define cfgBIFPLR4_0_PREF_BASE_LIMIT 0x0024 |
| #define cfgBIFPLR4_0_PREF_BASE_UPPER 0x0028 |
| #define cfgBIFPLR4_0_PREF_LIMIT_UPPER 0x002c |
| #define cfgBIFPLR4_0_IO_BASE_LIMIT_HI 0x0030 |
| #define cfgBIFPLR4_0_CAP_PTR 0x0034 |
| #define cfgBIFPLR4_0_INTERRUPT_LINE 0x003c |
| #define cfgBIFPLR4_0_INTERRUPT_PIN 0x003d |
| #define cfgBIFPLR4_0_IRQ_BRIDGE_CNTL 0x003e |
| #define cfgBIFPLR4_0_EXT_BRIDGE_CNTL 0x0040 |
| #define cfgBIFPLR4_0_PMI_CAP_LIST 0x0050 |
| #define cfgBIFPLR4_0_PMI_CAP 0x0052 |
| #define cfgBIFPLR4_0_PMI_STATUS_CNTL 0x0054 |
| #define cfgBIFPLR4_0_PCIE_CAP_LIST 0x0058 |
| #define cfgBIFPLR4_0_PCIE_CAP 0x005a |
| #define cfgBIFPLR4_0_DEVICE_CAP 0x005c |
| #define cfgBIFPLR4_0_DEVICE_CNTL 0x0060 |
| #define cfgBIFPLR4_0_DEVICE_STATUS 0x0062 |
| #define cfgBIFPLR4_0_LINK_CAP 0x0064 |
| #define cfgBIFPLR4_0_LINK_CNTL 0x0068 |
| #define cfgBIFPLR4_0_LINK_STATUS 0x006a |
| #define cfgBIFPLR4_0_SLOT_CAP 0x006c |
| #define cfgBIFPLR4_0_SLOT_CNTL 0x0070 |
| #define cfgBIFPLR4_0_SLOT_STATUS 0x0072 |
| #define cfgBIFPLR4_0_ROOT_CNTL 0x0074 |
| #define cfgBIFPLR4_0_ROOT_CAP 0x0076 |
| #define cfgBIFPLR4_0_ROOT_STATUS 0x0078 |
| #define cfgBIFPLR4_0_DEVICE_CAP2 0x007c |
| #define cfgBIFPLR4_0_DEVICE_CNTL2 0x0080 |
| #define cfgBIFPLR4_0_DEVICE_STATUS2 0x0082 |
| #define cfgBIFPLR4_0_LINK_CAP2 0x0084 |
| #define cfgBIFPLR4_0_LINK_CNTL2 0x0088 |
| #define cfgBIFPLR4_0_LINK_STATUS2 0x008a |
| #define cfgBIFPLR4_0_SLOT_CAP2 0x008c |
| #define cfgBIFPLR4_0_SLOT_CNTL2 0x0090 |
| #define cfgBIFPLR4_0_SLOT_STATUS2 0x0092 |
| #define cfgBIFPLR4_0_MSI_CAP_LIST 0x00a0 |
| #define cfgBIFPLR4_0_MSI_MSG_CNTL 0x00a2 |
| #define cfgBIFPLR4_0_MSI_MSG_ADDR_LO 0x00a4 |
| #define cfgBIFPLR4_0_MSI_MSG_ADDR_HI 0x00a8 |
| #define cfgBIFPLR4_0_MSI_MSG_DATA 0x00a8 |
| #define cfgBIFPLR4_0_MSI_MSG_DATA_64 0x00ac |
| #define cfgBIFPLR4_0_SSID_CAP_LIST 0x00c0 |
| #define cfgBIFPLR4_0_SSID_CAP 0x00c4 |
| #define cfgBIFPLR4_0_MSI_MAP_CAP_LIST 0x00c8 |
| #define cfgBIFPLR4_0_MSI_MAP_CAP 0x00ca |
| #define cfgBIFPLR4_0_MSI_MAP_ADDR_LO 0x00cc |
| #define cfgBIFPLR4_0_MSI_MAP_ADDR_HI 0x00d0 |
| #define cfgBIFPLR4_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x0100 |
| #define cfgBIFPLR4_0_PCIE_VENDOR_SPECIFIC_HDR 0x0104 |
| #define cfgBIFPLR4_0_PCIE_VENDOR_SPECIFIC1 0x0108 |
| #define cfgBIFPLR4_0_PCIE_VENDOR_SPECIFIC2 0x010c |
| #define cfgBIFPLR4_0_PCIE_VC_ENH_CAP_LIST 0x0110 |
| #define cfgBIFPLR4_0_PCIE_PORT_VC_CAP_REG1 0x0114 |
| #define cfgBIFPLR4_0_PCIE_PORT_VC_CAP_REG2 0x0118 |
| #define cfgBIFPLR4_0_PCIE_PORT_VC_CNTL 0x011c |
| #define cfgBIFPLR4_0_PCIE_PORT_VC_STATUS 0x011e |
| #define cfgBIFPLR4_0_PCIE_VC0_RESOURCE_CAP 0x0120 |
| #define cfgBIFPLR4_0_PCIE_VC0_RESOURCE_CNTL 0x0124 |
| #define cfgBIFPLR4_0_PCIE_VC0_RESOURCE_STATUS 0x012a |
| #define cfgBIFPLR4_0_PCIE_VC1_RESOURCE_CAP 0x012c |
| #define cfgBIFPLR4_0_PCIE_VC1_RESOURCE_CNTL 0x0130 |
| #define cfgBIFPLR4_0_PCIE_VC1_RESOURCE_STATUS 0x0136 |
| #define cfgBIFPLR4_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST 0x0140 |
| #define cfgBIFPLR4_0_PCIE_DEV_SERIAL_NUM_DW1 0x0144 |
| #define cfgBIFPLR4_0_PCIE_DEV_SERIAL_NUM_DW2 0x0148 |
| #define cfgBIFPLR4_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x0150 |
| #define cfgBIFPLR4_0_PCIE_UNCORR_ERR_STATUS 0x0154 |
| #define cfgBIFPLR4_0_PCIE_UNCORR_ERR_MASK 0x0158 |
| #define cfgBIFPLR4_0_PCIE_UNCORR_ERR_SEVERITY 0x015c |
| #define cfgBIFPLR4_0_PCIE_CORR_ERR_STATUS 0x0160 |
| #define cfgBIFPLR4_0_PCIE_CORR_ERR_MASK 0x0164 |
| #define cfgBIFPLR4_0_PCIE_ADV_ERR_CAP_CNTL 0x0168 |
| #define cfgBIFPLR4_0_PCIE_HDR_LOG0 0x016c |
| #define cfgBIFPLR4_0_PCIE_HDR_LOG1 0x0170 |
| #define cfgBIFPLR4_0_PCIE_HDR_LOG2 0x0174 |
| #define cfgBIFPLR4_0_PCIE_HDR_LOG3 0x0178 |
| #define cfgBIFPLR4_0_PCIE_ROOT_ERR_CMD 0x017c |
| #define cfgBIFPLR4_0_PCIE_ROOT_ERR_STATUS 0x0180 |
| #define cfgBIFPLR4_0_PCIE_ERR_SRC_ID 0x0184 |
| #define cfgBIFPLR4_0_PCIE_TLP_PREFIX_LOG0 0x0188 |
| #define cfgBIFPLR4_0_PCIE_TLP_PREFIX_LOG1 0x018c |
| #define cfgBIFPLR4_0_PCIE_TLP_PREFIX_LOG2 0x0190 |
| #define cfgBIFPLR4_0_PCIE_TLP_PREFIX_LOG3 0x0194 |
| #define cfgBIFPLR4_0_PCIE_SECONDARY_ENH_CAP_LIST 0x0270 |
| #define cfgBIFPLR4_0_PCIE_LINK_CNTL3 0x0274 |
| #define cfgBIFPLR4_0_PCIE_LANE_ERROR_STATUS 0x0278 |
| #define cfgBIFPLR4_0_PCIE_LANE_0_EQUALIZATION_CNTL 0x027c |
| #define cfgBIFPLR4_0_PCIE_LANE_1_EQUALIZATION_CNTL 0x027e |
| #define cfgBIFPLR4_0_PCIE_LANE_2_EQUALIZATION_CNTL 0x0280 |
| #define cfgBIFPLR4_0_PCIE_LANE_3_EQUALIZATION_CNTL 0x0282 |
| #define cfgBIFPLR4_0_PCIE_LANE_4_EQUALIZATION_CNTL 0x0284 |
| #define cfgBIFPLR4_0_PCIE_LANE_5_EQUALIZATION_CNTL 0x0286 |
| #define cfgBIFPLR4_0_PCIE_LANE_6_EQUALIZATION_CNTL 0x0288 |
| #define cfgBIFPLR4_0_PCIE_LANE_7_EQUALIZATION_CNTL 0x028a |
| #define cfgBIFPLR4_0_PCIE_LANE_8_EQUALIZATION_CNTL 0x028c |
| #define cfgBIFPLR4_0_PCIE_LANE_9_EQUALIZATION_CNTL 0x028e |
| #define cfgBIFPLR4_0_PCIE_LANE_10_EQUALIZATION_CNTL 0x0290 |
| #define cfgBIFPLR4_0_PCIE_LANE_11_EQUALIZATION_CNTL 0x0292 |
| #define cfgBIFPLR4_0_PCIE_LANE_12_EQUALIZATION_CNTL 0x0294 |
| #define cfgBIFPLR4_0_PCIE_LANE_13_EQUALIZATION_CNTL 0x0296 |
| #define cfgBIFPLR4_0_PCIE_LANE_14_EQUALIZATION_CNTL 0x0298 |
| #define cfgBIFPLR4_0_PCIE_LANE_15_EQUALIZATION_CNTL 0x029a |
| #define cfgBIFPLR4_0_PCIE_ACS_ENH_CAP_LIST 0x02a0 |
| #define cfgBIFPLR4_0_PCIE_ACS_CAP 0x02a4 |
| #define cfgBIFPLR4_0_PCIE_ACS_CNTL 0x02a6 |
| #define cfgBIFPLR4_0_PCIE_MC_ENH_CAP_LIST 0x02f0 |
| #define cfgBIFPLR4_0_PCIE_MC_CAP 0x02f4 |
| #define cfgBIFPLR4_0_PCIE_MC_CNTL 0x02f6 |
| #define cfgBIFPLR4_0_PCIE_MC_ADDR0 0x02f8 |
| #define cfgBIFPLR4_0_PCIE_MC_ADDR1 0x02fc |
| #define cfgBIFPLR4_0_PCIE_MC_RCV0 0x0300 |
| #define cfgBIFPLR4_0_PCIE_MC_RCV1 0x0304 |
| #define cfgBIFPLR4_0_PCIE_MC_BLOCK_ALL0 0x0308 |
| #define cfgBIFPLR4_0_PCIE_MC_BLOCK_ALL1 0x030c |
| #define cfgBIFPLR4_0_PCIE_MC_BLOCK_UNTRANSLATED_0 0x0310 |
| #define cfgBIFPLR4_0_PCIE_MC_BLOCK_UNTRANSLATED_1 0x0314 |
| #define cfgBIFPLR4_0_PCIE_MC_OVERLAY_BAR0 0x0318 |
| #define cfgBIFPLR4_0_PCIE_MC_OVERLAY_BAR1 0x031c |
| #define cfgBIFPLR4_0_PCIE_L1_PM_SUB_CAP_LIST 0x0370 |
| #define cfgBIFPLR4_0_PCIE_L1_PM_SUB_CAP 0x0374 |
| #define cfgBIFPLR4_0_PCIE_L1_PM_SUB_CNTL 0x0378 |
| #define cfgBIFPLR4_0_PCIE_L1_PM_SUB_CNTL2 0x037c |
| #define cfgBIFPLR4_0_PCIE_DPC_ENH_CAP_LIST 0x0380 |
| #define cfgBIFPLR4_0_PCIE_DPC_CAP_LIST 0x0384 |
| #define cfgBIFPLR4_0_PCIE_DPC_CNTL 0x0386 |
| #define cfgBIFPLR4_0_PCIE_DPC_STATUS 0x0388 |
| #define cfgBIFPLR4_0_PCIE_DPC_ERROR_SOURCE_ID 0x038a |
| #define cfgBIFPLR4_0_PCIE_RP_PIO_STATUS 0x038c |
| #define cfgBIFPLR4_0_PCIE_RP_PIO_MASK 0x0390 |
| #define cfgBIFPLR4_0_PCIE_RP_PIO_SEVERITY 0x0394 |
| #define cfgBIFPLR4_0_PCIE_RP_PIO_SYSERROR 0x0398 |
| #define cfgBIFPLR4_0_PCIE_RP_PIO_EXCEPTION 0x039c |
| #define cfgBIFPLR4_0_PCIE_RP_PIO_HDR_LOG0 0x03a0 |
| #define cfgBIFPLR4_0_PCIE_RP_PIO_HDR_LOG1 0x03a4 |
| #define cfgBIFPLR4_0_PCIE_RP_PIO_HDR_LOG2 0x03a8 |
| #define cfgBIFPLR4_0_PCIE_RP_PIO_HDR_LOG3 0x03ac |
| #define cfgBIFPLR4_0_PCIE_RP_PIO_IMPSPEC_LOG 0x03b0 |
| #define cfgBIFPLR4_0_PCIE_RP_PIO_PREFIX_LOG0 0x03b4 |
| #define cfgBIFPLR4_0_PCIE_RP_PIO_PREFIX_LOG1 0x03b8 |
| #define cfgBIFPLR4_0_PCIE_RP_PIO_PREFIX_LOG2 0x03bc |
| #define cfgBIFPLR4_0_PCIE_RP_PIO_PREFIX_LOG3 0x03c0 |
| #define cfgBIFPLR4_0_PCIE_ESM_CAP_LIST 0x03c4 |
| #define cfgBIFPLR4_0_PCIE_ESM_HEADER_1 0x03c8 |
| #define cfgBIFPLR4_0_PCIE_ESM_HEADER_2 0x03cc |
| #define cfgBIFPLR4_0_PCIE_ESM_STATUS 0x03ce |
| #define cfgBIFPLR4_0_PCIE_ESM_CTRL 0x03d0 |
| #define cfgBIFPLR4_0_PCIE_ESM_CAP_1 0x03d4 |
| #define cfgBIFPLR4_0_PCIE_ESM_CAP_2 0x03d8 |
| #define cfgBIFPLR4_0_PCIE_ESM_CAP_3 0x03dc |
| #define cfgBIFPLR4_0_PCIE_ESM_CAP_4 0x03e0 |
| #define cfgBIFPLR4_0_PCIE_ESM_CAP_5 0x03e4 |
| #define cfgBIFPLR4_0_PCIE_ESM_CAP_6 0x03e8 |
| #define cfgBIFPLR4_0_PCIE_ESM_CAP_7 0x03ec |
| |
| |
| // addressBlock: nbio_pcie0_bifplr5_cfgdecp |
| // base address: 0x0 |
| #define cfgBIFPLR5_0_VENDOR_ID 0x0000 |
| #define cfgBIFPLR5_0_DEVICE_ID 0x0002 |
| #define cfgBIFPLR5_0_COMMAND 0x0004 |
| #define cfgBIFPLR5_0_STATUS 0x0006 |
| #define cfgBIFPLR5_0_REVISION_ID 0x0008 |
| #define cfgBIFPLR5_0_PROG_INTERFACE 0x0009 |
| #define cfgBIFPLR5_0_SUB_CLASS 0x000a |
| #define cfgBIFPLR5_0_BASE_CLASS 0x000b |
| #define cfgBIFPLR5_0_CACHE_LINE 0x000c |
| #define cfgBIFPLR5_0_LATENCY 0x000d |
| #define cfgBIFPLR5_0_HEADER 0x000e |
| #define cfgBIFPLR5_0_BIST 0x000f |
| #define cfgBIFPLR5_0_SUB_BUS_NUMBER_LATENCY 0x0018 |
| #define cfgBIFPLR5_0_IO_BASE_LIMIT 0x001c |
| #define cfgBIFPLR5_0_SECONDARY_STATUS 0x001e |
| #define cfgBIFPLR5_0_MEM_BASE_LIMIT 0x0020 |
| #define cfgBIFPLR5_0_PREF_BASE_LIMIT 0x0024 |
| #define cfgBIFPLR5_0_PREF_BASE_UPPER 0x0028 |
| #define cfgBIFPLR5_0_PREF_LIMIT_UPPER 0x002c |
| #define cfgBIFPLR5_0_IO_BASE_LIMIT_HI 0x0030 |
| #define cfgBIFPLR5_0_CAP_PTR 0x0034 |
| #define cfgBIFPLR5_0_INTERRUPT_LINE 0x003c |
| #define cfgBIFPLR5_0_INTERRUPT_PIN 0x003d |
| #define cfgBIFPLR5_0_IRQ_BRIDGE_CNTL 0x003e |
| #define cfgBIFPLR5_0_EXT_BRIDGE_CNTL 0x0040 |
| #define cfgBIFPLR5_0_PMI_CAP_LIST 0x0050 |
| #define cfgBIFPLR5_0_PMI_CAP 0x0052 |
| #define cfgBIFPLR5_0_PMI_STATUS_CNTL 0x0054 |
| #define cfgBIFPLR5_0_PCIE_CAP_LIST 0x0058 |
| #define cfgBIFPLR5_0_PCIE_CAP 0x005a |
| #define cfgBIFPLR5_0_DEVICE_CAP 0x005c |
| #define cfgBIFPLR5_0_DEVICE_CNTL 0x0060 |
| #define cfgBIFPLR5_0_DEVICE_STATUS 0x0062 |
| #define cfgBIFPLR5_0_LINK_CAP 0x0064 |
| #define cfgBIFPLR5_0_LINK_CNTL 0x0068 |
| #define cfgBIFPLR5_0_LINK_STATUS 0x006a |
| #define cfgBIFPLR5_0_SLOT_CAP 0x006c |
| #define cfgBIFPLR5_0_SLOT_CNTL 0x0070 |
| #define cfgBIFPLR5_0_SLOT_STATUS 0x0072 |
| #define cfgBIFPLR5_0_ROOT_CNTL 0x0074 |
| #define cfgBIFPLR5_0_ROOT_CAP 0x0076 |
| #define cfgBIFPLR5_0_ROOT_STATUS 0x0078 |
| #define cfgBIFPLR5_0_DEVICE_CAP2 0x007c |
| #define cfgBIFPLR5_0_DEVICE_CNTL2 0x0080 |
| #define cfgBIFPLR5_0_DEVICE_STATUS2 0x0082 |
| #define cfgBIFPLR5_0_LINK_CAP2 0x0084 |
| #define cfgBIFPLR5_0_LINK_CNTL2 0x0088 |
| #define cfgBIFPLR5_0_LINK_STATUS2 0x008a |
| #define cfgBIFPLR5_0_SLOT_CAP2 0x008c |
| #define cfgBIFPLR5_0_SLOT_CNTL2 0x0090 |
| #define cfgBIFPLR5_0_SLOT_STATUS2 0x0092 |
| #define cfgBIFPLR5_0_MSI_CAP_LIST 0x00a0 |
| #define cfgBIFPLR5_0_MSI_MSG_CNTL 0x00a2 |
| #define cfgBIFPLR5_0_MSI_MSG_ADDR_LO 0x00a4 |
| #define cfgBIFPLR5_0_MSI_MSG_ADDR_HI 0x00a8 |
| #define cfgBIFPLR5_0_MSI_MSG_DATA 0x00a8 |
| #define cfgBIFPLR5_0_MSI_MSG_DATA_64 0x00ac |
| #define cfgBIFPLR5_0_SSID_CAP_LIST 0x00c0 |
| #define cfgBIFPLR5_0_SSID_CAP 0x00c4 |
| #define cfgBIFPLR5_0_MSI_MAP_CAP_LIST 0x00c8 |
| #define cfgBIFPLR5_0_MSI_MAP_CAP 0x00ca |
| #define cfgBIFPLR5_0_MSI_MAP_ADDR_LO 0x00cc |
| #define cfgBIFPLR5_0_MSI_MAP_ADDR_HI 0x00d0 |
| #define cfgBIFPLR5_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x0100 |
| #define cfgBIFPLR5_0_PCIE_VENDOR_SPECIFIC_HDR 0x0104 |
| #define cfgBIFPLR5_0_PCIE_VENDOR_SPECIFIC1 0x0108 |
| #define cfgBIFPLR5_0_PCIE_VENDOR_SPECIFIC2 0x010c |
| #define cfgBIFPLR5_0_PCIE_VC_ENH_CAP_LIST 0x0110 |
| #define cfgBIFPLR5_0_PCIE_PORT_VC_CAP_REG1 0x0114 |
| #define cfgBIFPLR5_0_PCIE_PORT_VC_CAP_REG2 0x0118 |
| #define cfgBIFPLR5_0_PCIE_PORT_VC_CNTL 0x011c |
| #define cfgBIFPLR5_0_PCIE_PORT_VC_STATUS 0x011e |
| #define cfgBIFPLR5_0_PCIE_VC0_RESOURCE_CAP 0x0120 |
| #define cfgBIFPLR5_0_PCIE_VC0_RESOURCE_CNTL 0x0124 |
| #define cfgBIFPLR5_0_PCIE_VC0_RESOURCE_STATUS 0x012a |
| #define cfgBIFPLR5_0_PCIE_VC1_RESOURCE_CAP 0x012c |
| #define cfgBIFPLR5_0_PCIE_VC1_RESOURCE_CNTL 0x0130 |
| #define cfgBIFPLR5_0_PCIE_VC1_RESOURCE_STATUS 0x0136 |
| #define cfgBIFPLR5_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST 0x0140 |
| #define cfgBIFPLR5_0_PCIE_DEV_SERIAL_NUM_DW1 0x0144 |
| #define cfgBIFPLR5_0_PCIE_DEV_SERIAL_NUM_DW2 0x0148 |
| #define cfgBIFPLR5_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x0150 |
| #define cfgBIFPLR5_0_PCIE_UNCORR_ERR_STATUS 0x0154 |
| #define cfgBIFPLR5_0_PCIE_UNCORR_ERR_MASK 0x0158 |
| #define cfgBIFPLR5_0_PCIE_UNCORR_ERR_SEVERITY 0x015c |
| #define cfgBIFPLR5_0_PCIE_CORR_ERR_STATUS 0x0160 |
| #define cfgBIFPLR5_0_PCIE_CORR_ERR_MASK 0x0164 |
| #define cfgBIFPLR5_0_PCIE_ADV_ERR_CAP_CNTL 0x0168 |
| #define cfgBIFPLR5_0_PCIE_HDR_LOG0 0x016c |
| #define cfgBIFPLR5_0_PCIE_HDR_LOG1 0x0170 |
| #define cfgBIFPLR5_0_PCIE_HDR_LOG2 0x0174 |
| #define cfgBIFPLR5_0_PCIE_HDR_LOG3 0x0178 |
| #define cfgBIFPLR5_0_PCIE_ROOT_ERR_CMD 0x017c |
| #define cfgBIFPLR5_0_PCIE_ROOT_ERR_STATUS 0x0180 |
| #define cfgBIFPLR5_0_PCIE_ERR_SRC_ID 0x0184 |
| #define cfgBIFPLR5_0_PCIE_TLP_PREFIX_LOG0 0x0188 |
| #define cfgBIFPLR5_0_PCIE_TLP_PREFIX_LOG1 0x018c |
| #define cfgBIFPLR5_0_PCIE_TLP_PREFIX_LOG2 0x0190 |
| #define cfgBIFPLR5_0_PCIE_TLP_PREFIX_LOG3 0x0194 |
| #define cfgBIFPLR5_0_PCIE_SECONDARY_ENH_CAP_LIST 0x0270 |
| #define cfgBIFPLR5_0_PCIE_LINK_CNTL3 0x0274 |
| #define cfgBIFPLR5_0_PCIE_LANE_ERROR_STATUS 0x0278 |
| #define cfgBIFPLR5_0_PCIE_LANE_0_EQUALIZATION_CNTL 0x027c |
| #define cfgBIFPLR5_0_PCIE_LANE_1_EQUALIZATION_CNTL 0x027e |
| #define cfgBIFPLR5_0_PCIE_LANE_2_EQUALIZATION_CNTL 0x0280 |
| #define cfgBIFPLR5_0_PCIE_LANE_3_EQUALIZATION_CNTL 0x0282 |
| #define cfgBIFPLR5_0_PCIE_LANE_4_EQUALIZATION_CNTL 0x0284 |
| #define cfgBIFPLR5_0_PCIE_LANE_5_EQUALIZATION_CNTL 0x0286 |
| #define cfgBIFPLR5_0_PCIE_LANE_6_EQUALIZATION_CNTL 0x0288 |
| #define cfgBIFPLR5_0_PCIE_LANE_7_EQUALIZATION_CNTL 0x028a |
| #define cfgBIFPLR5_0_PCIE_LANE_8_EQUALIZATION_CNTL 0x028c |
| #define cfgBIFPLR5_0_PCIE_LANE_9_EQUALIZATION_CNTL 0x028e |
| #define cfgBIFPLR5_0_PCIE_LANE_10_EQUALIZATION_CNTL 0x0290 |
| #define cfgBIFPLR5_0_PCIE_LANE_11_EQUALIZATION_CNTL 0x0292 |
| #define cfgBIFPLR5_0_PCIE_LANE_12_EQUALIZATION_CNTL 0x0294 |
| #define cfgBIFPLR5_0_PCIE_LANE_13_EQUALIZATION_CNTL 0x0296 |
| #define cfgBIFPLR5_0_PCIE_LANE_14_EQUALIZATION_CNTL 0x0298 |
| #define cfgBIFPLR5_0_PCIE_LANE_15_EQUALIZATION_CNTL 0x029a |
| #define cfgBIFPLR5_0_PCIE_ACS_ENH_CAP_LIST 0x02a0 |
| #define cfgBIFPLR5_0_PCIE_ACS_CAP 0x02a4 |
| #define cfgBIFPLR5_0_PCIE_ACS_CNTL 0x02a6 |
| #define cfgBIFPLR5_0_PCIE_MC_ENH_CAP_LIST 0x02f0 |
| #define cfgBIFPLR5_0_PCIE_MC_CAP 0x02f4 |
| #define cfgBIFPLR5_0_PCIE_MC_CNTL 0x02f6 |
| #define cfgBIFPLR5_0_PCIE_MC_ADDR0 0x02f8 |
| #define cfgBIFPLR5_0_PCIE_MC_ADDR1 0x02fc |
| #define cfgBIFPLR5_0_PCIE_MC_RCV0 0x0300 |
| #define cfgBIFPLR5_0_PCIE_MC_RCV1 0x0304 |
| #define cfgBIFPLR5_0_PCIE_MC_BLOCK_ALL0 0x0308 |
| #define cfgBIFPLR5_0_PCIE_MC_BLOCK_ALL1 0x030c |
| #define cfgBIFPLR5_0_PCIE_MC_BLOCK_UNTRANSLATED_0 0x0310 |
| #define cfgBIFPLR5_0_PCIE_MC_BLOCK_UNTRANSLATED_1 0x0314 |
| #define cfgBIFPLR5_0_PCIE_MC_OVERLAY_BAR0 0x0318 |
| #define cfgBIFPLR5_0_PCIE_MC_OVERLAY_BAR1 0x031c |
| #define cfgBIFPLR5_0_PCIE_L1_PM_SUB_CAP_LIST 0x0370 |
| #define cfgBIFPLR5_0_PCIE_L1_PM_SUB_CAP 0x0374 |
| #define cfgBIFPLR5_0_PCIE_L1_PM_SUB_CNTL 0x0378 |
| #define cfgBIFPLR5_0_PCIE_L1_PM_SUB_CNTL2 0x037c |
| #define cfgBIFPLR5_0_PCIE_DPC_ENH_CAP_LIST 0x0380 |
| #define cfgBIFPLR5_0_PCIE_DPC_CAP_LIST 0x0384 |
| #define cfgBIFPLR5_0_PCIE_DPC_CNTL 0x0386 |
| #define cfgBIFPLR5_0_PCIE_DPC_STATUS 0x0388 |
| #define cfgBIFPLR5_0_PCIE_DPC_ERROR_SOURCE_ID 0x038a |
| #define cfgBIFPLR5_0_PCIE_RP_PIO_STATUS 0x038c |
| #define cfgBIFPLR5_0_PCIE_RP_PIO_MASK 0x0390 |
| #define cfgBIFPLR5_0_PCIE_RP_PIO_SEVERITY 0x0394 |
| #define cfgBIFPLR5_0_PCIE_RP_PIO_SYSERROR 0x0398 |
| #define cfgBIFPLR5_0_PCIE_RP_PIO_EXCEPTION 0x039c |
| #define cfgBIFPLR5_0_PCIE_RP_PIO_HDR_LOG0 0x03a0 |
| #define cfgBIFPLR5_0_PCIE_RP_PIO_HDR_LOG1 0x03a4 |
| #define cfgBIFPLR5_0_PCIE_RP_PIO_HDR_LOG2 0x03a8 |
| #define cfgBIFPLR5_0_PCIE_RP_PIO_HDR_LOG3 0x03ac |
| #define cfgBIFPLR5_0_PCIE_RP_PIO_IMPSPEC_LOG 0x03b0 |
| #define cfgBIFPLR5_0_PCIE_RP_PIO_PREFIX_LOG0 0x03b4 |
| #define cfgBIFPLR5_0_PCIE_RP_PIO_PREFIX_LOG1 0x03b8 |
| #define cfgBIFPLR5_0_PCIE_RP_PIO_PREFIX_LOG2 0x03bc |
| #define cfgBIFPLR5_0_PCIE_RP_PIO_PREFIX_LOG3 0x03c0 |
| #define cfgBIFPLR5_0_PCIE_ESM_CAP_LIST 0x03c4 |
| #define cfgBIFPLR5_0_PCIE_ESM_HEADER_1 0x03c8 |
| #define cfgBIFPLR5_0_PCIE_ESM_HEADER_2 0x03cc |
| #define cfgBIFPLR5_0_PCIE_ESM_STATUS 0x03ce |
| #define cfgBIFPLR5_0_PCIE_ESM_CTRL 0x03d0 |
| #define cfgBIFPLR5_0_PCIE_ESM_CAP_1 0x03d4 |
| #define cfgBIFPLR5_0_PCIE_ESM_CAP_2 0x03d8 |
| #define cfgBIFPLR5_0_PCIE_ESM_CAP_3 0x03dc |
| #define cfgBIFPLR5_0_PCIE_ESM_CAP_4 0x03e0 |
| #define cfgBIFPLR5_0_PCIE_ESM_CAP_5 0x03e4 |
| #define cfgBIFPLR5_0_PCIE_ESM_CAP_6 0x03e8 |
| #define cfgBIFPLR5_0_PCIE_ESM_CAP_7 0x03ec |
| |
| |
| // addressBlock: nbio_pcie0_bifplr6_cfgdecp |
| // base address: 0x0 |
| #define cfgBIFPLR6_0_VENDOR_ID 0x0000 |
| #define cfgBIFPLR6_0_DEVICE_ID 0x0002 |
| #define cfgBIFPLR6_0_COMMAND 0x0004 |
| #define cfgBIFPLR6_0_STATUS 0x0006 |
| #define cfgBIFPLR6_0_REVISION_ID 0x0008 |
| #define cfgBIFPLR6_0_PROG_INTERFACE 0x0009 |
| #define cfgBIFPLR6_0_SUB_CLASS 0x000a |
| #define cfgBIFPLR6_0_BASE_CLASS 0x000b |
| #define cfgBIFPLR6_0_CACHE_LINE 0x000c |
| #define cfgBIFPLR6_0_LATENCY 0x000d |
| #define cfgBIFPLR6_0_HEADER 0x000e |
| #define cfgBIFPLR6_0_BIST 0x000f |
| #define cfgBIFPLR6_0_SUB_BUS_NUMBER_LATENCY 0x0018 |
| #define cfgBIFPLR6_0_IO_BASE_LIMIT 0x001c |
| #define cfgBIFPLR6_0_SECONDARY_STATUS 0x001e |
| #define cfgBIFPLR6_0_MEM_BASE_LIMIT 0x0020 |
| #define cfgBIFPLR6_0_PREF_BASE_LIMIT 0x0024 |
| #define cfgBIFPLR6_0_PREF_BASE_UPPER 0x0028 |
| #define cfgBIFPLR6_0_PREF_LIMIT_UPPER 0x002c |
| #define cfgBIFPLR6_0_IO_BASE_LIMIT_HI 0x0030 |
| #define cfgBIFPLR6_0_CAP_PTR 0x0034 |
| #define cfgBIFPLR6_0_INTERRUPT_LINE 0x003c |
| #define cfgBIFPLR6_0_INTERRUPT_PIN 0x003d |
| #define cfgBIFPLR6_0_IRQ_BRIDGE_CNTL 0x003e |
| #define cfgBIFPLR6_0_EXT_BRIDGE_CNTL 0x0040 |
| #define cfgBIFPLR6_0_PMI_CAP_LIST 0x0050 |
| #define cfgBIFPLR6_0_PMI_CAP 0x0052 |
| #define cfgBIFPLR6_0_PMI_STATUS_CNTL 0x0054 |
| #define cfgBIFPLR6_0_PCIE_CAP_LIST 0x0058 |
| #define cfgBIFPLR6_0_PCIE_CAP 0x005a |
| #define cfgBIFPLR6_0_DEVICE_CAP 0x005c |
| #define cfgBIFPLR6_0_DEVICE_CNTL 0x0060 |
| #define cfgBIFPLR6_0_DEVICE_STATUS 0x0062 |
| #define cfgBIFPLR6_0_LINK_CAP 0x0064 |
| #define cfgBIFPLR6_0_LINK_CNTL 0x0068 |
| #define cfgBIFPLR6_0_LINK_STATUS 0x006a |
| #define cfgBIFPLR6_0_SLOT_CAP 0x006c |
| #define cfgBIFPLR6_0_SLOT_CNTL 0x0070 |
| #define cfgBIFPLR6_0_SLOT_STATUS 0x0072 |
| #define cfgBIFPLR6_0_ROOT_CNTL 0x0074 |
| #define cfgBIFPLR6_0_ROOT_CAP 0x0076 |
| #define cfgBIFPLR6_0_ROOT_STATUS 0x0078 |
| #define cfgBIFPLR6_0_DEVICE_CAP2 0x007c |
| #define cfgBIFPLR6_0_DEVICE_CNTL2 0x0080 |
| #define cfgBIFPLR6_0_DEVICE_STATUS2 0x0082 |
| #define cfgBIFPLR6_0_LINK_CAP2 0x0084 |
| #define cfgBIFPLR6_0_LINK_CNTL2 0x0088 |
| #define cfgBIFPLR6_0_LINK_STATUS2 0x008a |
| #define cfgBIFPLR6_0_SLOT_CAP2 0x008c |
| #define cfgBIFPLR6_0_SLOT_CNTL2 0x0090 |
| #define cfgBIFPLR6_0_SLOT_STATUS2 0x0092 |
| #define cfgBIFPLR6_0_MSI_CAP_LIST 0x00a0 |
| #define cfgBIFPLR6_0_MSI_MSG_CNTL 0x00a2 |
| #define cfgBIFPLR6_0_MSI_MSG_ADDR_LO 0x00a4 |
| #define cfgBIFPLR6_0_MSI_MSG_ADDR_HI 0x00a8 |
| #define cfgBIFPLR6_0_MSI_MSG_DATA 0x00a8 |
| #define cfgBIFPLR6_0_MSI_MSG_DATA_64 0x00ac |
| #define cfgBIFPLR6_0_SSID_CAP_LIST 0x00c0 |
| #define cfgBIFPLR6_0_SSID_CAP 0x00c4 |
| #define cfgBIFPLR6_0_MSI_MAP_CAP_LIST 0x00c8 |
| #define cfgBIFPLR6_0_MSI_MAP_CAP 0x00ca |
| #define cfgBIFPLR6_0_MSI_MAP_ADDR_LO 0x00cc |
| #define cfgBIFPLR6_0_MSI_MAP_ADDR_HI 0x00d0 |
| #define cfgBIFPLR6_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST 0x0100 |
| #define cfgBIFPLR6_0_PCIE_VENDOR_SPECIFIC_HDR 0x0104 |
| #define cfgBIFPLR6_0_PCIE_VENDOR_SPECIFIC1 0x0108 |
| #define cfgBIFPLR6_0_PCIE_VENDOR_SPECIFIC2 0x010c |
| #define cfgBIFPLR6_0_PCIE_VC_ENH_CAP_LIST 0x0110 |
| #define cfgBIFPLR6_0_PCIE_PORT_VC_CAP_REG1 0x0114 |
| #define cfgBIFPLR6_0_PCIE_PORT_VC_CAP_REG2 0x0118 |
| #define cfgBIFPLR6_0_PCIE_PORT_VC_CNTL 0x011c |
| #define cfgBIFPLR6_0_PCIE_PORT_VC_STATUS 0x011e |
| #define cfgBIFPLR6_0_PCIE_VC0_RESOURCE_CAP 0x0120 |
| #define cfgBIFPLR6_0_PCIE_VC0_RESOURCE_CNTL 0x0124 |
| #define cfgBIFPLR6_0_PCIE_VC0_RESOURCE_STATUS 0x012a |
| #define cfgBIFPLR6_0_PCIE_VC1_RESOURCE_CAP 0x012c |
| #define cfgBIFPLR6_0_PCIE_VC1_RESOURCE_CNTL 0x0130 |
| #define cfgBIFPLR6_0_PCIE_VC1_RESOURCE_STATUS 0x0136 |
| #define cfgBIFPLR6_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST 0x0140 |
| #define cfgBIFPLR6_0_PCIE_DEV_SERIAL_NUM_DW1 0x0144 |
| #define cfgBIFPLR6_0_PCIE_DEV_SERIAL_NUM_DW2 0x0148 |
| #define cfgBIFPLR6_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST 0x0150 |
| #define cfgBIFPLR6_0_PCIE_UNCORR_ERR_STATUS 0x0154 |
| #define cfgBIFPLR6_0_PCIE_UNCORR_ERR_MASK 0x0158 |
| #define cfgBIFPLR6_0_PCIE_UNCORR_ERR_SEVERITY 0x015c |
| #define cfgBIFPLR6_0_PCIE_CORR_ERR_STATUS 0x0160 |
| #define cfgBIFPLR6_0_PCIE_CORR_ERR_MASK 0x0164 |
| #define cfgBIFPLR6_0_PCIE_ADV_ERR_CAP_CNTL 0x0168 |
| #define cfgBIFPLR6_0_PCIE_HDR_LOG0 0x016c |
| #define cfgBIFPLR6_0_PCIE_HDR_LOG1 0x0170 |
| #define cfgBIFPLR6_0_PCIE_HDR_LOG2 0x0174 |
| #define cfgBIFPLR6_0_PCIE_HDR_LOG3 0x0178 |
| #define cfgBIFPLR6_0_PCIE_ROOT_ERR_CMD 0x017c |
| #define cfgBIFPLR6_0_PCIE_ROOT_ERR_STATUS 0x0180 |
| #define cfgBIFPLR6_0_PCIE_ERR_SRC_ID 0x0184 |
| #define cfgBIFPLR6_0_PCIE_TLP_PREFIX_LOG0 0x0188 |
| #define cfgBIFPLR6_0_PCIE_TLP_PREFIX_LOG1 0x018c |
| #define cfgBIFPLR6_0_PCIE_TLP_PREFIX_LOG2 0x0190 |
| #define cfgBIFPLR6_0_PCIE_TLP_PREFIX_LOG3 0x0194 |
| #define cfgBIFPLR6_0_PCIE_SECONDARY_ENH_CAP_LIST 0x0270 |
| #define cfgBIFPLR6_0_PCIE_LINK_CNTL3 0x0274 |
| #define cfgBIFPLR6_0_PCIE_LANE_ERROR_STATUS 0x0278 |
| #define cfgBIFPLR6_0_PCIE_LANE_0_EQUALIZATION_CNTL 0x027c |
| #define cfgBIFPLR6_0_PCIE_LANE_1_EQUALIZATION_CNTL 0x027e |
| #define cfgBIFPLR6_0_PCIE_LANE_2_EQUALIZATION_CNTL 0x0280 |
| #define cfgBIFPLR6_0_PCIE_LANE_3_EQUALIZATION_CNTL 0x0282 |
| #define cfgBIFPLR6_0_PCIE_LANE_4_EQUALIZATION_CNTL 0x0284 |
| #define cfgBIFPLR6_0_PCIE_LANE_5_EQUALIZATION_CNTL 0x0286 |
| #define cfgBIFPLR6_0_PCIE_LANE_6_EQUALIZATION_CNTL 0x0288 |
| #define cfgBIFPLR6_0_PCIE_LANE_7_EQUALIZATION_CNTL 0x028a |
| #define cfgBIFPLR6_0_PCIE_LANE_8_EQUALIZATION_CNTL 0x028c |
| #define cfgBIFPLR6_0_PCIE_LANE_9_EQUALIZATION_CNTL 0x028e |
| #define cfgBIFPLR6_0_PCIE_LANE_10_EQUALIZATION_CNTL 0x0290 |
| #define cfgBIFPLR6_0_PCIE_LANE_11_EQUALIZATION_CNTL 0x0292 |
| #define cfgBIFPLR6_0_PCIE_LANE_12_EQUALIZATION_CNTL 0x0294 |
| #define cfgBIFPLR6_0_PCIE_LANE_13_EQUALIZATION_CNTL 0x0296 |
| #define cfgBIFPLR6_0_PCIE_LANE_14_EQUALIZATION_CNTL 0x0298 |
| #define cfgBIFPLR6_0_PCIE_LANE_15_EQUALIZATION_CNTL 0x029a |
| #define cfgBIFPLR6_0_PCIE_ACS_ENH_CAP_LIST 0x02a0 |
| #define cfgBIFPLR6_0_PCIE_ACS_CAP 0x02a4 |
| #define cfgBIFPLR6_0_PCIE_ACS_CNTL 0x02a6 |
| #define cfgBIFPLR6_0_PCIE_MC_ENH_CAP_LIST 0x02f0 |
| #define cfgBIFPLR6_0_PCIE_MC_CAP 0x02f4 |
| #define cfgBIFPLR6_0_PCIE_MC_CNTL 0x02f6 |
| #define cfgBIFPLR6_0_PCIE_MC_ADDR0 0x02f8 |
| #define cfgBIFPLR6_0_PCIE_MC_ADDR1 0x02fc |
| #define cfgBIFPLR6_0_PCIE_MC_RCV0 0x0300 |
| #define cfgBIFPLR6_0_PCIE_MC_RCV1 0x0304 |
| #define cfgBIFPLR6_0_PCIE_MC_BLOCK_ALL0 0x0308 |
| #define cfgBIFPLR6_0_PCIE_MC_BLOCK_ALL1 0x030c |
| #define cfgBIFPLR6_0_PCIE_MC_BLOCK_UNTRANSLATED_0 0x0310 |
| #define cfgBIFPLR6_0_PCIE_MC_BLOCK_UNTRANSLATED_1 0x0314 |
| #define cfgBIFPLR6_0_PCIE_MC_OVERLAY_BAR0 0x0318 |
| #define cfgBIFPLR6_0_PCIE_MC_OVERLAY_BAR1 0x031c |
| #define cfgBIFPLR6_0_PCIE_L1_PM_SUB_CAP_LIST 0x0370 |
| #define cfgBIFPLR6_0_PCIE_L1_PM_SUB_CAP 0x0374 |
| #define cfgBIFPLR6_0_PCIE_L1_PM_SUB_CNTL 0x0378 |
| #define cfgBIFPLR6_0_PCIE_L1_PM_SUB_CNTL2 0x037c |
| #define cfgBIFPLR6_0_PCIE_DPC_ENH_CAP_LIST 0x0380 |
| #define cfgBIFPLR6_0_PCIE_DPC_CAP_LIST 0x0384 |
| #define cfgBIFPLR6_0_PCIE_DPC_CNTL 0x0386 |
| #define cfgBIFPLR6_0_PCIE_DPC_STATUS 0x0388 |
| #define cfgBIFPLR6_0_PCIE_DPC_ERROR_SOURCE_ID 0x038a |
| #define cfgBIFPLR6_0_PCIE_RP_PIO_STATUS 0x038c |
| #define cfgBIFPLR6_0_PCIE_RP_PIO_MASK 0x0390 |
| #define cfgBIFPLR6_0_PCIE_RP_PIO_SEVERITY 0x0394 |
| #define cfgBIFPLR6_0_PCIE_RP_PIO_SYSERROR 0x0398 |
| #define cfgBIFPLR6_0_PCIE_RP_PIO_EXCEPTION 0x039c |
| #define cfgBIFPLR6_0_PCIE_RP_PIO_HDR_LOG0 0x03a0 |
| #define cfgBIFPLR6_0_PCIE_RP_PIO_HDR_LOG1 0x03a4 |
| #define cfgBIFPLR6_0_PCIE_RP_PIO_HDR_LOG2 0x03a8 |
| #define cfgBIFPLR6_0_PCIE_RP_PIO_HDR_LOG3 0x03ac |
| #define cfgBIFPLR6_0_PCIE_RP_PIO_IMPSPEC_LOG 0x03b0 |
| #define cfgBIFPLR6_0_PCIE_RP_PIO_PREFIX_LOG0 0x03b4 |
| #define cfgBIFPLR6_0_PCIE_RP_PIO_PREFIX_LOG1 0x03b8 |
| #define cfgBIFPLR6_0_PCIE_RP_PIO_PREFIX_LOG2 0x03bc |
| #define cfgBIFPLR6_0_PCIE_RP_PIO_PREFIX_LOG3 0x03c0 |
| #define cfgBIFPLR6_0_PCIE_ESM_CAP_LIST 0x03c4 |
| #define cfgBIFPLR6_0_PCIE_ESM_HEADER_1 0x03c8 |
| #define cfgBIFPLR6_0_PCIE_ESM_HEADER_2 0x03cc |
| #define cfgBIFPLR6_0_PCIE_ESM_STATUS 0x03ce |
| #define cfgBIFPLR6_0_PCIE_ESM_CTRL 0x03d0 |
| #define cfgBIFPLR6_0_PCIE_ESM_CAP_1 0x03d4 |
| #define cfgBIFPLR6_0_PCIE_ESM_CAP_2 0x03d8 |
| #define cfgBIFPLR6_0_PCIE_ESM_CAP_3 0x03dc |
| #define cfgBIFPLR6_0_PCIE_ESM_CAP_4 0x03e0 |
| #define cfgBIFPLR6_0_PCIE_ESM_CAP_5 0x03e4 |
| #define cfgBIFPLR6_0_PCIE_ESM_CAP_6 0x03e8 |
| #define cfgBIFPLR6_0_PCIE_ESM_CAP_7 0x03ec |
| |
| |
| // addressBlock: nbio_dbgu0_dbgudec |
| // base address: 0x700 |
| #define mmport_a_addr 0x01ac |
| #define mmport_a_addr_BASE_IDX 1 |
| #define mmport_a_data_lo 0x01ad |
| #define mmport_a_data_lo_BASE_IDX 1 |
| #define mmport_a_data_hi 0x01ae |
| #define mmport_a_data_hi_BASE_IDX 1 |
| #define mmport_b_addr 0x01af |
| #define mmport_b_addr_BASE_IDX 1 |
| #define mmport_b_data_lo 0x01b0 |
| #define mmport_b_data_lo_BASE_IDX 1 |
| #define mmport_b_data_hi 0x01b1 |
| #define mmport_b_data_hi_BASE_IDX 1 |
| #define mmport_c_addr 0x01b2 |
| #define mmport_c_addr_BASE_IDX 1 |
| #define mmport_c_data_lo 0x01b3 |
| #define mmport_c_data_lo_BASE_IDX 1 |
| #define mmport_c_data_hi 0x01b4 |
| #define mmport_c_data_hi_BASE_IDX 1 |
| #define mmport_d_addr 0x01b5 |
| #define mmport_d_addr_BASE_IDX 1 |
| #define mmport_d_data_lo 0x01b6 |
| #define mmport_d_data_lo_BASE_IDX 1 |
| #define mmport_d_data_hi 0x01b7 |
| #define mmport_d_data_hi_BASE_IDX 1 |
| |
| |
| // addressBlock: nbio_iohub_iommu_l2mmio_l2mmiocfg |
| // base address: 0x0 |
| #define mmIOMMU_MMIO_DEVTBL_BASE_0 0x0000 |
| #define mmIOMMU_MMIO_DEVTBL_BASE_0_BASE_IDX 0 |
| #define mmIOMMU_MMIO_DEVTBL_BASE_1 0x0001 |
| #define mmIOMMU_MMIO_DEVTBL_BASE_1_BASE_IDX 0 |
| #define mmIOMMU_MMIO_CMD_BASE_0 0x0002 |
| #define mmIOMMU_MMIO_CMD_BASE_0_BASE_IDX 0 |
| #define mmIOMMU_MMIO_CMD_BASE_1 0x0003 |
| #define mmIOMMU_MMIO_CMD_BASE_1_BASE_IDX 0 |
| #define mmIOMMU_MMIO_EVENT_BASE_0 0x0004 |
| #define mmIOMMU_MMIO_EVENT_BASE_0_BASE_IDX 0 |
| #define mmIOMMU_MMIO_EVENT_BASE_1 0x0005 |
| #define mmIOMMU_MMIO_EVENT_BASE_1_BASE_IDX 0 |
| #define mmIOMMU_MMIO_CNTRL_0 0x0006 |
| #define mmIOMMU_MMIO_CNTRL_0_BASE_IDX 0 |
| #define mmIOMMU_MMIO_CNTRL_1 0x0007 |
| #define mmIOMMU_MMIO_CNTRL_1_BASE_IDX 0 |
| #define mmIOMMU_MMIO_EXCL_BASE_0 0x0008 |
| #define mmIOMMU_MMIO_EXCL_BASE_0_BASE_IDX 0 |
| #define mmIOMMU_MMIO_EXCL_BASE_1 0x0009 |
| #define mmIOMMU_MMIO_EXCL_BASE_1_BASE_IDX 0 |
| #define mmIOMMU_MMIO_EXCL_LIM_0 0x000a |
| #define mmIOMMU_MMIO_EXCL_LIM_0_BASE_IDX 0 |
| #define mmIOMMU_MMIO_EXCL_LIM_1 0x000b |
| #define mmIOMMU_MMIO_EXCL_LIM_1_BASE_IDX 0 |
| #define mmIOMMU_MMIO_EFR_0 0x000c |
| #define mmIOMMU_MMIO_EFR_0_BASE_IDX 0 |
| #define mmIOMMU_MMIO_EFR_1 0x000d |
| #define mmIOMMU_MMIO_EFR_1_BASE_IDX 0 |
| #define mmIOMMU_MMIO_PPR_BASE_0 0x000e |
| #define mmIOMMU_MMIO_PPR_BASE_0_BASE_IDX 0 |
| #define mmIOMMU_MMIO_PPR_BASE_1 0x000f |
| #define mmIOMMU_MMIO_PPR_BASE_1_BASE_IDX 0 |
| #define mmIOMMU_MMIO_HW_ERR_UPPER_0 0x0010 |
| #define mmIOMMU_MMIO_HW_ERR_UPPER_0_BASE_IDX 0 |
| #define mmIOMMU_MMIO_HW_ERR_UPPER_1 0x0011 |
| #define mmIOMMU_MMIO_HW_ERR_UPPER_1_BASE_IDX 0 |
| #define mmIOMMU_MMIO_HW_ERR_LOWER_0 0x0012 |
| #define mmIOMMU_MMIO_HW_ERR_LOWER_0_BASE_IDX 0 |
| #define mmIOMMU_MMIO_HW_ERR_LOWER_1 0x0013 |
| #define mmIOMMU_MMIO_HW_ERR_LOWER_1_BASE_IDX 0 |
| #define mmIOMMU_MMIO_HW_ERR_STATUS_0 0x0000 |
| #define mmIOMMU_MMIO_HW_ERR_STATUS_0_BASE_IDX 1 |
| #define mmIOMMU_MMIO_HW_ERR_STATUS_1 0x0001 |
| #define mmIOMMU_MMIO_HW_ERR_STATUS_1_BASE_IDX 1 |
| #define mmSMI_FILTER_REGISTER_0_0 0x0004 |
| #define mmSMI_FILTER_REGISTER_0_0_BASE_IDX 1 |
| #define mmSMI_FILTER_REGISTER_0_1 0x0005 |
| #define mmSMI_FILTER_REGISTER_0_1_BASE_IDX 1 |
| #define mmSMI_FILTER_REGISTER_1_0 0x0006 |
| #define mmSMI_FILTER_REGISTER_1_0_BASE_IDX 1 |
| #define mmSMI_FILTER_REGISTER_1_1 0x0007 |
| #define mmSMI_FILTER_REGISTER_1_1_BASE_IDX 1 |
| #define mmSMI_FILTER_REGISTER_2_0 0x0008 |
| #define mmSMI_FILTER_REGISTER_2_0_BASE_IDX 1 |
| #define mmSMI_FILTER_REGISTER_2_1 0x0009 |
| #define mmSMI_FILTER_REGISTER_2_1_BASE_IDX 1 |
| #define mmSMI_FILTER_REGISTER_3_0 0x000a |
| #define mmSMI_FILTER_REGISTER_3_0_BASE_IDX 1 |
| #define mmSMI_FILTER_REGISTER_3_1 0x000b |
| #define mmSMI_FILTER_REGISTER_3_1_BASE_IDX 1 |
| #define mmIOMMU_MMIO_GA_LOG_BASE_0 0x0024 |
| #define mmIOMMU_MMIO_GA_LOG_BASE_0_BASE_IDX 1 |
| #define mmIOMMU_MMIO_GA_LOG_BASE_1 0x0025 |
| #define mmIOMMU_MMIO_GA_LOG_BASE_1_BASE_IDX 1 |
| #define mmIOMMU_MMIO_GA_LOG_TAILPTR_ADDR_0 0x0026 |
| #define mmIOMMU_MMIO_GA_LOG_TAILPTR_ADDR_0_BASE_IDX 1 |
| #define mmIOMMU_MMIO_GA_LOG_TAILPTR_ADDR_1 0x0027 |
| #define mmIOMMU_MMIO_GA_LOG_TAILPTR_ADDR_1_BASE_IDX 1 |
| #define mmIOMMU_MMIO_PPR_B_BASE_0 0x0028 |
| #define mmIOMMU_MMIO_PPR_B_BASE_0_BASE_IDX 1 |
| #define mmIOMMU_MMIO_PPR_B_BASE_1 0x0029 |
| #define mmIOMMU_MMIO_PPR_B_BASE_1_BASE_IDX 1 |
| #define mmIOMMU_MMIO_EVENT_B_BASE_0 0x002a |
| #define mmIOMMU_MMIO_EVENT_B_BASE_0_BASE_IDX 1 |
| #define mmIOMMU_MMIO_EVENT_B_BASE_1 0x002b |
| #define mmIOMMU_MMIO_EVENT_B_BASE_1_BASE_IDX 1 |
| #define mmIOMMU_MMIO_DEVTBL_1_BASE_0 0x002c |
| #define mmIOMMU_MMIO_DEVTBL_1_BASE_0_BASE_IDX 1 |
| #define mmIOMMU_MMIO_DEVTBL_1_BASE_1 0x002d |
| #define mmIOMMU_MMIO_DEVTBL_1_BASE_1_BASE_IDX 1 |
| #define mmIOMMU_MMIO_DEVTBL_2_BASE_0 0x002e |
| #define mmIOMMU_MMIO_DEVTBL_2_BASE_0_BASE_IDX 1 |
| #define mmIOMMU_MMIO_DEVTBL_2_BASE_1 0x002f |
| #define mmIOMMU_MMIO_DEVTBL_2_BASE_1_BASE_IDX 1 |
| #define mmIOMMU_MMIO_DEVTBL_3_BASE_0 0x0030 |
| #define mmIOMMU_MMIO_DEVTBL_3_BASE_0_BASE_IDX 1 |
| #define mmIOMMU_MMIO_DEVTBL_3_BASE_1 0x0031 |
| #define mmIOMMU_MMIO_DEVTBL_3_BASE_1_BASE_IDX 1 |
| #define mmIOMMU_MMIO_DEVTBL_4_BASE_0 0x0032 |
| #define mmIOMMU_MMIO_DEVTBL_4_BASE_0_BASE_IDX 1 |
| #define mmIOMMU_MMIO_DEVTBL_4_BASE_1 0x0033 |
| #define mmIOMMU_MMIO_DEVTBL_4_BASE_1_BASE_IDX 1 |
| #define mmIOMMU_MMIO_DEVTBL_5_BASE_0 0x0034 |
| #define mmIOMMU_MMIO_DEVTBL_5_BASE_0_BASE_IDX 1 |
| #define mmIOMMU_MMIO_DEVTBL_5_BASE_1 0x0035 |
| #define mmIOMMU_MMIO_DEVTBL_5_BASE_1_BASE_IDX 1 |
| #define mmIOMMU_MMIO_DEVTBL_6_BASE_0 0x0036 |
| #define mmIOMMU_MMIO_DEVTBL_6_BASE_0_BASE_IDX 1 |
| #define mmIOMMU_MMIO_DEVTBL_6_BASE_1 0x0037 |
| #define mmIOMMU_MMIO_DEVTBL_6_BASE_1_BASE_IDX 1 |
| #define mmIOMMU_MMIO_DEVTBL_7_BASE_0 0x0038 |
| #define mmIOMMU_MMIO_DEVTBL_7_BASE_0_BASE_IDX 1 |
| #define mmIOMMU_MMIO_DEVTBL_7_BASE_1 0x0039 |
| #define mmIOMMU_MMIO_DEVTBL_7_BASE_1_BASE_IDX 1 |
| #define mmIOMMU_MMIO_DSFX 0x003a |
| #define mmIOMMU_MMIO_DSFX_BASE_IDX 1 |
| #define mmIOMMU_MMIO_DSCX 0x003c |
| #define mmIOMMU_MMIO_DSCX_BASE_IDX 1 |
| #define mmIOMMU_MMIO_DSSX 0x003e |
| #define mmIOMMU_MMIO_DSSX_BASE_IDX 1 |
| #define mmIOMMU_MMIO_CAP_MISC 0x0040 |
| #define mmIOMMU_MMIO_CAP_MISC_BASE_IDX 1 |
| #define mmIOMMU_MMIO_CAP_MISC_1 0x0041 |
| #define mmIOMMU_MMIO_CAP_MISC_1_BASE_IDX 1 |
| #define mmIOMMU_MMIO_MSI_CAP 0x0042 |
| #define mmIOMMU_MMIO_MSI_CAP_BASE_IDX 1 |
| #define mmIOMMU_MMIO_MSI_ADDR_LO 0x0043 |
| #define mmIOMMU_MMIO_MSI_ADDR_LO_BASE_IDX 1 |
| #define mmIOMMU_MMIO_MSI_ADDR_HI 0x0044 |
| #define mmIOMMU_MMIO_MSI_ADDR_HI_BASE_IDX 1 |
| #define mmIOMMU_MMIO_MSI_DATA 0x0045 |
| #define mmIOMMU_MMIO_MSI_DATA_BASE_IDX 1 |
| #define mmIOMMU_MMIO_MSI_MAPPING_CAP 0x0046 |
| #define mmIOMMU_MMIO_MSI_MAPPING_CAP_BASE_IDX 1 |
| #define mmIOMMU_MMIO_CONTROL_W 0x0047 |
| #define mmIOMMU_MMIO_CONTROL_W_BASE_IDX 1 |
| #define mmIOMMU_MARC_BASE_LO_0 0x006c |
| #define mmIOMMU_MARC_BASE_LO_0_BASE_IDX 1 |
| #define mmIOMMU_MARC_BASE_HI_0 0x006d |
| #define mmIOMMU_MARC_BASE_HI_0_BASE_IDX 1 |
| #define mmIOMMU_MARC_RELOC_LO_0 0x006e |
| #define mmIOMMU_MARC_RELOC_LO_0_BASE_IDX 1 |
| #define mmIOMMU_MARC_RELOC_HI_0 0x006f |
| #define mmIOMMU_MARC_RELOC_HI_0_BASE_IDX 1 |
| #define mmIOMMU_MARC_LEN_LO_0 0x0070 |
| #define mmIOMMU_MARC_LEN_LO_0_BASE_IDX 1 |
| #define mmIOMMU_MARC_LEN_HI_0 0x0071 |
| #define mmIOMMU_MARC_LEN_HI_0_BASE_IDX 1 |
| #define mmIOMMU_MARC_BASE_LO_1 0x0072 |
| #define mmIOMMU_MARC_BASE_LO_1_BASE_IDX 1 |
| #define mmIOMMU_MARC_BASE_HI_1 0x0073 |
| #define mmIOMMU_MARC_BASE_HI_1_BASE_IDX 1 |
| #define mmIOMMU_MARC_RELOC_LO_1 0x0074 |
| #define mmIOMMU_MARC_RELOC_LO_1_BASE_IDX 1 |
| #define mmIOMMU_MARC_RELOC_HI_1 0x0075 |
| #define mmIOMMU_MARC_RELOC_HI_1_BASE_IDX 1 |
| #define mmIOMMU_MARC_LEN_LO_1 0x0076 |
| #define mmIOMMU_MARC_LEN_LO_1_BASE_IDX 1 |
| #define mmIOMMU_MARC_LEN_HI_1 0x0077 |
| #define mmIOMMU_MARC_LEN_HI_1_BASE_IDX 1 |
| #define mmIOMMU_MARC_BASE_LO_2 0x0078 |
| #define mmIOMMU_MARC_BASE_LO_2_BASE_IDX 1 |
| #define mmIOMMU_MARC_BASE_HI_2 0x0079 |
| #define mmIOMMU_MARC_BASE_HI_2_BASE_IDX 1 |
| #define mmIOMMU_MARC_RELOC_LO_2 0x007a |
| #define mmIOMMU_MARC_RELOC_LO_2_BASE_IDX 1 |
| #define mmIOMMU_MARC_RELOC_HI_2 0x007b |
| #define mmIOMMU_MARC_RELOC_HI_2_BASE_IDX 1 |
| #define mmIOMMU_MARC_LEN_LO_2 0x007c |
| #define mmIOMMU_MARC_LEN_LO_2_BASE_IDX 1 |
| #define mmIOMMU_MARC_LEN_HI_2 0x007d |
| #define mmIOMMU_MARC_LEN_HI_2_BASE_IDX 1 |
| #define mmIOMMU_MARC_BASE_LO_3 0x007e |
| #define mmIOMMU_MARC_BASE_LO_3_BASE_IDX 1 |
| #define mmIOMMU_MARC_BASE_HI_3 0x007f |
| #define mmIOMMU_MARC_BASE_HI_3_BASE_IDX 1 |
| #define mmIOMMU_MARC_RELOC_LO_3 0x0080 |
| #define mmIOMMU_MARC_RELOC_LO_3_BASE_IDX 1 |
| #define mmIOMMU_MARC_RELOC_HI_3 0x0081 |
| #define mmIOMMU_MARC_RELOC_HI_3_BASE_IDX 1 |
| #define mmIOMMU_MARC_LEN_LO_3 0x0082 |
| #define mmIOMMU_MARC_LEN_LO_3_BASE_IDX 1 |
| #define mmIOMMU_MARC_LEN_HI_3 0x0083 |
| #define mmIOMMU_MARC_LEN_HI_3_BASE_IDX 1 |
| #define mmIOMMU_MMIO_CMD_BUF_HDPTR_0 0x07ec |
| #define mmIOMMU_MMIO_CMD_BUF_HDPTR_0_BASE_IDX 1 |
| #define mmIOMMU_MMIO_CMD_BUF_HDPTR_1 0x07ed |
| #define mmIOMMU_MMIO_CMD_BUF_HDPTR_1_BASE_IDX 1 |
| #define mmIOMMU_MMIO_CMD_BUF_TAILPTR_0 0x07ee |
| #define mmIOMMU_MMIO_CMD_BUF_TAILPTR_0_BASE_IDX 1 |
| #define mmIOMMU_MMIO_CMD_BUF_TAILPTR_1 0x07ef |
| #define mmIOMMU_MMIO_CMD_BUF_TAILPTR_1_BASE_IDX 1 |
| #define mmIOMMU_MMIO_EVENT_BUF_HDPTR_0 0x07f0 |
| #define mmIOMMU_MMIO_EVENT_BUF_HDPTR_0_BASE_IDX 1 |
| #define mmIOMMU_MMIO_EVENT_BUF_HDPTR_1 0x07f1 |
| #define mmIOMMU_MMIO_EVENT_BUF_HDPTR_1_BASE_IDX 1 |
| #define mmIOMMU_MMIO_EVENT_BUF_TAILPTR_0 0x07f2 |
| #define mmIOMMU_MMIO_EVENT_BUF_TAILPTR_0_BASE_IDX 1 |
| #define mmIOMMU_MMIO_EVENT_BUF_TAILPTR_1 0x07f3 |
| #define mmIOMMU_MMIO_EVENT_BUF_TAILPTR_1_BASE_IDX 1 |
| #define mmIOMMU_MMIO_STATUS_0 0x07f4 |
| #define mmIOMMU_MMIO_STATUS_0_BASE_IDX 1 |
| #define mmIOMMU_MMIO_STATUS_1 0x07f5 |
| #define mmIOMMU_MMIO_STATUS_1_BASE_IDX 1 |
| #define mmIOMMU_MMIO_PPR_BUF_HDPTR_0 0x07f8 |
| #define mmIOMMU_MMIO_PPR_BUF_HDPTR_0_BASE_IDX 1 |
| #define mmIOMMU_MMIO_PPR_BUF_HDPTR_1 0x07f9 |
| #define mmIOMMU_MMIO_PPR_BUF_HDPTR_1_BASE_IDX 1 |
| #define mmIOMMU_MMIO_PPR_BUF_TAILPTR_0 0x07fa |
| #define mmIOMMU_MMIO_PPR_BUF_TAILPTR_0_BASE_IDX 1 |
| #define mmIOMMU_MMIO_PPR_BUF_TAILPTR_1 0x07fb |
| #define mmIOMMU_MMIO_PPR_BUF_TAILPTR_1_BASE_IDX 1 |
| #define mmIOMMU_MMIO_GA_BUF_HDPTR_0 0x07fc |
| #define mmIOMMU_MMIO_GA_BUF_HDPTR_0_BASE_IDX 1 |
| #define mmIOMMU_MMIO_GA_BUF_HDPTR_1 0x07fd |
| #define mmIOMMU_MMIO_GA_BUF_HDPTR_1_BASE_IDX 1 |
| #define mmIOMMU_MMIO_GA_BUF_TAILPTR_0 0x07fe |
| #define mmIOMMU_MMIO_GA_BUF_TAILPTR_0_BASE_IDX 1 |
| #define mmIOMMU_MMIO_GA_BUF_TAILPTR_1 0x07ff |
| #define mmIOMMU_MMIO_GA_BUF_TAILPTR_1_BASE_IDX 1 |
| #define mmIOMMU_MMIO_PPR_B_BUF_HDPTR_0 0x0800 |
| #define mmIOMMU_MMIO_PPR_B_BUF_HDPTR_0_BASE_IDX 1 |
| #define mmIOMMU_MMIO_PPR_B_BUF_HDPTR_1 0x0801 |
| #define mmIOMMU_MMIO_PPR_B_BUF_HDPTR_1_BASE_IDX 1 |
| #define mmIOMMU_MMIO_PPR_B_BUF_TAILPTR_0 0x0802 |
| #define mmIOMMU_MMIO_PPR_B_BUF_TAILPTR_0_BASE_IDX 1 |
| #define mmIOMMU_MMIO_PPR_B_BUF_TAILPTR_1 0x0803 |
| #define mmIOMMU_MMIO_PPR_B_BUF_TAILPTR_1_BASE_IDX 1 |
| #define mmIOMMU_MMIO_EVENT_B_BUF_HDPTR_0 0x0808 |
| #define mmIOMMU_MMIO_EVENT_B_BUF_HDPTR_0_BASE_IDX 1 |
| #define mmIOMMU_MMIO_EVENT_B_BUF_HDPTR_1 0x0809 |
| #define mmIOMMU_MMIO_EVENT_B_BUF_HDPTR_1_BASE_IDX 1 |
| #define mmIOMMU_MMIO_EVENT_B_BUF_TAILPTR_0 0x080a |
| #define mmIOMMU_MMIO_EVENT_B_BUF_TAILPTR_0_BASE_IDX 1 |
| #define mmIOMMU_MMIO_EVENT_B_BUF_TAILPTR_1 0x080b |
| #define mmIOMMU_MMIO_EVENT_B_BUF_TAILPTR_1_BASE_IDX 1 |
| #define mmIOMMU_MMIO_PPR_AUTORESP_0 0x080c |
| #define mmIOMMU_MMIO_PPR_AUTORESP_0_BASE_IDX 1 |
| #define mmIOMMU_MMIO_PPR_OVERFLOW_EARLY_0 0x080e |
| #define mmIOMMU_MMIO_PPR_OVERFLOW_EARLY_0_BASE_IDX 1 |
| #define mmIOMMU_MMIO_PPR_B_OVERFLOW_EARLY_0 0x0810 |
| #define mmIOMMU_MMIO_PPR_B_OVERFLOW_EARLY_0_BASE_IDX 1 |
| #define mmIOMMU_MMIO_COUNTER_CONFIG_0 0x02e0 |
| #define mmIOMMU_MMIO_COUNTER_CONFIG_0_BASE_IDX 2 |
| #define mmIOMMU_MMIO_COUNTER_CONFIG_1 0x02e1 |
| #define mmIOMMU_MMIO_COUNTER_CONFIG_1_BASE_IDX 2 |
| #define mmIOMMU_MMIO_COUNTER_PASID_BANK_LOCK_0 0x02e2 |
| #define mmIOMMU_MMIO_COUNTER_PASID_BANK_LOCK_0_BASE_IDX 2 |
| #define mmIOMMU_MMIO_COUNTER_PASID_BANK_LOCK_1 0x02e3 |
| #define mmIOMMU_MMIO_COUNTER_PASID_BANK_LOCK_1_BASE_IDX 2 |
| #define mmIOMMU_MMIO_COUNTER_DOMAIN_BANK_LOCK_0 0x02e4 |
| #define mmIOMMU_MMIO_COUNTER_DOMAIN_BANK_LOCK_0_BASE_IDX 2 |
| #define mmIOMMU_MMIO_COUNTER_DOMAIN_BANK_LOCK_1 0x02e5 |
| #define mmIOMMU_MMIO_COUNTER_DOMAIN_BANK_LOCK_1_BASE_IDX 2 |
| #define mmIOMMU_MMIO_COUNTER_DEVID_BANK_LOCK_0 0x02e6 |
| #define mmIOMMU_MMIO_COUNTER_DEVID_BANK_LOCK_0_BASE_IDX 2 |
| #define mmIOMMU_MMIO_COUNTER_DEVID_BANK_LOCK_1 0x02e7 |
| #define mmIOMMU_MMIO_COUNTER_DEVID_BANK_LOCK_1_BASE_IDX 2 |
| #define mmIOMMU_MMIO_COUNTER_BANK_0_CNT_0_0 0xf2e0 |
| #define mmIOMMU_MMIO_COUNTER_BANK_0_CNT_0_0_BASE_IDX 2 |
| #define mmIOMMU_MMIO_COUNTER_BANK_0_CNT_0_1 0xf2e1 |
| #define mmIOMMU_MMIO_COUNTER_BANK_0_CNT_0_1_BASE_IDX 2 |
| #define mmIOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_0_0 0xf2e2 |
| #define mmIOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_0_0_BASE_IDX 2 |
| #define mmIOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_0_1 0xf2e3 |
| #define mmIOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_0_1_BASE_IDX 2 |
| #define mmIOMMU_MMIO_PASID_MATCH_BANK_0_CNT_0_0 0xf2e4 |
| #define mmIOMMU_MMIO_PASID_MATCH_BANK_0_CNT_0_0_BASE_IDX 2 |
| #define mmIOMMU_MMIO_PASID_MATCH_BANK_0_CNT_0_1 0xf2e5 |
| #define mmIOMMU_MMIO_PASID_MATCH_BANK_0_CNT_0_1_BASE_IDX 2 |
| #define mmIOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_0_0 0xf2e6 |
| #define mmIOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_0_0_BASE_IDX 2 |
| #define mmIOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_0_1 0xf2e7 |
| #define mmIOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_0_1_BASE_IDX 2 |
| #define mmIOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_0_0 0xf2e8 |
| #define mmIOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_0_0_BASE_IDX 2 |
| #define mmIOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_0_1 0xf2e9 |
| #define mmIOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_0_1_BASE_IDX 2 |
| #define mmIOMMU_MMIO_COUNTER_RPT_BANK_0_CNT_0_0 0xf2ea |
| #define mmIOMMU_MMIO_COUNTER_RPT_BANK_0_CNT_0_0_BASE_IDX 2 |
| #define mmIOMMU_MMIO_COUNTER_RPT_BANK_0_CNT_0_1 0xf2eb |
| #define mmIOMMU_MMIO_COUNTER_RPT_BANK_0_CNT_0_1_BASE_IDX 2 |
| #define mmIOMMU_MMIO_COUNTER_BANK_0_CNT_1_0 0xf320 |
| #define mmIOMMU_MMIO_COUNTER_BANK_0_CNT_1_0_BASE_IDX 2 |
| #define mmIOMMU_MMIO_COUNTER_BANK_0_CNT_1_1 0xf321 |
| #define mmIOMMU_MMIO_COUNTER_BANK_0_CNT_1_1_BASE_IDX 2 |
| #define mmIOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_1_0 0xf322 |
| #define mmIOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_1_0_BASE_IDX 2 |
| #define mmIOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_1_1 0xf323 |
| #define mmIOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_1_1_BASE_IDX 2 |
| #define mmIOMMU_MMIO_PASID_MATCH_BANK_0_CNT_1_0 0xf324 |
| #define mmIOMMU_MMIO_PASID_MATCH_BANK_0_CNT_1_0_BASE_IDX 2 |
| #define mmIOMMU_MMIO_PASID_MATCH_BANK_0_CNT_1_1 0xf325 |
| #define mmIOMMU_MMIO_PASID_MATCH_BANK_0_CNT_1_1_BASE_IDX 2 |
| #define mmIOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_1_0 0xf326 |
| #define mmIOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_1_0_BASE_IDX 2 |
| #define mmIOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_1_1 0xf327 |
| #define mmIOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_1_1_BASE_IDX 2 |
| #define mmIOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_1_0 0xf328 |
| #define mmIOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_1_0_BASE_IDX 2 |
| #define mmIOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_1_1 0xf329 |
| #define mmIOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_1_1_BASE_IDX 2 |
| #define mmIOMMU_MMIO_COUNTER_RPT_BANK_0_CNT_1_0 0xf32a |
| #define mmIOMMU_MMIO_COUNTER_RPT_BANK_0_CNT_1_0_BASE_IDX 2 |
| #define mmIOMMU_MMIO_COUNTER_RPT_BANK_0_CNT_1_1 0xf32b |
| #define mmIOMMU_MMIO_COUNTER_RPT_BANK_0_CNT_1_1_BASE_IDX 2 |
| #define mmIOMMU_MMIO_COUNTER_BANK_0_CNT_2_0 0xf360 |
| #define mmIOMMU_MMIO_COUNTER_BANK_0_CNT_2_0_BASE_IDX 2 |
| #define mmIOMMU_MMIO_COUNTER_BANK_0_CNT_2_1 0xf361 |
| #define mmIOMMU_MMIO_COUNTER_BANK_0_CNT_2_1_BASE_IDX 2 |
| #define mmIOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_2_0 0xf362 |
| #define mmIOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_2_0_BASE_IDX 2 |
| #define mmIOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_2_1 0xf363 |
| #define mmIOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_2_1_BASE_IDX 2 |
| #define mmIOMMU_MMIO_PASID_MATCH_BANK_0_CNT_2_0 0xf364 |
| #define mmIOMMU_MMIO_PASID_MATCH_BANK_0_CNT_2_0_BASE_IDX 2 |
| #define mmIOMMU_MMIO_PASID_MATCH_BANK_0_CNT_2_1 0xf365 |
| #define mmIOMMU_MMIO_PASID_MATCH_BANK_0_CNT_2_1_BASE_IDX 2 |
| #define mmIOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_2_0 0xf366 |
| #define mmIOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_2_0_BASE_IDX 2 |
| #define mmIOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_2_1 0xf367 |
| #define mmIOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_2_1_BASE_IDX 2 |
| #define mmIOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_2_0 0xf368 |
| #define mmIOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_2_0_BASE_IDX 2 |
| #define mmIOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_2_1 0xf369 |
| #define mmIOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_2_1_BASE_IDX 2 |
| #define mmIOMMU_MMIO_COUNTER_RPT_BANK_0_CNT_2_0 0xf36a |
| #define mmIOMMU_MMIO_COUNTER_RPT_BANK_0_CNT_2_0_BASE_IDX 2 |
| #define mmIOMMU_MMIO_COUNTER_RPT_BANK_0_CNT_2_1 0xf36b |
| #define mmIOMMU_MMIO_COUNTER_RPT_BANK_0_CNT_2_1_BASE_IDX 2 |
| #define mmIOMMU_MMIO_COUNTER_BANK_0_CNT_3_0 0xf3a0 |
| #define mmIOMMU_MMIO_COUNTER_BANK_0_CNT_3_0_BASE_IDX 2 |
| #define mmIOMMU_MMIO_COUNTER_BANK_0_CNT_3_1 0xf3a1 |
| #define mmIOMMU_MMIO_COUNTER_BANK_0_CNT_3_1_BASE_IDX 2 |
| #define mmIOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_3_0 0xf3a2 |
| #define mmIOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_3_0_BASE_IDX 2 |
| #define mmIOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_3_1 0xf3a3 |
| #define mmIOMMU_MMIO_COUNTER_SRC_BANK_0_CNT_3_1_BASE_IDX 2 |
| #define mmIOMMU_MMIO_PASID_MATCH_BANK_0_CNT_3_0 0xf3a4 |
| #define mmIOMMU_MMIO_PASID_MATCH_BANK_0_CNT_3_0_BASE_IDX 2 |
| #define mmIOMMU_MMIO_PASID_MATCH_BANK_0_CNT_3_1 0xf3a5 |
| #define mmIOMMU_MMIO_PASID_MATCH_BANK_0_CNT_3_1_BASE_IDX 2 |
| #define mmIOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_3_0 0xf3a6 |
| #define mmIOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_3_0_BASE_IDX 2 |
| #define mmIOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_3_1 0xf3a7 |
| #define mmIOMMU_MMIO_DOMAIN_MATCH_BANK_0_CNT_3_1_BASE_IDX 2 |
| #define mmIOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_3_0 0xf3a8 |
| #define mmIOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_3_0_BASE_IDX 2 |
| #define mmIOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_3_1 0xf3a9 |
| #define mmIOMMU_MMIO_DEVICEID_MATCH_BANK_0_CNT_3_1_BASE_IDX 2 |
| #define mmIOMMU_MMIO_COUNTER_RPT_BANK_0_CNT_3_0 0xf3aa |
| #define mmIOMMU_MMIO_COUNTER_RPT_BANK_0_CNT_3_0_BASE_IDX 2 |
| #define mmIOMMU_MMIO_COUNTER_RPT_BANK_0_CNT_3_1 0xf3ab |
| #define mmIOMMU_MMIO_COUNTER_RPT_BANK_0_CNT_3_1_BASE_IDX 2 |
| #define mmIOMMU_MMIO_COUNTER_BANK_1_CNT_0_0 0x0000 |
| #define mmIOMMU_MMIO_COUNTER_BANK_1_CNT_0_0_BASE_IDX 3 |
| #define mmIOMMU_MMIO_COUNTER_BANK_1_CNT_0_1 0x0001 |
| #define mmIOMMU_MMIO_COUNTER_BANK_1_CNT_0_1_BASE_IDX 3 |
| #define mmIOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_0_0 0x0002 |
| #define mmIOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_0_0_BASE_IDX 3 |
| #define mmIOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_0_1 0x0003 |
| #define mmIOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_0_1_BASE_IDX 3 |
| #define mmIOMMU_MMIO_PASID_MATCH_BANK_1_CNT_0_0 0x0004 |
| #define mmIOMMU_MMIO_PASID_MATCH_BANK_1_CNT_0_0_BASE_IDX 3 |
| #define mmIOMMU_MMIO_PASID_MATCH_BANK_1_CNT_0_1 0x0005 |
| #define mmIOMMU_MMIO_PASID_MATCH_BANK_1_CNT_0_1_BASE_IDX 3 |
| #define mmIOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_0_0 0x0006 |
| #define mmIOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_0_0_BASE_IDX 3 |
| #define mmIOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_0_1 0x0007 |
| #define mmIOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_0_1_BASE_IDX 3 |
| #define mmIOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_0_0 0x0008 |
| #define mmIOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_0_0_BASE_IDX 3 |
| #define mmIOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_0_1 0x0009 |
| #define mmIOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_0_1_BASE_IDX 3 |
| #define mmIOMMU_MMIO_COUNTER_RPT_BANK_1_CNT_0_0 0x000a |
| #define mmIOMMU_MMIO_COUNTER_RPT_BANK_1_CNT_0_0_BASE_IDX 3 |
| #define mmIOMMU_MMIO_COUNTER_RPT_BANK_1_CNT_0_1 0x000b |
| #define mmIOMMU_MMIO_COUNTER_RPT_BANK_1_CNT_0_1_BASE_IDX 3 |
| #define mmIOMMU_MMIO_COUNTER_BANK_1_CNT_1_0 0x0040 |
| #define mmIOMMU_MMIO_COUNTER_BANK_1_CNT_1_0_BASE_IDX 3 |
| #define mmIOMMU_MMIO_COUNTER_BANK_1_CNT_1_1 0x0041 |
| #define mmIOMMU_MMIO_COUNTER_BANK_1_CNT_1_1_BASE_IDX 3 |
| #define mmIOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_1_0 0x0042 |
| #define mmIOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_1_0_BASE_IDX 3 |
| #define mmIOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_1_1 0x0043 |
| #define mmIOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_1_1_BASE_IDX 3 |
| #define mmIOMMU_MMIO_PASID_MATCH_BANK_1_CNT_1_0 0x0044 |
| #define mmIOMMU_MMIO_PASID_MATCH_BANK_1_CNT_1_0_BASE_IDX 3 |
| #define mmIOMMU_MMIO_PASID_MATCH_BANK_1_CNT_1_1 0x0045 |
| #define mmIOMMU_MMIO_PASID_MATCH_BANK_1_CNT_1_1_BASE_IDX 3 |
| #define mmIOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_1_0 0x0046 |
| #define mmIOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_1_0_BASE_IDX 3 |
| #define mmIOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_1_1 0x0047 |
| #define mmIOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_1_1_BASE_IDX 3 |
| #define mmIOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_1_0 0x0048 |
| #define mmIOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_1_0_BASE_IDX 3 |
| #define mmIOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_1_1 0x0049 |
| #define mmIOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_1_1_BASE_IDX 3 |
| #define mmIOMMU_MMIO_COUNTER_RPT_BANK_1_CNT_1_0 0x004a |
| #define mmIOMMU_MMIO_COUNTER_RPT_BANK_1_CNT_1_0_BASE_IDX 3 |
| #define mmIOMMU_MMIO_COUNTER_RPT_BANK_1_CNT_1_1 0x004b |
| #define mmIOMMU_MMIO_COUNTER_RPT_BANK_1_CNT_1_1_BASE_IDX 3 |
| #define mmIOMMU_MMIO_COUNTER_BANK_1_CNT_2_0 0x0080 |
| #define mmIOMMU_MMIO_COUNTER_BANK_1_CNT_2_0_BASE_IDX 3 |
| #define mmIOMMU_MMIO_COUNTER_BANK_1_CNT_2_1 0x0081 |
| #define mmIOMMU_MMIO_COUNTER_BANK_1_CNT_2_1_BASE_IDX 3 |
| #define mmIOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_2_0 0x0082 |
| #define mmIOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_2_0_BASE_IDX 3 |
| #define mmIOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_2_1 0x0083 |
| #define mmIOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_2_1_BASE_IDX 3 |
| #define mmIOMMU_MMIO_PASID_MATCH_BANK_1_CNT_2_0 0x0084 |
| #define mmIOMMU_MMIO_PASID_MATCH_BANK_1_CNT_2_0_BASE_IDX 3 |
| #define mmIOMMU_MMIO_PASID_MATCH_BANK_1_CNT_2_1 0x0085 |
| #define mmIOMMU_MMIO_PASID_MATCH_BANK_1_CNT_2_1_BASE_IDX 3 |
| #define mmIOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_2_0 0x0086 |
| #define mmIOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_2_0_BASE_IDX 3 |
| #define mmIOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_2_1 0x0087 |
| #define mmIOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_2_1_BASE_IDX 3 |
| #define mmIOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_2_0 0x0088 |
| #define mmIOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_2_0_BASE_IDX 3 |
| #define mmIOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_2_1 0x0089 |
| #define mmIOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_2_1_BASE_IDX 3 |
| #define mmIOMMU_MMIO_COUNTER_RPT_BANK_1_CNT_2_0 0x008a |
| #define mmIOMMU_MMIO_COUNTER_RPT_BANK_1_CNT_2_0_BASE_IDX 3 |
| #define mmIOMMU_MMIO_COUNTER_RPT_BANK_1_CNT_2_1 0x008b |
| #define mmIOMMU_MMIO_COUNTER_RPT_BANK_1_CNT_2_1_BASE_IDX 3 |
| #define mmIOMMU_MMIO_COUNTER_BANK_1_CNT_3_0 0x00c0 |
| #define mmIOMMU_MMIO_COUNTER_BANK_1_CNT_3_0_BASE_IDX 3 |
| #define mmIOMMU_MMIO_COUNTER_BANK_1_CNT_3_1 0x00c1 |
| #define mmIOMMU_MMIO_COUNTER_BANK_1_CNT_3_1_BASE_IDX 3 |
| #define mmIOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_3_0 0x00c2 |
| #define mmIOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_3_0_BASE_IDX 3 |
| #define mmIOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_3_1 0x00c3 |
| #define mmIOMMU_MMIO_COUNTER_SRC_BANK_1_CNT_3_1_BASE_IDX 3 |
| #define mmIOMMU_MMIO_PASID_MATCH_BANK_1_CNT_3_0 0x00c4 |
| #define mmIOMMU_MMIO_PASID_MATCH_BANK_1_CNT_3_0_BASE_IDX 3 |
| #define mmIOMMU_MMIO_PASID_MATCH_BANK_1_CNT_3_1 0x00c5 |
| #define mmIOMMU_MMIO_PASID_MATCH_BANK_1_CNT_3_1_BASE_IDX 3 |
| #define mmIOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_3_0 0x00c6 |
| #define mmIOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_3_0_BASE_IDX 3 |
| #define mmIOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_3_1 0x00c7 |
| #define mmIOMMU_MMIO_DOMAIN_MATCH_BANK_1_CNT_3_1_BASE_IDX 3 |
| #define mmIOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_3_0 0x00c8 |
| #define mmIOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_3_0_BASE_IDX 3 |
| #define mmIOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_3_1 0x00c9 |
| #define mmIOMMU_MMIO_DEVICEID_MATCH_BANK_1_CNT_3_1_BASE_IDX 3 |
| #define mmIOMMU_MMIO_COUNTER_RPT_BANK_1_CNT_3_0 0x00ca |
| #define mmIOMMU_MMIO_COUNTER_RPT_BANK_1_CNT_3_0_BASE_IDX 3 |
| #define mmIOMMU_MMIO_COUNTER_RPT_BANK_1_CNT_3_1 0x00cb |
| #define mmIOMMU_MMIO_COUNTER_RPT_BANK_1_CNT_3_1_BASE_IDX 3 |
| |
| |
| // addressBlock: nbio_nbif0_bif_bx_pf_SYSPFVFDEC |
| // base address: 0x0 |
| #define mmMM_INDEX 0x0000 |
| #define mmMM_INDEX_BASE_IDX 0 |
| #define mmMM_DATA 0x0001 |
| #define mmMM_DATA_BASE_IDX 0 |
| #define mmMM_INDEX_HI 0x0006 |
| #define mmMM_INDEX_HI_BASE_IDX 0 |
| |
| |
| // addressBlock: nbio_nbif0_bif_bx_pf_SYSDEC |
| // base address: 0x0 |
| #define mmSYSHUB_INDEX_OVLP 0x0008 |
| #define mmSYSHUB_INDEX_OVLP_BASE_IDX 0 |
| #define mmSYSHUB_DATA_OVLP 0x0009 |
| #define mmSYSHUB_DATA_OVLP_BASE_IDX 0 |
| #define mmPCIE_INDEX 0x000c |
| #define mmPCIE_INDEX_BASE_IDX 0 |
| #define mmPCIE_DATA 0x000d |
| #define mmPCIE_DATA_BASE_IDX 0 |
| #define mmPCIE_INDEX2 0x000e |
| #define mmPCIE_INDEX2_BASE_IDX 0 |
| #define mmPCIE_DATA2 0x000f |
| #define mmPCIE_DATA2_BASE_IDX 0 |
| #define mmSBIOS_SCRATCH_0 0x0034 |
| #define mmSBIOS_SCRATCH_0_BASE_IDX 1 |
| #define mmSBIOS_SCRATCH_1 0x0035 |
| #define mmSBIOS_SCRATCH_1_BASE_IDX 1 |
| #define mmSBIOS_SCRATCH_2 0x0036 |
| #define mmSBIOS_SCRATCH_2_BASE_IDX 1 |
| #define mmSBIOS_SCRATCH_3 0x0037 |
| #define mmSBIOS_SCRATCH_3_BASE_IDX 1 |
| #define mmBIOS_SCRATCH_0 0x0038 |
| #define mmBIOS_SCRATCH_0_BASE_IDX 1 |
| #define mmBIOS_SCRATCH_1 0x0039 |
| #define mmBIOS_SCRATCH_1_BASE_IDX 1 |
| #define mmBIOS_SCRATCH_2 0x003a |
| #define mmBIOS_SCRATCH_2_BASE_IDX 1 |
| #define mmBIOS_SCRATCH_3 0x003b |
| #define mmBIOS_SCRATCH_3_BASE_IDX 1 |
| #define mmBIOS_SCRATCH_4 0x003c |
| #define mmBIOS_SCRATCH_4_BASE_IDX 1 |
| #define mmBIOS_SCRATCH_5 0x003d |
| #define mmBIOS_SCRATCH_5_BASE_IDX 1 |
| #define mmBIOS_SCRATCH_6 0x003e |
| #define mmBIOS_SCRATCH_6_BASE_IDX 1 |
| #define mmBIOS_SCRATCH_7 0x003f |
| #define mmBIOS_SCRATCH_7_BASE_IDX 1 |
| #define mmBIOS_SCRATCH_8 0x0040 |
| #define mmBIOS_SCRATCH_8_BASE_IDX 1 |
| #define mmBIOS_SCRATCH_9 0x0041 |
| #define mmBIOS_SCRATCH_9_BASE_IDX 1 |
| #define mmBIOS_SCRATCH_10 0x0042 |
| #define mmBIOS_SCRATCH_10_BASE_IDX 1 |
| #define mmBIOS_SCRATCH_11 0x0043 |
| #define mmBIOS_SCRATCH_11_BASE_IDX 1 |
| #define mmBIOS_SCRATCH_12 0x0044 |
| #define mmBIOS_SCRATCH_12_BASE_IDX 1 |
| #define mmBIOS_SCRATCH_13 0x0045 |
| #define mmBIOS_SCRATCH_13_BASE_IDX 1 |
| #define mmBIOS_SCRATCH_14 0x0046 |
| #define mmBIOS_SCRATCH_14_BASE_IDX 1 |
| #define mmBIOS_SCRATCH_15 0x0047 |
| #define mmBIOS_SCRATCH_15_BASE_IDX 1 |
| #define mmBIF_RLC_INTR_CNTL 0x004c |
| #define mmBIF_RLC_INTR_CNTL_BASE_IDX 1 |
| #define mmBIF_VCE_INTR_CNTL 0x004d |
| #define mmBIF_VCE_INTR_CNTL_BASE_IDX 1 |
| #define mmBIF_UVD_INTR_CNTL 0x004e |
| #define mmBIF_UVD_INTR_CNTL_BASE_IDX 1 |
| #define mmGFX_MMIOREG_CAM_ADDR0 0x006c |
| #define mmGFX_MMIOREG_CAM_ADDR0_BASE_IDX 1 |
| #define mmGFX_MMIOREG_CAM_REMAP_ADDR0 0x006d |
| #define mmGFX_MMIOREG_CAM_REMAP_ADDR0_BASE_IDX 1 |
| #define mmGFX_MMIOREG_CAM_ADDR1 0x006e |
| #define mmGFX_MMIOREG_CAM_ADDR1_BASE_IDX 1 |
| #define mmGFX_MMIOREG_CAM_REMAP_ADDR1 0x006f |
| #define mmGFX_MMIOREG_CAM_REMAP_ADDR1_BASE_IDX 1 |
| #define mmGFX_MMIOREG_CAM_ADDR2 0x0070 |
| #define mmGFX_MMIOREG_CAM_ADDR2_BASE_IDX 1 |
| #define mmGFX_MMIOREG_CAM_REMAP_ADDR2 0x0071 |
| #define mmGFX_MMIOREG_CAM_REMAP_ADDR2_BASE_IDX 1 |
| #define mmGFX_MMIOREG_CAM_ADDR3 0x0072 |
| #define mmGFX_MMIOREG_CAM_ADDR3_BASE_IDX 1 |
| #define mmGFX_MMIOREG_CAM_REMAP_ADDR3 0x0073 |
| #define mmGFX_MMIOREG_CAM_REMAP_ADDR3_BASE_IDX 1 |
| #define mmGFX_MMIOREG_CAM_ADDR4 0x0074 |
| #define mmGFX_MMIOREG_CAM_ADDR4_BASE_IDX 1 |
| #define mmGFX_MMIOREG_CAM_REMAP_ADDR4 0x0075 |
| #define mmGFX_MMIOREG_CAM_REMAP_ADDR4_BASE_IDX 1 |
| #define mmGFX_MMIOREG_CAM_ADDR5 0x0076 |
| #define mmGFX_MMIOREG_CAM_ADDR5_BASE_IDX 1 |
| #define mmGFX_MMIOREG_CAM_REMAP_ADDR5 0x0077 |
| #define mmGFX_MMIOREG_CAM_REMAP_ADDR5_BASE_IDX 1 |
| #define mmGFX_MMIOREG_CAM_ADDR6 0x0078 |
| #define mmGFX_MMIOREG_CAM_ADDR6_BASE_IDX 1 |
| #define mmGFX_MMIOREG_CAM_REMAP_ADDR6 0x0079 |
| #define mmGFX_MMIOREG_CAM_REMAP_ADDR6_BASE_IDX 1 |
| #define mmGFX_MMIOREG_CAM_ADDR7 0x007a |
| #define mmGFX_MMIOREG_CAM_ADDR7_BASE_IDX 1 |
| #define mmGFX_MMIOREG_CAM_REMAP_ADDR7 0x007b |
| #define mmGFX_MMIOREG_CAM_REMAP_ADDR7_BASE_IDX 1 |
| #define mmGFX_MMIOREG_CAM_CNTL 0x007c |
| #define mmGFX_MMIOREG_CAM_CNTL_BASE_IDX 1 |
| #define mmGFX_MMIOREG_CAM_ZERO_CPL 0x007d |
| #define mmGFX_MMIOREG_CAM_ZERO_CPL_BASE_IDX 1 |
| #define mmGFX_MMIOREG_CAM_ONE_CPL 0x007e |
| #define mmGFX_MMIOREG_CAM_ONE_CPL_BASE_IDX 1 |
| #define mmGFX_MMIOREG_CAM_PROGRAMMABLE_CPL 0x007f |
| #define mmGFX_MMIOREG_CAM_PROGRAMMABLE_CPL_BASE_IDX 1 |
| |
| |
| // addressBlock: nbio_nbif0_syshub_mmreg_ind_syshubdec |
| // base address: 0x0 |
| #define mmSYSHUB_INDEX 0x0008 |
| #define mmSYSHUB_INDEX_BASE_IDX 0 |
| #define mmSYSHUB_DATA 0x0009 |
| #define mmSYSHUB_DATA_BASE_IDX 0 |
| |
| |
| // addressBlock: nbio_nbif0_rcc_strap_BIFDEC1 |
| // base address: 0x0 |
| #define mmRCC_DEV0_EPF0_STRAP0 0x000f |
| #define mmRCC_DEV0_EPF0_STRAP0_BASE_IDX 2 |
| |
| |
| // addressBlock: nbio_nbif0_rcc_ep_dev0_BIFDEC1 |
| // base address: 0x0 |
| #define mmEP_PCIE_SCRATCH 0x0023 |
| #define mmEP_PCIE_SCRATCH_BASE_IDX 2 |
| #define mmEP_PCIE_CNTL 0x0025 |
| #define mmEP_PCIE_CNTL_BASE_IDX 2 |
| #define mmEP_PCIE_INT_CNTL 0x0026 |
| #define mmEP_PCIE_INT_CNTL_BASE_IDX 2 |
| #define mmEP_PCIE_INT_STATUS 0x0027 |
| #define mmEP_PCIE_INT_STATUS_BASE_IDX 2 |
| #define mmEP_PCIE_RX_CNTL2 0x0028 |
| #define mmEP_PCIE_RX_CNTL2_BASE_IDX 2 |
| #define mmEP_PCIE_BUS_CNTL 0x0029 |
| #define mmEP_PCIE_BUS_CNTL_BASE_IDX 2 |
| #define mmEP_PCIE_CFG_CNTL 0x002a |
| #define mmEP_PCIE_CFG_CNTL_BASE_IDX 2 |
| #define mmEP_PCIE_TX_LTR_CNTL 0x002c |
| #define mmEP_PCIE_TX_LTR_CNTL_BASE_IDX 2 |
| #define mmPCIE_F1_DPA_SUBSTATE_PWR_ALLOC_0 0x002d |
| #define mmPCIE_F1_DPA_SUBSTATE_PWR_ALLOC_0_BASE_IDX 2 |
| #define mmPCIE_F1_DPA_SUBSTATE_PWR_ALLOC_1 0x002d |
| #define mmPCIE_F1_DPA_SUBSTATE_PWR_ALLOC_1_BASE_IDX 2 |
| #define mmPCIE_F1_DPA_SUBSTATE_PWR_ALLOC_2 0x002d |
| #define mmPCIE_F1_DPA_SUBSTATE_PWR_ALLOC_2_BASE_IDX 2 |
| #define mmPCIE_F1_DPA_SUBSTATE_PWR_ALLOC_3 0x002d |
| #define mmPCIE_F1_DPA_SUBSTATE_PWR_ALLOC_3_BASE_IDX 2 |
| #define mmPCIE_F1_DPA_SUBSTATE_PWR_ALLOC_4 0x002e |
| #define mmPCIE_F1_DPA_SUBSTATE_PWR_ALLOC_4_BASE_IDX 2 |
| #define mmPCIE_F1_DPA_SUBSTATE_PWR_ALLOC_5 0x002e |
| #define mmPCIE_F1_DPA_SUBSTATE_PWR_ALLOC_5_BASE_IDX 2 |
| #define mmPCIE_F1_DPA_SUBSTATE_PWR_ALLOC_6 0x002e |
| #define mmPCIE_F1_DPA_SUBSTATE_PWR_ALLOC_6_BASE_IDX 2 |
| #define mmPCIE_F1_DPA_SUBSTATE_PWR_ALLOC_7 0x002e |
| #define mmPCIE_F1_DPA_SUBSTATE_PWR_ALLOC_7_BASE_IDX 2 |
| #define mmEP_PCIE_F0_DPA_CAP 0x0032 |
| #define mmEP_PCIE_F0_DPA_CAP_BASE_IDX 2 |
| #define mmEP_PCIE_F0_DPA_LATENCY_INDICATOR 0x0033 |
| #define mmEP_PCIE_F0_DPA_LATENCY_INDICATOR_BASE_IDX 2 |
| #define mmEP_PCIE_F0_DPA_CNTL 0x0033 |
| #define mmEP_PCIE_F0_DPA_CNTL_BASE_IDX 2 |
| #define mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0 0x0033 |
| #define mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0_BASE_IDX 2 |
| #define mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1 0x0034 |
| #define mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1_BASE_IDX 2 |
| #define mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2 0x0034 |
| #define mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2_BASE_IDX 2 |
| #define mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3 0x0034 |
| #define mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3_BASE_IDX 2 |
| #define mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4 0x0034 |
| #define mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4_BASE_IDX 2 |
| #define mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5 0x0035 |
| #define mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5_BASE_IDX 2 |
| #define mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6 0x0035 |
| #define mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6_BASE_IDX 2 |
| #define mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7 0x0035 |
| #define mmPCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7_BASE_IDX 2 |
| #define mmEP_PCIE_PME_CONTROL 0x0035 |
| #define mmEP_PCIE_PME_CONTROL_BASE_IDX 2 |
| #define mmEP_PCIEP_RESERVED 0x0036 |
| #define mmEP_PCIEP_RESERVED_BASE_IDX 2 |
| #define mmEP_PCIE_TX_CNTL 0x0038 |
| #define mmEP_PCIE_TX_CNTL_BASE_IDX 2 |
| #define mmEP_PCIE_TX_REQUESTER_ID 0x0039 |
| #define mmEP_PCIE_TX_REQUESTER_ID_BASE_IDX 2 |
| #define mmEP_PCIE_ERR_CNTL 0x003a |
| #define mmEP_PCIE_ERR_CNTL_BASE_IDX 2 |
| #define mmEP_PCIE_RX_CNTL 0x003b |
| #define mmEP_PCIE_RX_CNTL_BASE_IDX 2 |
| #define mmEP_PCIE_LC_SPEED_CNTL 0x003c |
| #define mmEP_PCIE_LC_SPEED_CNTL_BASE_IDX 2 |
| |
| |
| // addressBlock: nbio_nbif0_rcc_dwn_dev0_BIFDEC1 |
| // base address: 0x0 |
| #define mmDN_PCIE_RESERVED 0x0040 |
| #define mmDN_PCIE_RESERVED_BASE_IDX 2 |
| #define mmDN_PCIE_SCRATCH 0x0041 |
| #define mmDN_PCIE_SCRATCH_BASE_IDX 2 |
| #define mmDN_PCIE_CNTL 0x0043 |
| #define mmDN_PCIE_CNTL_BASE_IDX 2 |
| #define mmDN_PCIE_CONFIG_CNTL 0x0044 |
| #define mmDN_PCIE_CONFIG_CNTL_BASE_IDX 2 |
| #define mmDN_PCIE_RX_CNTL2 0x0045 |
| #define mmDN_PCIE_RX_CNTL2_BASE_IDX 2 |
| #define mmDN_PCIE_BUS_CNTL 0x0046 |
| #define mmDN_PCIE_BUS_CNTL_BASE_IDX 2 |
| #define mmDN_PCIE_CFG_CNTL 0x0047 |
| #define mmDN_PCIE_CFG_CNTL_BASE_IDX 2 |
| |
| |
| // addressBlock: nbio_nbif0_rcc_dwnp_dev0_BIFDEC1 |
| // base address: 0x0 |
| #define mmPCIE_ERR_CNTL 0x004f |
| #define mmPCIE_ERR_CNTL_BASE_IDX 2 |
| #define mmPCIE_RX_CNTL 0x0050 |
| #define mmPCIE_RX_CNTL_BASE_IDX 2 |
| #define mmPCIE_LC_SPEED_CNTL 0x0051 |
| #define mmPCIE_LC_SPEED_CNTL_BASE_IDX 2 |
| #define mmPCIE_LC_CNTL2 0x0052 |
| #define mmPCIE_LC_CNTL2_BASE_IDX 2 |
| #define mmPCIEP_STRAP_MISC 0x0053 |
| #define mmPCIEP_STRAP_MISC_BASE_IDX 2 |
| #define mmLTR_MSG_INFO_FROM_EP 0x0054 |
| #define mmLTR_MSG_INFO_FROM_EP_BASE_IDX 2 |
| |
| |
| // addressBlock: nbio_nbif0_rcc_dev0_BIFPFVFDEC1 |
| // base address: 0x0 |
| #define mmRCC_ERR_LOG 0x0085 |
| #define mmRCC_ERR_LOG_BASE_IDX 2 |
| #define mmRCC_DOORBELL_APER_EN 0x00c0 |
| #define mmRCC_DOORBELL_APER_EN_BASE_IDX 2 |
| #define mmRCC_CONFIG_MEMSIZE 0x00c3 |
| #define mmRCC_CONFIG_MEMSIZE_BASE_IDX 2 |
| #define mmRCC_CONFIG_RESERVED 0x00c4 |
| #define mmRCC_CONFIG_RESERVED_BASE_IDX 2 |
| #define mmRCC_IOV_FUNC_IDENTIFIER 0x00c5 |
| #define mmRCC_IOV_FUNC_IDENTIFIER_BASE_IDX 2 |
| |
| |
| // addressBlock: nbio_nbif0_rcc_dev0_BIFDEC1 |
| // base address: 0x0 |
| #define mmRCC_ERR_INT_CNTL 0x0086 |
| #define mmRCC_ERR_INT_CNTL_BASE_IDX 2 |
| #define mmRCC_BACO_CNTL_MISC 0x0087 |
| #define mmRCC_BACO_CNTL_MISC_BASE_IDX 2 |
| #define mmRCC_RESET_EN 0x0088 |
| #define mmRCC_RESET_EN_BASE_IDX 2 |
| #define mmRCC_VDM_SUPPORT 0x0089 |
| #define mmRCC_VDM_SUPPORT_BASE_IDX 2 |
| #define mmRCC_PEER_REG_RANGE0 0x00be |
| #define mmRCC_PEER_REG_RANGE0_BASE_IDX 2 |
| #define mmRCC_PEER_REG_RANGE1 0x00bf |
| #define mmRCC_PEER_REG_RANGE1_BASE_IDX 2 |
| #define mmRCC_BUS_CNTL 0x00c1 |
| #define mmRCC_BUS_CNTL_BASE_IDX 2 |
| #define mmRCC_CONFIG_CNTL 0x00c2 |
| #define mmRCC_CONFIG_CNTL_BASE_IDX 2 |
| #define mmRCC_CONFIG_F0_BASE 0x00c6 |
| #define mmRCC_CONFIG_F0_BASE_BASE_IDX 2 |
| #define mmRCC_CONFIG_APER_SIZE 0x00c7 |
| #define mmRCC_CONFIG_APER_SIZE_BASE_IDX 2 |
| #define mmRCC_CONFIG_REG_APER_SIZE 0x00c8 |
| #define mmRCC_CONFIG_REG_APER_SIZE_BASE_IDX 2 |
| #define mmRCC_XDMA_LO 0x00c9 |
| #define mmRCC_XDMA_LO_BASE_IDX 2 |
| #define mmRCC_XDMA_HI 0x00ca |
| #define mmRCC_XDMA_HI_BASE_IDX 2 |
| #define mmRCC_FEATURES_CONTROL_MISC 0x00cb |
| #define mmRCC_FEATURES_CONTROL_MISC_BASE_IDX 2 |
| #define mmRCC_BUSNUM_CNTL1 0x00cc |
| #define mmRCC_BUSNUM_CNTL1_BASE_IDX 2 |
| #define mmRCC_BUSNUM_LIST0 0x00cd |
| #define mmRCC_BUSNUM_LIST0_BASE_IDX 2 |
| #define mmRCC_BUSNUM_LIST1 0x00ce |
| #define mmRCC_BUSNUM_LIST1_BASE_IDX 2 |
| #define mmRCC_BUSNUM_CNTL2 0x00cf |
| #define mmRCC_BUSNUM_CNTL2_BASE_IDX 2 |
| #define mmRCC_CAPTURE_HOST_BUSNUM 0x00d0 |
| #define mmRCC_CAPTURE_HOST_BUSNUM_BASE_IDX 2 |
| #define mmRCC_HOST_BUSNUM 0x00d1 |
| #define mmRCC_HOST_BUSNUM_BASE_IDX 2 |
| #define mmRCC_PEER0_FB_OFFSET_HI 0x00d2 |
| #define mmRCC_PEER0_FB_OFFSET_HI_BASE_IDX 2 |
| #define mmRCC_PEER0_FB_OFFSET_LO 0x00d3 |
| #define mmRCC_PEER0_FB_OFFSET_LO_BASE_IDX 2 |
| #define mmRCC_PEER1_FB_OFFSET_HI 0x00d4 |
| #define mmRCC_PEER1_FB_OFFSET_HI_BASE_IDX 2 |
| #define mmRCC_PEER1_FB_OFFSET_LO 0x00d5 |
| #define mmRCC_PEER1_FB_OFFSET_LO_BASE_IDX 2 |
| #define mmRCC_PEER2_FB_OFFSET_HI 0x00d6 |
| #define mmRCC_PEER2_FB_OFFSET_HI_BASE_IDX 2 |
| #define mmRCC_PEER2_FB_OFFSET_LO 0x00d7 |
| #define mmRCC_PEER2_FB_OFFSET_LO_BASE_IDX 2 |
| #define mmRCC_PEER3_FB_OFFSET_HI 0x00d8 |
| #define mmRCC_PEER3_FB_OFFSET_HI_BASE_IDX 2 |
| #define mmRCC_PEER3_FB_OFFSET_LO 0x00d9 |
| #define mmRCC_PEER3_FB_OFFSET_LO_BASE_IDX 2 |
| #define mmRCC_CMN_LINK_CNTL 0x00de |
| #define mmRCC_CMN_LINK_CNTL_BASE_IDX 2 |
| #define mmRCC_EP_REQUESTERID_RESTORE 0x00df |
| #define mmRCC_EP_REQUESTERID_RESTORE_BASE_IDX 2 |
| #define mmRCC_LTR_LSWITCH_CNTL 0x00e0 |
| #define mmRCC_LTR_LSWITCH_CNTL_BASE_IDX 2 |
| #define mmRCC_MH_ARB_CNTL 0x00e1 |
| #define mmRCC_MH_ARB_CNTL_BASE_IDX 2 |
| |
| |
| // addressBlock: nbio_nbif0_bif_bx_pf_BIFDEC1 |
| // base address: 0x0 |
| #define mmBIF_MM_INDACCESS_CNTL 0x00e6 |
| #define mmBIF_MM_INDACCESS_CNTL_BASE_IDX 2 |
| #define mmBUS_CNTL 0x00e7 |
| #define mmBUS_CNTL_BASE_IDX 2 |
| #define mmBIF_SCRATCH0 0x00e8 |
| #define mmBIF_SCRATCH0_BASE_IDX 2 |
| #define mmBIF_SCRATCH1 0x00e9 |
| #define mmBIF_SCRATCH1_BASE_IDX 2 |
| #define mmBX_RESET_EN 0x00ed |
| #define mmBX_RESET_EN_BASE_IDX 2 |
| #define mmMM_CFGREGS_CNTL 0x00ee |
| #define mmMM_CFGREGS_CNTL_BASE_IDX 2 |
| #define mmBX_RESET_CNTL 0x00f0 |
| #define mmBX_RESET_CNTL_BASE_IDX 2 |
| #define mmINTERRUPT_CNTL 0x00f1 |
| #define mmINTERRUPT_CNTL_BASE_IDX 2 |
| #define mmINTERRUPT_CNTL2 0x00f2 |
| #define mmINTERRUPT_CNTL2_BASE_IDX 2 |
| #define mmCLKREQB_PAD_CNTL 0x00f8 |
| #define mmCLKREQB_PAD_CNTL_BASE_IDX 2 |
| #define mmBIF_FEATURES_CONTROL_MISC 0x00fb |
| #define mmBIF_FEATURES_CONTROL_MISC_BASE_IDX 2 |
| #define mmBIF_DOORBELL_CNTL 0x00fc |
| #define mmBIF_DOORBELL_CNTL_BASE_IDX 2 |
| #define mmBIF_DOORBELL_INT_CNTL 0x00fd |
| #define mmBIF_DOORBELL_INT_CNTL_BASE_IDX 2 |
| #define mmBIF_FB_EN 0x00ff |
| #define mmBIF_FB_EN_BASE_IDX 2 |
| #define mmBIF_BUSY_DELAY_CNTR 0x0100 |
| #define mmBIF_BUSY_DELAY_CNTR_BASE_IDX 2 |
| #define mmBIF_MST_TRANS_PENDING_VF 0x0109 |
| #define mmBIF_MST_TRANS_PENDING_VF_BASE_IDX 2 |
| #define mmBIF_SLV_TRANS_PENDING_VF 0x010a |
| #define mmBIF_SLV_TRANS_PENDING_VF_BASE_IDX 2 |
| #define mmBACO_CNTL 0x010b |
| #define mmBACO_CNTL_BASE_IDX 2 |
| #define mmBIF_BACO_EXIT_TIME0 0x010c |
| #define mmBIF_BACO_EXIT_TIME0_BASE_IDX 2 |
| #define mmBIF_BACO_EXIT_TIMER1 0x010d |
| #define mmBIF_BACO_EXIT_TIMER1_BASE_IDX 2 |
| #define mmBIF_BACO_EXIT_TIMER2 0x010e |
| #define mmBIF_BACO_EXIT_TIMER2_BASE_IDX 2 |
| #define mmBIF_BACO_EXIT_TIMER3 0x010f |
| #define mmBIF_BACO_EXIT_TIMER3_BASE_IDX 2 |
| #define mmBIF_BACO_EXIT_TIMER4 0x0110 |
| #define mmBIF_BACO_EXIT_TIMER4_BASE_IDX 2 |
| #define mmMEM_TYPE_CNTL 0x0111 |
| #define mmMEM_TYPE_CNTL_BASE_IDX 2 |
| #define mmSMU_BIF_VDDGFX_PWR_STATUS 0x0113 |
| #define mmSMU_BIF_VDDGFX_PWR_STATUS_BASE_IDX 2 |
| #define mmBIF_VDDGFX_GFX0_LOWER 0x0114 |
| #define mmBIF_VDDGFX_GFX0_LOWER_BASE_IDX 2 |
| #define mmBIF_VDDGFX_GFX0_UPPER 0x0115 |
| #define mmBIF_VDDGFX_GFX0_UPPER_BASE_IDX 2 |
| #define mmBIF_VDDGFX_GFX1_LOWER 0x0116 |
| #define mmBIF_VDDGFX_GFX1_LOWER_BASE_IDX 2 |
| #define mmBIF_VDDGFX_GFX1_UPPER 0x0117 |
| #define mmBIF_VDDGFX_GFX1_UPPER_BASE_IDX 2 |
| #define mmBIF_VDDGFX_GFX2_LOWER 0x0118 |
| #define mmBIF_VDDGFX_GFX2_LOWER_BASE_IDX 2 |
| #define mmBIF_VDDGFX_GFX2_UPPER 0x0119 |
| #define mmBIF_VDDGFX_GFX2_UPPER_BASE_IDX 2 |
| #define mmBIF_VDDGFX_GFX3_LOWER 0x011a |
| #define mmBIF_VDDGFX_GFX3_LOWER_BASE_IDX 2 |
| #define mmBIF_VDDGFX_GFX3_UPPER 0x011b |
| #define mmBIF_VDDGFX_GFX3_UPPER_BASE_IDX 2 |
| #define mmBIF_VDDGFX_GFX4_LOWER 0x011c |
| #define mmBIF_VDDGFX_GFX4_LOWER_BASE_IDX 2 |
| #define mmBIF_VDDGFX_GFX4_UPPER 0x011d |
| #define mmBIF_VDDGFX_GFX4_UPPER_BASE_IDX 2 |
| #define mmBIF_VDDGFX_GFX5_LOWER 0x011e |
| #define mmBIF_VDDGFX_GFX5_LOWER_BASE_IDX 2 |
| #define mmBIF_VDDGFX_GFX5_UPPER 0x011f |
| #define mmBIF_VDDGFX_GFX5_UPPER_BASE_IDX 2 |
| #define mmBIF_VDDGFX_RSV1_LOWER 0x0120 |
| #define mmBIF_VDDGFX_RSV1_LOWER_BASE_IDX 2 |
| #define mmBIF_VDDGFX_RSV1_UPPER 0x0121 |
| #define mmBIF_VDDGFX_RSV1_UPPER_BASE_IDX 2 |
| #define mmBIF_VDDGFX_RSV2_LOWER 0x0122 |
| #define mmBIF_VDDGFX_RSV2_LOWER_BASE_IDX 2 |
| #define mmBIF_VDDGFX_RSV2_UPPER 0x0123 |
| #define mmBIF_VDDGFX_RSV2_UPPER_BASE_IDX 2 |
| #define mmBIF_VDDGFX_RSV3_LOWER 0x0124 |
| #define mmBIF_VDDGFX_RSV3_LOWER_BASE_IDX 2 |
| #define mmBIF_VDDGFX_RSV3_UPPER 0x0125 |
| #define mmBIF_VDDGFX_RSV3_UPPER_BASE_IDX 2 |
| #define mmBIF_VDDGFX_RSV4_LOWER 0x0126 |
| #define mmBIF_VDDGFX_RSV4_LOWER_BASE_IDX 2 |
| #define mmBIF_VDDGFX_RSV4_UPPER 0x0127 |
| #define mmBIF_VDDGFX_RSV4_UPPER_BASE_IDX 2 |
| #define mmBIF_VDDGFX_FB_CMP 0x0128 |
| #define mmBIF_VDDGFX_FB_CMP_BASE_IDX 2 |
| #define mmBIF_DOORBELL_GBLAPER1_LOWER 0x0129 |
| #define mmBIF_DOORBELL_GBLAPER1_LOWER_BASE_IDX 2 |
| #define mmBIF_DOORBELL_GBLAPER1_UPPER 0x012a |
| #define mmBIF_DOORBELL_GBLAPER1_UPPER_BASE_IDX 2 |
| #define mmBIF_DOORBELL_GBLAPER2_LOWER 0x012b |
| #define mmBIF_DOORBELL_GBLAPER2_LOWER_BASE_IDX 2 |
| #define mmBIF_DOORBELL_GBLAPER2_UPPER 0x012c |
| #define mmBIF_DOORBELL_GBLAPER2_UPPER_BASE_IDX 2 |
| #define mmREMAP_HDP_MEM_FLUSH_CNTL 0x012d |
| #define mmREMAP_HDP_MEM_FLUSH_CNTL_BASE_IDX 2 |
| #define mmREMAP_HDP_REG_FLUSH_CNTL 0x012e |
| #define mmREMAP_HDP_REG_FLUSH_CNTL_BASE_IDX 2 |
| #define mmBIF_RB_CNTL 0x012f |
| #define mmBIF_RB_CNTL_BASE_IDX 2 |
| #define mmBIF_RB_BASE 0x0130 |
| #define mmBIF_RB_BASE_BASE_IDX 2 |
| #define mmBIF_RB_RPTR 0x0131 |
| #define mmBIF_RB_RPTR_BASE_IDX 2 |
| #define mmBIF_RB_WPTR 0x0132 |
| #define mmBIF_RB_WPTR_BASE_IDX 2 |
| #define mmBIF_RB_WPTR_ADDR_HI 0x0133 |
| #define mmBIF_RB_WPTR_ADDR_HI_BASE_IDX 2 |
| #define mmBIF_RB_WPTR_ADDR_LO 0x0134 |
| #define mmBIF_RB_WPTR_ADDR_LO_BASE_IDX 2 |
| #define mmMAILBOX_INDEX 0x0135 |
| #define mmMAILBOX_INDEX_BASE_IDX 2 |
| #define mmBIF_UVD_GPUIOV_CFG_SIZE 0x0143 |
| #define mmBIF_UVD_GPUIOV_CFG_SIZE_BASE_IDX 2 |
| #define mmBIF_VCE_GPUIOV_CFG_SIZE 0x0144 |
| #define mmBIF_VCE_GPUIOV_CFG_SIZE_BASE_IDX 2 |
| #define mmBIF_GFX_SDMA_GPUIOV_CFG_SIZE 0x0145 |
| #define mmBIF_GFX_SDMA_GPUIOV_CFG_SIZE_BASE_IDX 2 |
| #define mmBIF_PERSTB_PAD_CNTL 0x0148 |
| #define mmBIF_PERSTB_PAD_CNTL_BASE_IDX 2 |
| #define mmBIF_PX_EN_PAD_CNTL 0x0149 |
| #define mmBIF_PX_EN_PAD_CNTL_BASE_IDX 2 |
| #define mmBIF_REFPADKIN_PAD_CNTL 0x014a |
| #define mmBIF_REFPADKIN_PAD_CNTL_BASE_IDX 2 |
| #define mmBIF_CLKREQB_PAD_CNTL 0x014b |
| #define mmBIF_CLKREQB_PAD_CNTL_BASE_IDX 2 |
| |
| |
| // addressBlock: nbio_nbif0_bif_bx_pf_BIFPFVFDEC1 |
| // base address: 0x0 |
| #define mmBIF_BME_STATUS 0x00eb |
| #define mmBIF_BME_STATUS_BASE_IDX 2 |
| #define mmBIF_ATOMIC_ERR_LOG 0x00ec |
| #define mmBIF_ATOMIC_ERR_LOG_BASE_IDX 2 |
| #define mmDOORBELL_SELFRING_GPA_APER_BASE_HIGH 0x00f3 |
| #define mmDOORBELL_SELFRING_GPA_APER_BASE_HIGH_BASE_IDX 2 |
| #define mmDOORBELL_SELFRING_GPA_APER_BASE_LOW 0x00f4 |
| #define mmDOORBELL_SELFRING_GPA_APER_BASE_LOW_BASE_IDX 2 |
| #define mmDOORBELL_SELFRING_GPA_APER_CNTL 0x00f5 |
| #define mmDOORBELL_SELFRING_GPA_APER_CNTL_BASE_IDX 2 |
| #define mmHDP_REG_COHERENCY_FLUSH_CNTL 0x00f6 |
| #define mmHDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX 2 |
| #define mmHDP_MEM_COHERENCY_FLUSH_CNTL 0x00f7 |
| #define mmHDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX 2 |
| #define mmGPU_HDP_FLUSH_REQ 0x0106 |
| #define mmGPU_HDP_FLUSH_REQ_BASE_IDX 2 |
| #define mmGPU_HDP_FLUSH_DONE 0x0107 |
| #define mmGPU_HDP_FLUSH_DONE_BASE_IDX 2 |
| #define mmBIF_TRANS_PENDING 0x0108 |
| #define mmBIF_TRANS_PENDING_BASE_IDX 2 |
| #define mmMAILBOX_MSGBUF_TRN_DW0 0x0136 |
| #define mmMAILBOX_MSGBUF_TRN_DW0_BASE_IDX 2 |
| #define mmMAILBOX_MSGBUF_TRN_DW1 0x0137 |
| #define mmMAILBOX_MSGBUF_TRN_DW1_BASE_IDX 2 |
| #define mmMAILBOX_MSGBUF_TRN_DW2 0x0138 |
| #define mmMAILBOX_MSGBUF_TRN_DW2_BASE_IDX 2 |
| #define mmMAILBOX_MSGBUF_TRN_DW3 0x0139 |
| #define mmMAILBOX_MSGBUF_TRN_DW3_BASE_IDX 2 |
| #define mmMAILBOX_MSGBUF_RCV_DW0 0x013a |
| #define mmMAILBOX_MSGBUF_RCV_DW0_BASE_IDX 2 |
| #define mmMAILBOX_MSGBUF_RCV_DW1 0x013b |
| #define mmMAILBOX_MSGBUF_RCV_DW1_BASE_IDX 2 |
| #define mmMAILBOX_MSGBUF_RCV_DW2 0x013c |
| #define mmMAILBOX_MSGBUF_RCV_DW2_BASE_IDX 2 |
| #define mmMAILBOX_MSGBUF_RCV_DW3 0x013d |
| #define mmMAILBOX_MSGBUF_RCV_DW3_BASE_IDX 2 |
| #define mmMAILBOX_CONTROL 0x013e |
| #define mmMAILBOX_CONTROL_BASE_IDX 2 |
| #define mmMAILBOX_INT_CNTL 0x013f |
| #define mmMAILBOX_INT_CNTL_BASE_IDX 2 |
| #define mmBIF_VMHV_MAILBOX 0x0140 |
| #define mmBIF_VMHV_MAILBOX_BASE_IDX 2 |
| |
| |
| // addressBlock: nbio_nbif0_gdc_GDCDEC |
| // base address: 0x0 |
| #define mmNGDC_SDP_PORT_CTRL 0x01c2 |
| #define mmNGDC_SDP_PORT_CTRL_BASE_IDX 2 |
| #define mmSHUB_REGS_IF_CTL 0x01c3 |
| #define mmSHUB_REGS_IF_CTL_BASE_IDX 2 |
| #define mmNGDC_RESERVED_0 0x01cb |
| #define mmNGDC_RESERVED_0_BASE_IDX 2 |
| #define mmNGDC_RESERVED_1 0x01cc |
| #define mmNGDC_RESERVED_1_BASE_IDX 2 |
| #define mmNGDC_SDP_PORT_CTRL_SOCCLK 0x01cd |
| #define mmNGDC_SDP_PORT_CTRL_SOCCLK_BASE_IDX 2 |
| #define mmBIF_SDMA0_DOORBELL_RANGE 0x01d0 |
| #define mmBIF_SDMA0_DOORBELL_RANGE_BASE_IDX 2 |
| #define mmBIF_SDMA1_DOORBELL_RANGE 0x01d1 |
| #define mmBIF_SDMA1_DOORBELL_RANGE_BASE_IDX 2 |
| #define mmBIF_IH_DOORBELL_RANGE 0x01d2 |
| #define mmBIF_IH_DOORBELL_RANGE_BASE_IDX 2 |
| #define mmBIF_MMSCH0_DOORBELL_RANGE 0x01d3 |
| #define mmBIF_MMSCH0_DOORBELL_RANGE_BASE_IDX 2 |
| #define mmATDMA_MISC_CNTL 0x01dd |
| #define mmATDMA_MISC_CNTL_BASE_IDX 2 |
| #define mmBIF_DOORBELL_FENCE_CNTL 0x01de |
| #define mmBIF_DOORBELL_FENCE_CNTL_BASE_IDX 2 |
| #define mmS2A_MISC_CNTL 0x01df |
| #define mmS2A_MISC_CNTL_BASE_IDX 2 |
| #define mmGDC_PG_MISC_CNTL 0x01f0 |
| #define mmGDC_PG_MISC_CNTL_BASE_IDX 2 |
| |
| |
| // addressBlock: nbio_nbif0_rcc_dev0_BIFDEC2 |
| // base address: 0x0 |
| #define mmGFXMSIX_VECT0_ADDR_LO 0x0400 |
| #define mmGFXMSIX_VECT0_ADDR_LO_BASE_IDX 3 |
| #define mmGFXMSIX_VECT0_ADDR_HI 0x0401 |
| #define mmGFXMSIX_VECT0_ADDR_HI_BASE_IDX 3 |
| #define mmGFXMSIX_VECT0_MSG_DATA 0x0402 |
| #define mmGFXMSIX_VECT0_MSG_DATA_BASE_IDX 3 |
| #define mmGFXMSIX_VECT0_CONTROL 0x0403 |
| #define mmGFXMSIX_VECT0_CONTROL_BASE_IDX 3 |
| #define mmGFXMSIX_VECT1_ADDR_LO 0x0404 |
| #define mmGFXMSIX_VECT1_ADDR_LO_BASE_IDX 3 |
| #define mmGFXMSIX_VECT1_ADDR_HI 0x0405 |
| #define mmGFXMSIX_VECT1_ADDR_HI_BASE_IDX 3 |
| #define mmGFXMSIX_VECT1_MSG_DATA 0x0406 |
| #define mmGFXMSIX_VECT1_MSG_DATA_BASE_IDX 3 |
| #define mmGFXMSIX_VECT1_CONTROL 0x0407 |
| #define mmGFXMSIX_VECT1_CONTROL_BASE_IDX 3 |
| #define mmGFXMSIX_VECT2_ADDR_LO 0x0408 |
| #define mmGFXMSIX_VECT2_ADDR_LO_BASE_IDX 3 |
| #define mmGFXMSIX_VECT2_ADDR_HI 0x0409 |
| #define mmGFXMSIX_VECT2_ADDR_HI_BASE_IDX 3 |
| #define mmGFXMSIX_VECT2_MSG_DATA 0x040a |
| #define mmGFXMSIX_VECT2_MSG_DATA_BASE_IDX 3 |
| #define mmGFXMSIX_VECT2_CONTROL 0x040b |
| #define mmGFXMSIX_VECT2_CONTROL_BASE_IDX 3 |
| #define mmGFXMSIX_PBA 0x0800 |
| #define mmGFXMSIX_PBA_BASE_IDX 3 |
| |
| |
| // addressBlock: syshub_mmreg_ind_syshubind |
| // base address: 0x0 |
| #define ixSYSHUB_MMREG_IND_SYSHUB_DS_CTRL_SOCCLK 0x10000 |
| #define ixSYSHUB_MMREG_IND_SYSHUB_DS_CTRL2_SOCCLK 0x10004 |
| #define ixSYSHUB_MMREG_IND_SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SOCCLK 0x10008 |
| #define ixSYSHUB_MMREG_IND_SYSHUB_BGEN_ENHANCEMENT_IMM_EN_SOCCLK 0x1000c |
| #define ixSYSHUB_MMREG_IND_DMA_CLK0_SW0_SYSHUB_QOS_CNTL 0x10010 |
| #define ixSYSHUB_MMREG_IND_DMA_CLK0_SW1_SYSHUB_QOS_CNTL 0x10014 |
| #define ixSYSHUB_MMREG_IND_DMA_CLK0_SW2_SYSHUB_QOS_CNTL 0x10018 |
| #define ixSYSHUB_MMREG_IND_DMA_CLK0_SW0_CL0_CNTL 0x1001c |
| #define ixSYSHUB_MMREG_IND_DMA_CLK0_SW0_CL1_CNTL 0x10020 |
| #define ixSYSHUB_MMREG_IND_DMA_CLK0_SW0_CL2_CNTL 0x10024 |
| #define ixSYSHUB_MMREG_IND_DMA_CLK0_SW0_CL3_CNTL 0x10028 |
| #define ixSYSHUB_MMREG_IND_DMA_CLK0_SW0_CL4_CNTL 0x1002c |
| #define ixSYSHUB_MMREG_IND_DMA_CLK0_SW0_CL5_CNTL 0x10030 |
| #define ixSYSHUB_MMREG_IND_DMA_CLK0_SW1_CL0_CNTL 0x10034 |
| #define ixSYSHUB_MMREG_IND_DMA_CLK0_SW2_CL0_CNTL 0x10038 |
| #define ixSYSHUB_MMREG_IND_HST_CLK0_SW0_CL0_CNTL 0x10100 |
| #define ixSYSHUB_MMREG_IND_HST_CLK0_SW0_CL1_CNTL 0x10104 |
| #define ixSYSHUB_MMREG_IND_HST_CLK0_SW0_CL2_CNTL 0x10108 |
| #define ixSYSHUB_MMREG_IND_HST_CLK0_SW1_CL0_CNTL 0x1010c |
| #define ixSYSHUB_MMREG_IND_HST_CLK0_SW1_CL1_CNTL 0x10110 |
| #define ixSYSHUB_MMREG_IND_HST_CLK0_SW1_CL2_CNTL 0x10114 |
| #define ixSYSHUB_MMREG_IND_HST_CLK0_SW1_CL3_CNTL 0x10118 |
| #define ixSYSHUB_MMREG_IND_HST_CLK0_SW1_CL4_CNTL 0x1011c |
| #define ixSYSHUB_MMREG_IND_SYSHUB_CG_CNTL 0x10300 |
| #define ixSYSHUB_MMREG_IND_SYSHUB_TRANS_IDLE 0x10308 |
| #define ixSYSHUB_MMREG_IND_SYSHUB_HP_TIMER 0x1030c |
| #define ixSYSHUB_MMREG_IND_SYSHUB_MGCG_CTRL_SOCCLK 0x10310 |
| #define ixSYSHUB_MMREG_IND_SYSUB_CPF_DOORBELL_RS_RESET 0x10314 |
| #define ixSYSHUB_MMREG_IND_SYSHUB_SCRATCH 0x10f00 |
| #define ixSYSHUB_MMREG_IND_SYSHUB_CL_MASK 0x10f04 |
| #define ixSYSHUB_MMREG_IND_SYSHUB_DS_CTRL_SHUBCLK 0x11000 |
| #define ixSYSHUB_MMREG_IND_SYSHUB_DS_CTRL2_SHUBCLK 0x11004 |
| #define ixSYSHUB_MMREG_IND_SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SHUBCLK 0x11008 |
| #define ixSYSHUB_MMREG_IND_SYSHUB_BGEN_ENHANCEMENT_IMM_EN_SHUBCLK 0x1100c |
| #define ixSYSHUB_MMREG_IND_DMA_CLK1_SW0_SYSHUB_QOS_CNTL 0x11010 |
| #define ixSYSHUB_MMREG_IND_DMA_CLK1_SW1_SYSHUB_QOS_CNTL 0x11014 |
| #define ixSYSHUB_MMREG_IND_DMA_CLK1_SW0_CL0_CNTL 0x11018 |
| #define ixSYSHUB_MMREG_IND_DMA_CLK1_SW0_CL1_CNTL 0x1101c |
| #define ixSYSHUB_MMREG_IND_DMA_CLK1_SW0_CL2_CNTL 0x11020 |
| #define ixSYSHUB_MMREG_IND_DMA_CLK1_SW0_CL3_CNTL 0x11024 |
| #define ixSYSHUB_MMREG_IND_DMA_CLK1_SW0_CL4_CNTL 0x11028 |
| #define ixSYSHUB_MMREG_IND_DMA_CLK1_SW1_CL0_CNTL 0x1102c |
| #define ixSYSHUB_MMREG_IND_DMA_CLK1_SW1_CL1_CNTL 0x11030 |
| #define ixSYSHUB_MMREG_IND_DMA_CLK1_SW1_CL2_CNTL 0x11034 |
| #define ixSYSHUB_MMREG_IND_DMA_CLK1_SW1_CL3_CNTL 0x11038 |
| #define ixSYSHUB_MMREG_IND_DMA_CLK1_SW1_CL4_CNTL 0x1103c |
| #define ixSYSHUB_MMREG_IND_SYSHUB_MGCG_CTRL_SHUBCLK 0x11040 |
| #define ixSYSHUB_MMREG_IND_NIC400_0_ASIB_0_FN_MOD 0x20108 |
| #define ixSYSHUB_MMREG_IND_NIC400_0_AMIB_0_FN_MOD_BM_ISS 0x30008 |
| #define ixSYSHUB_MMREG_IND_NIC400_0_AMIB_1_FN_MOD_BM_ISS 0x31008 |
| #define ixSYSHUB_MMREG_IND_NIC400_1_ASIB_0_FN_MOD 0x40108 |
| #define ixSYSHUB_MMREG_IND_NIC400_1_AMIB_0_FN_MOD 0x50008 |
| #define ixSYSHUB_MMREG_IND_NIC400_1_AMIB_1_FN_MOD 0x51008 |
| #define ixSYSHUB_MMREG_IND_NIC400_1_AMIB_2_FN_MOD 0x52008 |
| #define ixSYSHUB_MMREG_IND_NIC400_2_ASIB_0_FN_MOD 0x60108 |
| #define ixSYSHUB_MMREG_IND_NIC400_2_ASIB_1_FN_MOD 0x61108 |
| #define ixSYSHUB_MMREG_IND_NIC400_2_ASIB_2_FN_MOD 0x62108 |
| #define ixSYSHUB_MMREG_IND_NIC400_2_ASIB_3_FN_MOD 0x63108 |
| #define ixSYSHUB_MMREG_IND_NIC400_2_ASIB_4_FN_MOD 0x64108 |
| #define ixSYSHUB_MMREG_IND_NIC400_2_AMIB_0_FN_MOD_BM_ISS 0x70008 |
| #define ixSYSHUB_MMREG_IND_NIC400_5_ASIB_0_FN_MOD 0xc0108 |
| #define ixSYSHUB_MMREG_IND_NIC400_5_ASIB_1_FN_MOD 0xc1108 |
| #define ixSYSHUB_MMREG_IND_NIC400_5_ASIB_2_FN_MOD 0xc2108 |
| #define ixSYSHUB_MMREG_IND_NIC400_5_ASIB_3_FN_MOD 0xc3108 |
| #define ixSYSHUB_MMREG_IND_NIC400_5_ASIB_4_FN_MOD 0xc4108 |
| #define ixSYSHUB_MMREG_IND_NIC400_5_AMIB_0_FN_MOD 0xd0008 |
| #define ixSYSHUB_MMREG_IND_NIC400_4_ASIB_0_FN_MOD 0xe0108 |
| #define ixSYSHUB_MMREG_IND_NIC400_4_ASIB_1_FN_MOD 0xe1108 |
| #define ixSYSHUB_MMREG_IND_NIC400_4_AMIB_0_FN_MOD 0xf0008 |
| |
| #endif |
