| [ |
| { |
| "PublicDescription": "Demand Data Read requests that hit L2 cache.", |
| "EventCode": "0x24", |
| "Counter": "0,1,2,3", |
| "UMask": "0x1", |
| "EventName": "L2_RQSTS.DEMAND_DATA_RD_HIT", |
| "SampleAfterValue": "200003", |
| "BriefDescription": "Demand Data Read requests that hit L2 cache", |
| "CounterHTOff": "0,1,2,3,4,5,6,7" |
| }, |
| { |
| "PublicDescription": "Counts any demand and L1 HW prefetch data load requests to L2.", |
| "EventCode": "0x24", |
| "Counter": "0,1,2,3", |
| "UMask": "0x3", |
| "EventName": "L2_RQSTS.ALL_DEMAND_DATA_RD", |
| "SampleAfterValue": "200003", |
| "BriefDescription": "Demand Data Read requests", |
| "CounterHTOff": "0,1,2,3,4,5,6,7" |
| }, |
| { |
| "PublicDescription": "RFO requests that hit L2 cache.", |
| "EventCode": "0x24", |
| "Counter": "0,1,2,3", |
| "UMask": "0x4", |
| "EventName": "L2_RQSTS.RFO_HIT", |
| "SampleAfterValue": "200003", |
| "BriefDescription": "RFO requests that hit L2 cache", |
| "CounterHTOff": "0,1,2,3,4,5,6,7" |
| }, |
| { |
| "PublicDescription": "Counts the number of store RFO requests that miss the L2 cache.", |
| "EventCode": "0x24", |
| "Counter": "0,1,2,3", |
| "UMask": "0x8", |
| "EventName": "L2_RQSTS.RFO_MISS", |
| "SampleAfterValue": "200003", |
| "BriefDescription": "RFO requests that miss L2 cache", |
| "CounterHTOff": "0,1,2,3,4,5,6,7" |
| }, |
| { |
| "PublicDescription": "Counts all L2 store RFO requests.", |
| "EventCode": "0x24", |
| "Counter": "0,1,2,3", |
| "UMask": "0xc", |
| "EventName": "L2_RQSTS.ALL_RFO", |
| "SampleAfterValue": "200003", |
| "BriefDescription": "RFO requests to L2 cache", |
| "CounterHTOff": "0,1,2,3,4,5,6,7" |
| }, |
| { |
| "PublicDescription": "Number of instruction fetches that hit the L2 cache.", |
| "EventCode": "0x24", |
| "Counter": "0,1,2,3", |
| "UMask": "0x10", |
| "EventName": "L2_RQSTS.CODE_RD_HIT", |
| "SampleAfterValue": "200003", |
| "BriefDescription": "L2 cache hits when fetching instructions, code reads.", |
| "CounterHTOff": "0,1,2,3,4,5,6,7" |
| }, |
| { |
| "PublicDescription": "Number of instruction fetches that missed the L2 cache.", |
| "EventCode": "0x24", |
| "Counter": "0,1,2,3", |
| "UMask": "0x20", |
| "EventName": "L2_RQSTS.CODE_RD_MISS", |
| "SampleAfterValue": "200003", |
| "BriefDescription": "L2 cache misses when fetching instructions", |
| "CounterHTOff": "0,1,2,3,4,5,6,7" |
| }, |
| { |
| "PublicDescription": "Counts all L2 code requests.", |
| "EventCode": "0x24", |
| "Counter": "0,1,2,3", |
| "UMask": "0x30", |
| "EventName": "L2_RQSTS.ALL_CODE_RD", |
| "SampleAfterValue": "200003", |
| "BriefDescription": "L2 code requests", |
| "CounterHTOff": "0,1,2,3,4,5,6,7" |
| }, |
| { |
| "PublicDescription": "Counts all L2 HW prefetcher requests that hit L2.", |
| "EventCode": "0x24", |
| "Counter": "0,1,2,3", |
| "UMask": "0x40", |
| "EventName": "L2_RQSTS.PF_HIT", |
| "SampleAfterValue": "200003", |
| "BriefDescription": "Requests from the L2 hardware prefetchers that hit L2 cache", |
| "CounterHTOff": "0,1,2,3,4,5,6,7" |
| }, |
| { |
| "PublicDescription": "Counts all L2 HW prefetcher requests that missed L2.", |
| "EventCode": "0x24", |
| "Counter": "0,1,2,3", |
| "UMask": "0x80", |
| "EventName": "L2_RQSTS.PF_MISS", |
| "SampleAfterValue": "200003", |
| "BriefDescription": "Requests from the L2 hardware prefetchers that miss L2 cache", |
| "CounterHTOff": "0,1,2,3,4,5,6,7" |
| }, |
| { |
| "PublicDescription": "Counts all L2 HW prefetcher requests.", |
| "EventCode": "0x24", |
| "Counter": "0,1,2,3", |
| "UMask": "0xc0", |
| "EventName": "L2_RQSTS.ALL_PF", |
| "SampleAfterValue": "200003", |
| "BriefDescription": "Requests from L2 hardware prefetchers", |
| "CounterHTOff": "0,1,2,3,4,5,6,7" |
| }, |
| { |
| "PublicDescription": "RFOs that miss cache lines.", |
| "EventCode": "0x27", |
| "Counter": "0,1,2,3", |
| "UMask": "0x1", |
| "EventName": "L2_STORE_LOCK_RQSTS.MISS", |
| "SampleAfterValue": "200003", |
| "BriefDescription": "RFOs that miss cache lines", |
| "CounterHTOff": "0,1,2,3,4,5,6,7" |
| }, |
| { |
| "PublicDescription": "RFOs that hit cache lines in M state.", |
| "EventCode": "0x27", |
| "Counter": "0,1,2,3", |
| "UMask": "0x8", |
| "EventName": "L2_STORE_LOCK_RQSTS.HIT_M", |
| "SampleAfterValue": "200003", |
| "BriefDescription": "RFOs that hit cache lines in M state", |
| "CounterHTOff": "0,1,2,3,4,5,6,7" |
| }, |
| { |
| "PublicDescription": "RFOs that access cache lines in any state.", |
| "EventCode": "0x27", |
| "Counter": "0,1,2,3", |
| "UMask": "0xf", |
| "EventName": "L2_STORE_LOCK_RQSTS.ALL", |
| "SampleAfterValue": "200003", |
| "BriefDescription": "RFOs that access cache lines in any state", |
| "CounterHTOff": "0,1,2,3,4,5,6,7" |
| }, |
| { |
| "PublicDescription": "Not rejected writebacks that missed LLC.", |
| "EventCode": "0x28", |
| "Counter": "0,1,2,3", |
| "UMask": "0x1", |
| "EventName": "L2_L1D_WB_RQSTS.MISS", |
| "SampleAfterValue": "200003", |
| "BriefDescription": "Count the number of modified Lines evicted from L1 and missed L2. (Non-rejected WBs from the DCU.)", |
| "CounterHTOff": "0,1,2,3,4,5,6,7" |
| }, |
| { |
| "PublicDescription": "Not rejected writebacks from L1D to L2 cache lines in E state.", |
| "EventCode": "0x28", |
| "Counter": "0,1,2,3", |
| "UMask": "0x4", |
| "EventName": "L2_L1D_WB_RQSTS.HIT_E", |
| "SampleAfterValue": "200003", |
| "BriefDescription": "Not rejected writebacks from L1D to L2 cache lines in E state", |
| "CounterHTOff": "0,1,2,3,4,5,6,7" |
| }, |
| { |
| "PublicDescription": "Not rejected writebacks from L1D to L2 cache lines in M state.", |
| "EventCode": "0x28", |
| "Counter": "0,1,2,3", |
| "UMask": "0x8", |
| "EventName": "L2_L1D_WB_RQSTS.HIT_M", |
| "SampleAfterValue": "200003", |
| "BriefDescription": "Not rejected writebacks from L1D to L2 cache lines in M state", |
| "CounterHTOff": "0,1,2,3,4,5,6,7" |
| }, |
| { |
| "EventCode": "0x28", |
| "Counter": "0,1,2,3", |
| "UMask": "0xf", |
| "EventName": "L2_L1D_WB_RQSTS.ALL", |
| "SampleAfterValue": "200003", |
| "BriefDescription": "Not rejected writebacks from L1D to L2 cache lines in any state.", |
| "CounterHTOff": "0,1,2,3,4,5,6,7" |
| }, |
| { |
| "PublicDescription": "This event counts each cache miss condition for references to the last level cache.", |
| "EventCode": "0x2E", |
| "Counter": "0,1,2,3", |
| "UMask": "0x41", |
| "EventName": "LONGEST_LAT_CACHE.MISS", |
| "SampleAfterValue": "100003", |
| "BriefDescription": "Core-originated cacheable demand requests missed LLC", |
| "CounterHTOff": "0,1,2,3,4,5,6,7" |
| }, |
| { |
| "PublicDescription": "This event counts requests originating from the core that reference a cache line in the last level cache.", |
| "EventCode": "0x2E", |
| "Counter": "0,1,2,3", |
| "UMask": "0x4f", |
| "EventName": "LONGEST_LAT_CACHE.REFERENCE", |
| "SampleAfterValue": "100003", |
| "BriefDescription": "Core-originated cacheable demand requests that refer to LLC", |
| "CounterHTOff": "0,1,2,3,4,5,6,7" |
| }, |
| { |
| "PublicDescription": "Increments the number of outstanding L1D misses every cycle. Set Cmask = 1 and Edge =1 to count occurrences.", |
| "EventCode": "0x48", |
| "Counter": "2", |
| "UMask": "0x1", |
| "EventName": "L1D_PEND_MISS.PENDING", |
| "SampleAfterValue": "2000003", |
| "BriefDescription": "L1D miss oustandings duration in cycles", |
| "CounterHTOff": "2" |
| }, |
| { |
| "EventCode": "0x48", |
| "Counter": "2", |
| "UMask": "0x1", |
| "EventName": "L1D_PEND_MISS.PENDING_CYCLES", |
| "SampleAfterValue": "2000003", |
| "BriefDescription": "Cycles with L1D load Misses outstanding.", |
| "CounterMask": "1", |
| "CounterHTOff": "2" |
| }, |
| { |
| "PublicDescription": "Cycles with L1D load Misses outstanding from any thread on physical core.", |
| "EventCode": "0x48", |
| "Counter": "2", |
| "UMask": "0x1", |
| "AnyThread": "1", |
| "EventName": "L1D_PEND_MISS.PENDING_CYCLES_ANY", |
| "SampleAfterValue": "2000003", |
| "BriefDescription": "Cycles with L1D load Misses outstanding from any thread on physical core", |
| "CounterMask": "1", |
| "CounterHTOff": "2" |
| }, |
| { |
| "PublicDescription": "Cycles a demand request was blocked due to Fill Buffers inavailability.", |
| "EventCode": "0x48", |
| "Counter": "0,1,2,3", |
| "UMask": "0x2", |
| "EventName": "L1D_PEND_MISS.FB_FULL", |
| "SampleAfterValue": "2000003", |
| "BriefDescription": "Cycles a demand request was blocked due to Fill Buffers inavailability", |
| "CounterMask": "1", |
| "CounterHTOff": "0,1,2,3,4,5,6,7" |
| }, |
| { |
| "PublicDescription": "Counts the number of lines brought into the L1 data cache.", |
| "EventCode": "0x51", |
| "Counter": "0,1,2,3", |
| "UMask": "0x1", |
| "EventName": "L1D.REPLACEMENT", |
| "SampleAfterValue": "2000003", |
| "BriefDescription": "L1D data line replacements", |
| "CounterHTOff": "0,1,2,3,4,5,6,7" |
| }, |
| { |
| "PublicDescription": "Offcore outstanding Demand Data Read transactions in SQ to uncore. Set Cmask=1 to count cycles.", |
| "EventCode": "0x60", |
| "Counter": "0,1,2,3", |
| "UMask": "0x1", |
| "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD", |
| "SampleAfterValue": "2000003", |
| "BriefDescription": "Offcore outstanding Demand Data Read transactions in uncore queue.", |
| "CounterHTOff": "0,1,2,3,4,5,6,7" |
| }, |
| { |
| "PublicDescription": "Cycles when offcore outstanding Demand Data Read transactions are present in SuperQueue (SQ), queue to uncore.", |
| "EventCode": "0x60", |
| "Counter": "0,1,2,3", |
| "UMask": "0x1", |
| "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_DATA_RD", |
| "SampleAfterValue": "2000003", |
| "BriefDescription": "Cycles when offcore outstanding Demand Data Read transactions are present in SuperQueue (SQ), queue to uncore", |
| "CounterMask": "1", |
| "CounterHTOff": "0,1,2,3,4,5,6,7" |
| }, |
| { |
| "PublicDescription": "Cycles with at least 6 offcore outstanding Demand Data Read transactions in uncore queue.", |
| "EventCode": "0x60", |
| "Counter": "0,1,2,3", |
| "UMask": "0x1", |
| "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD_GE_6", |
| "SampleAfterValue": "2000003", |
| "BriefDescription": "Cycles with at least 6 offcore outstanding Demand Data Read transactions in uncore queue", |
| "CounterMask": "6", |
| "CounterHTOff": "0,1,2,3,4,5,6,7" |
| }, |
| { |
| "PublicDescription": "Offcore outstanding Demand Code Read transactions in SQ to uncore. Set Cmask=1 to count cycles.", |
| "EventCode": "0x60", |
| "Counter": "0,1,2,3", |
| "UMask": "0x2", |
| "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_CODE_RD", |
| "SampleAfterValue": "2000003", |
| "BriefDescription": "Offcore outstanding code reads transactions in SuperQueue (SQ), queue to uncore, every cycle", |
| "CounterHTOff": "0,1,2,3,4,5,6,7" |
| }, |
| { |
| "PublicDescription": "Offcore outstanding code reads transactions in SuperQueue (SQ), queue to uncore, every cycle.", |
| "EventCode": "0x60", |
| "Counter": "0,1,2,3", |
| "UMask": "0x2", |
| "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_CODE_RD", |
| "SampleAfterValue": "2000003", |
| "BriefDescription": "Offcore outstanding code reads transactions in SuperQueue (SQ), queue to uncore, every cycle", |
| "CounterMask": "1", |
| "CounterHTOff": "0,1,2,3,4,5,6,7" |
| }, |
| { |
| "PublicDescription": "Offcore outstanding RFO store transactions in SQ to uncore. Set Cmask=1 to count cycles.", |
| "EventCode": "0x60", |
| "Counter": "0,1,2,3", |
| "UMask": "0x4", |
| "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_RFO", |
| "SampleAfterValue": "2000003", |
| "BriefDescription": "Offcore outstanding RFO store transactions in SuperQueue (SQ), queue to uncore", |
| "CounterHTOff": "0,1,2,3,4,5,6,7" |
| }, |
| { |
| "PublicDescription": "Offcore outstanding demand rfo reads transactions in SuperQueue (SQ), queue to uncore, every cycle.", |
| "EventCode": "0x60", |
| "Counter": "0,1,2,3", |
| "UMask": "0x4", |
| "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO", |
| "SampleAfterValue": "2000003", |
| "BriefDescription": "Offcore outstanding demand rfo reads transactions in SuperQueue (SQ), queue to uncore, every cycle", |
| "CounterMask": "1", |
| "CounterHTOff": "0,1,2,3,4,5,6,7" |
| }, |
| { |
| "PublicDescription": "Offcore outstanding cacheable data read transactions in SQ to uncore. Set Cmask=1 to count cycles.", |
| "EventCode": "0x60", |
| "Counter": "0,1,2,3", |
| "UMask": "0x8", |
| "EventName": "OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD", |
| "SampleAfterValue": "2000003", |
| "BriefDescription": "Offcore outstanding cacheable Core Data Read transactions in SuperQueue (SQ), queue to uncore", |
| "CounterHTOff": "0,1,2,3,4,5,6,7" |
| }, |
| { |
| "PublicDescription": "Cycles when offcore outstanding cacheable Core Data Read transactions are present in SuperQueue (SQ), queue to uncore.", |
| "EventCode": "0x60", |
| "Counter": "0,1,2,3", |
| "UMask": "0x8", |
| "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD", |
| "SampleAfterValue": "2000003", |
| "BriefDescription": "Cycles when offcore outstanding cacheable Core Data Read transactions are present in SuperQueue (SQ), queue to uncore", |
| "CounterMask": "1", |
| "CounterHTOff": "0,1,2,3,4,5,6,7" |
| }, |
| { |
| "PublicDescription": "Cycles in which the L1D is locked.", |
| "EventCode": "0x63", |
| "Counter": "0,1,2,3", |
| "UMask": "0x2", |
| "EventName": "LOCK_CYCLES.CACHE_LOCK_DURATION", |
| "SampleAfterValue": "2000003", |
| "BriefDescription": "Cycles when L1D is locked", |
| "CounterHTOff": "0,1,2,3,4,5,6,7" |
| }, |
| { |
| "PublicDescription": "Demand data read requests sent to uncore.", |
| "EventCode": "0xB0", |
| "Counter": "0,1,2,3", |
| "UMask": "0x1", |
| "EventName": "OFFCORE_REQUESTS.DEMAND_DATA_RD", |
| "SampleAfterValue": "100003", |
| "BriefDescription": "Demand Data Read requests sent to uncore", |
| "CounterHTOff": "0,1,2,3,4,5,6,7" |
| }, |
| { |
| "PublicDescription": "Demand code read requests sent to uncore.", |
| "EventCode": "0xB0", |
| "Counter": "0,1,2,3", |
| "UMask": "0x2", |
| "EventName": "OFFCORE_REQUESTS.DEMAND_CODE_RD", |
| "SampleAfterValue": "100003", |
| "BriefDescription": "Cacheable and noncachaeble code read requests", |
| "CounterHTOff": "0,1,2,3,4,5,6,7" |
| }, |
| { |
| "PublicDescription": "Demand RFO read requests sent to uncore, including regular RFOs, locks, ItoM.", |
| "EventCode": "0xB0", |
| "Counter": "0,1,2,3", |
| "UMask": "0x4", |
| "EventName": "OFFCORE_REQUESTS.DEMAND_RFO", |
| "SampleAfterValue": "100003", |
| "BriefDescription": "Demand RFO requests including regular RFOs, locks, ItoM", |
| "CounterHTOff": "0,1,2,3,4,5,6,7" |
| }, |
| { |
| "PublicDescription": "Data read requests sent to uncore (demand and prefetch).", |
| "EventCode": "0xB0", |
| "Counter": "0,1,2,3", |
| "UMask": "0x8", |
| "EventName": "OFFCORE_REQUESTS.ALL_DATA_RD", |
| "SampleAfterValue": "100003", |
| "BriefDescription": "Demand and prefetch data reads", |
| "CounterHTOff": "0,1,2,3,4,5,6,7" |
| }, |
| { |
| "PublicDescription": "Cases when offcore requests buffer cannot take more entries for core.", |
| "EventCode": "0xB2", |
| "Counter": "0,1,2,3", |
| "UMask": "0x1", |
| "EventName": "OFFCORE_REQUESTS_BUFFER.SQ_FULL", |
| "SampleAfterValue": "2000003", |
| "BriefDescription": "Cases when offcore requests buffer cannot take more entries for core", |
| "CounterHTOff": "0,1,2,3,4,5,6,7" |
| }, |
| { |
| "PEBS": "1", |
| "EventCode": "0xD0", |
| "Counter": "0,1,2,3", |
| "UMask": "0x11", |
| "EventName": "MEM_UOPS_RETIRED.STLB_MISS_LOADS", |
| "SampleAfterValue": "100003", |
| "BriefDescription": "Retired load uops that miss the STLB. (Precise Event)", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "PEBS": "1", |
| "EventCode": "0xD0", |
| "Counter": "0,1,2,3", |
| "UMask": "0x12", |
| "EventName": "MEM_UOPS_RETIRED.STLB_MISS_STORES", |
| "SampleAfterValue": "100003", |
| "BriefDescription": "Retired store uops that miss the STLB. (Precise Event)", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "PEBS": "1", |
| "EventCode": "0xD0", |
| "Counter": "0,1,2,3", |
| "UMask": "0x21", |
| "EventName": "MEM_UOPS_RETIRED.LOCK_LOADS", |
| "SampleAfterValue": "100007", |
| "BriefDescription": "Retired load uops with locked access. (Precise Event)", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "PEBS": "1", |
| "EventCode": "0xD0", |
| "Counter": "0,1,2,3", |
| "UMask": "0x41", |
| "EventName": "MEM_UOPS_RETIRED.SPLIT_LOADS", |
| "SampleAfterValue": "100003", |
| "BriefDescription": "Retired load uops that split across a cacheline boundary. (Precise Event)", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "PEBS": "1", |
| "EventCode": "0xD0", |
| "Counter": "0,1,2,3", |
| "UMask": "0x42", |
| "EventName": "MEM_UOPS_RETIRED.SPLIT_STORES", |
| "SampleAfterValue": "100003", |
| "BriefDescription": "Retired store uops that split across a cacheline boundary. (Precise Event)", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "PEBS": "1", |
| "EventCode": "0xD0", |
| "Counter": "0,1,2,3", |
| "UMask": "0x81", |
| "EventName": "MEM_UOPS_RETIRED.ALL_LOADS", |
| "SampleAfterValue": "2000003", |
| "BriefDescription": "All retired load uops. (Precise Event)", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "PEBS": "1", |
| "EventCode": "0xD0", |
| "Counter": "0,1,2,3", |
| "UMask": "0x82", |
| "EventName": "MEM_UOPS_RETIRED.ALL_STORES", |
| "SampleAfterValue": "2000003", |
| "BriefDescription": "All retired store uops. (Precise Event)", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "PEBS": "1", |
| "EventCode": "0xD1", |
| "Counter": "0,1,2,3", |
| "UMask": "0x1", |
| "EventName": "MEM_LOAD_UOPS_RETIRED.L1_HIT", |
| "SampleAfterValue": "2000003", |
| "BriefDescription": "Retired load uops with L1 cache hits as data sources.", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "PEBS": "1", |
| "EventCode": "0xD1", |
| "Counter": "0,1,2,3", |
| "UMask": "0x2", |
| "EventName": "MEM_LOAD_UOPS_RETIRED.L2_HIT", |
| "SampleAfterValue": "100003", |
| "BriefDescription": "Retired load uops with L2 cache hits as data sources.", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "PEBS": "1", |
| "EventCode": "0xD1", |
| "Counter": "0,1,2,3", |
| "UMask": "0x4", |
| "EventName": "MEM_LOAD_UOPS_RETIRED.LLC_HIT", |
| "SampleAfterValue": "50021", |
| "BriefDescription": "Retired load uops which data sources were data hits in LLC without snoops required.", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "PEBS": "1", |
| "EventCode": "0xD1", |
| "Counter": "0,1,2,3", |
| "UMask": "0x8", |
| "EventName": "MEM_LOAD_UOPS_RETIRED.L1_MISS", |
| "SampleAfterValue": "100003", |
| "BriefDescription": "Retired load uops which data sources following L1 data-cache miss.", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "PEBS": "1", |
| "EventCode": "0xD1", |
| "Counter": "0,1,2,3", |
| "UMask": "0x10", |
| "EventName": "MEM_LOAD_UOPS_RETIRED.L2_MISS", |
| "SampleAfterValue": "50021", |
| "BriefDescription": "Retired load uops with L2 cache misses as data sources.", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "PEBS": "1", |
| "EventCode": "0xD1", |
| "Counter": "0,1,2,3", |
| "UMask": "0x20", |
| "EventName": "MEM_LOAD_UOPS_RETIRED.LLC_MISS", |
| "SampleAfterValue": "100007", |
| "BriefDescription": "Miss in last-level (L3) cache. Excludes Unknown data-source.", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "PEBS": "1", |
| "EventCode": "0xD1", |
| "Counter": "0,1,2,3", |
| "UMask": "0x40", |
| "EventName": "MEM_LOAD_UOPS_RETIRED.HIT_LFB", |
| "SampleAfterValue": "100003", |
| "BriefDescription": "Retired load uops which data sources were load uops missed L1 but hit FB due to preceding miss to the same cache line with data not ready.", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "PEBS": "1", |
| "EventCode": "0xD2", |
| "Counter": "0,1,2,3", |
| "UMask": "0x1", |
| "EventName": "MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_MISS", |
| "SampleAfterValue": "20011", |
| "BriefDescription": "Retired load uops which data sources were LLC hit and cross-core snoop missed in on-pkg core cache.", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "PEBS": "1", |
| "EventCode": "0xD2", |
| "Counter": "0,1,2,3", |
| "UMask": "0x2", |
| "EventName": "MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HIT", |
| "SampleAfterValue": "20011", |
| "BriefDescription": "Retired load uops which data sources were LLC and cross-core snoop hits in on-pkg core cache.", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "PEBS": "1", |
| "EventCode": "0xD2", |
| "Counter": "0,1,2,3", |
| "UMask": "0x4", |
| "EventName": "MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HITM", |
| "SampleAfterValue": "20011", |
| "BriefDescription": "Retired load uops which data sources were HitM responses from shared LLC.", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "PEBS": "1", |
| "EventCode": "0xD2", |
| "Counter": "0,1,2,3", |
| "UMask": "0x8", |
| "EventName": "MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_NONE", |
| "SampleAfterValue": "100003", |
| "BriefDescription": "Retired load uops which data sources were hits in LLC without snoops required.", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "PublicDescription": "Retired load uops whose data source was local memory (cross-socket snoop not needed or missed).", |
| "EventCode": "0xD3", |
| "Counter": "0,1,2,3", |
| "UMask": "0x1", |
| "EventName": "MEM_LOAD_UOPS_LLC_MISS_RETIRED.LOCAL_DRAM", |
| "SampleAfterValue": "100007", |
| "BriefDescription": "Retired load uops which data sources missed LLC but serviced from local dram.", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "PublicDescription": "Demand Data Read requests that access L2 cache.", |
| "EventCode": "0xF0", |
| "Counter": "0,1,2,3", |
| "UMask": "0x1", |
| "EventName": "L2_TRANS.DEMAND_DATA_RD", |
| "SampleAfterValue": "200003", |
| "BriefDescription": "Demand Data Read requests that access L2 cache", |
| "CounterHTOff": "0,1,2,3,4,5,6,7" |
| }, |
| { |
| "PublicDescription": "RFO requests that access L2 cache.", |
| "EventCode": "0xF0", |
| "Counter": "0,1,2,3", |
| "UMask": "0x2", |
| "EventName": "L2_TRANS.RFO", |
| "SampleAfterValue": "200003", |
| "BriefDescription": "RFO requests that access L2 cache", |
| "CounterHTOff": "0,1,2,3,4,5,6,7" |
| }, |
| { |
| "PublicDescription": "L2 cache accesses when fetching instructions.", |
| "EventCode": "0xF0", |
| "Counter": "0,1,2,3", |
| "UMask": "0x4", |
| "EventName": "L2_TRANS.CODE_RD", |
| "SampleAfterValue": "200003", |
| "BriefDescription": "L2 cache accesses when fetching instructions", |
| "CounterHTOff": "0,1,2,3,4,5,6,7" |
| }, |
| { |
| "PublicDescription": "Any MLC or LLC HW prefetch accessing L2, including rejects.", |
| "EventCode": "0xF0", |
| "Counter": "0,1,2,3", |
| "UMask": "0x8", |
| "EventName": "L2_TRANS.ALL_PF", |
| "SampleAfterValue": "200003", |
| "BriefDescription": "L2 or LLC HW prefetches that access L2 cache", |
| "CounterHTOff": "0,1,2,3,4,5,6,7" |
| }, |
| { |
| "PublicDescription": "L1D writebacks that access L2 cache.", |
| "EventCode": "0xF0", |
| "Counter": "0,1,2,3", |
| "UMask": "0x10", |
| "EventName": "L2_TRANS.L1D_WB", |
| "SampleAfterValue": "200003", |
| "BriefDescription": "L1D writebacks that access L2 cache", |
| "CounterHTOff": "0,1,2,3,4,5,6,7" |
| }, |
| { |
| "PublicDescription": "L2 fill requests that access L2 cache.", |
| "EventCode": "0xF0", |
| "Counter": "0,1,2,3", |
| "UMask": "0x20", |
| "EventName": "L2_TRANS.L2_FILL", |
| "SampleAfterValue": "200003", |
| "BriefDescription": "L2 fill requests that access L2 cache", |
| "CounterHTOff": "0,1,2,3,4,5,6,7" |
| }, |
| { |
| "PublicDescription": "L2 writebacks that access L2 cache.", |
| "EventCode": "0xF0", |
| "Counter": "0,1,2,3", |
| "UMask": "0x40", |
| "EventName": "L2_TRANS.L2_WB", |
| "SampleAfterValue": "200003", |
| "BriefDescription": "L2 writebacks that access L2 cache", |
| "CounterHTOff": "0,1,2,3,4,5,6,7" |
| }, |
| { |
| "PublicDescription": "Transactions accessing L2 pipe.", |
| "EventCode": "0xF0", |
| "Counter": "0,1,2,3", |
| "UMask": "0x80", |
| "EventName": "L2_TRANS.ALL_REQUESTS", |
| "SampleAfterValue": "200003", |
| "BriefDescription": "Transactions accessing L2 pipe", |
| "CounterHTOff": "0,1,2,3,4,5,6,7" |
| }, |
| { |
| "PublicDescription": "L2 cache lines in I state filling L2.", |
| "EventCode": "0xF1", |
| "Counter": "0,1,2,3", |
| "UMask": "0x1", |
| "EventName": "L2_LINES_IN.I", |
| "SampleAfterValue": "100003", |
| "BriefDescription": "L2 cache lines in I state filling L2", |
| "CounterHTOff": "0,1,2,3,4,5,6,7" |
| }, |
| { |
| "PublicDescription": "L2 cache lines in S state filling L2.", |
| "EventCode": "0xF1", |
| "Counter": "0,1,2,3", |
| "UMask": "0x2", |
| "EventName": "L2_LINES_IN.S", |
| "SampleAfterValue": "100003", |
| "BriefDescription": "L2 cache lines in S state filling L2", |
| "CounterHTOff": "0,1,2,3,4,5,6,7" |
| }, |
| { |
| "PublicDescription": "L2 cache lines in E state filling L2.", |
| "EventCode": "0xF1", |
| "Counter": "0,1,2,3", |
| "UMask": "0x4", |
| "EventName": "L2_LINES_IN.E", |
| "SampleAfterValue": "100003", |
| "BriefDescription": "L2 cache lines in E state filling L2", |
| "CounterHTOff": "0,1,2,3,4,5,6,7" |
| }, |
| { |
| "PublicDescription": "L2 cache lines filling L2.", |
| "EventCode": "0xF1", |
| "Counter": "0,1,2,3", |
| "UMask": "0x7", |
| "EventName": "L2_LINES_IN.ALL", |
| "SampleAfterValue": "100003", |
| "BriefDescription": "L2 cache lines filling L2", |
| "CounterHTOff": "0,1,2,3,4,5,6,7" |
| }, |
| { |
| "PublicDescription": "Clean L2 cache lines evicted by demand.", |
| "EventCode": "0xF2", |
| "Counter": "0,1,2,3", |
| "UMask": "0x1", |
| "EventName": "L2_LINES_OUT.DEMAND_CLEAN", |
| "SampleAfterValue": "100003", |
| "BriefDescription": "Clean L2 cache lines evicted by demand", |
| "CounterHTOff": "0,1,2,3,4,5,6,7" |
| }, |
| { |
| "PublicDescription": "Dirty L2 cache lines evicted by demand.", |
| "EventCode": "0xF2", |
| "Counter": "0,1,2,3", |
| "UMask": "0x2", |
| "EventName": "L2_LINES_OUT.DEMAND_DIRTY", |
| "SampleAfterValue": "100003", |
| "BriefDescription": "Dirty L2 cache lines evicted by demand", |
| "CounterHTOff": "0,1,2,3,4,5,6,7" |
| }, |
| { |
| "PublicDescription": "Clean L2 cache lines evicted by the MLC prefetcher.", |
| "EventCode": "0xF2", |
| "Counter": "0,1,2,3", |
| "UMask": "0x4", |
| "EventName": "L2_LINES_OUT.PF_CLEAN", |
| "SampleAfterValue": "100003", |
| "BriefDescription": "Clean L2 cache lines evicted by L2 prefetch", |
| "CounterHTOff": "0,1,2,3,4,5,6,7" |
| }, |
| { |
| "PublicDescription": "Dirty L2 cache lines evicted by the MLC prefetcher.", |
| "EventCode": "0xF2", |
| "Counter": "0,1,2,3", |
| "UMask": "0x8", |
| "EventName": "L2_LINES_OUT.PF_DIRTY", |
| "SampleAfterValue": "100003", |
| "BriefDescription": "Dirty L2 cache lines evicted by L2 prefetch", |
| "CounterHTOff": "0,1,2,3,4,5,6,7" |
| }, |
| { |
| "PublicDescription": "Dirty L2 cache lines filling the L2.", |
| "EventCode": "0xF2", |
| "Counter": "0,1,2,3", |
| "UMask": "0xa", |
| "EventName": "L2_LINES_OUT.DIRTY_ALL", |
| "SampleAfterValue": "100003", |
| "BriefDescription": "Dirty L2 cache lines filling the L2", |
| "CounterHTOff": "0,1,2,3,4,5,6,7" |
| }, |
| { |
| "EventCode": "0xF4", |
| "Counter": "0,1,2,3", |
| "UMask": "0x10", |
| "EventName": "SQ_MISC.SPLIT_LOCK", |
| "SampleAfterValue": "100003", |
| "BriefDescription": "Split locks in SQ", |
| "CounterHTOff": "0,1,2,3,4,5,6,7" |
| }, |
| { |
| "EventCode": "0xB7, 0xBB", |
| "MSRValue": "0x3f803c0244", |
| "Counter": "0,1,2,3", |
| "UMask": "0x1", |
| "Offcore": "1", |
| "EventName": "OFFCORE_RESPONSE.ALL_CODE_RD.LLC_HIT.ANY_RESPONSE", |
| "MSRIndex": "0x1a6,0x1a7", |
| "SampleAfterValue": "100003", |
| "BriefDescription": "Counts all demand & prefetch code reads that hit in the LLC", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "EventCode": "0xB7, 0xBB", |
| "MSRValue": "0x1003c0244", |
| "Counter": "0,1,2,3", |
| "UMask": "0x1", |
| "Offcore": "1", |
| "EventName": "OFFCORE_RESPONSE.ALL_CODE_RD.LLC_HIT.NO_SNOOP_NEEDED", |
| "MSRIndex": "0x1a6,0x1a7", |
| "SampleAfterValue": "100003", |
| "BriefDescription": "Counts demand & prefetch code reads that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "EventCode": "0xB7, 0xBB", |
| "MSRValue": "0x3f803c0091", |
| "Counter": "0,1,2,3", |
| "UMask": "0x1", |
| "Offcore": "1", |
| "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_HIT.ANY_RESPONSE", |
| "MSRIndex": "0x1a6,0x1a7", |
| "SampleAfterValue": "100003", |
| "BriefDescription": "Counts all demand & prefetch data reads that hit in the LLC", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "EventCode": "0xB7, 0xBB", |
| "MSRValue": "0x4003c0091", |
| "Counter": "0,1,2,3", |
| "UMask": "0x1", |
| "Offcore": "1", |
| "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_HIT.HIT_OTHER_CORE_NO_FWD", |
| "MSRIndex": "0x1a6,0x1a7", |
| "SampleAfterValue": "100003", |
| "BriefDescription": "Counts demand & prefetch data reads that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "EventCode": "0xB7, 0xBB", |
| "MSRValue": "0x10003c0091", |
| "Counter": "0,1,2,3", |
| "UMask": "0x1", |
| "Offcore": "1", |
| "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_HIT.HITM_OTHER_CORE", |
| "MSRIndex": "0x1a6,0x1a7", |
| "SampleAfterValue": "100003", |
| "BriefDescription": "Counts demand & prefetch data reads that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "EventCode": "0xB7, 0xBB", |
| "MSRValue": "0x1003c0091", |
| "Counter": "0,1,2,3", |
| "UMask": "0x1", |
| "Offcore": "1", |
| "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_HIT.NO_SNOOP_NEEDED", |
| "MSRIndex": "0x1a6,0x1a7", |
| "SampleAfterValue": "100003", |
| "BriefDescription": "Counts demand & prefetch data reads that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "EventCode": "0xB7, 0xBB", |
| "MSRValue": "0x3f803c0122", |
| "Counter": "0,1,2,3", |
| "UMask": "0x1", |
| "Offcore": "1", |
| "EventName": "OFFCORE_RESPONSE.ALL_RFO.LLC_HIT.ANY_RESPONSE", |
| "MSRIndex": "0x1a6,0x1a7", |
| "SampleAfterValue": "100003", |
| "BriefDescription": "Counts all demand & prefetch RFOs that hit in the LLC", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "EventCode": "0xB7, 0xBB", |
| "MSRValue": "0x1003c0122", |
| "Counter": "0,1,2,3", |
| "UMask": "0x1", |
| "Offcore": "1", |
| "EventName": "OFFCORE_RESPONSE.ALL_RFO.LLC_HIT.NO_SNOOP_NEEDED", |
| "MSRIndex": "0x1a6,0x1a7", |
| "SampleAfterValue": "100003", |
| "BriefDescription": "Counts demand & prefetch RFOs that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "EventCode": "0xB7, 0xBB", |
| "MSRValue": "0x10008", |
| "Counter": "0,1,2,3", |
| "UMask": "0x1", |
| "Offcore": "1", |
| "EventName": "OFFCORE_RESPONSE.COREWB.ANY_RESPONSE", |
| "MSRIndex": "0x1a6,0x1a7", |
| "SampleAfterValue": "100003", |
| "BriefDescription": "Counts all writebacks from the core to the LLC", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "EventCode": "0xB7, 0xBB", |
| "MSRValue": "0x3f803c0004", |
| "Counter": "0,1,2,3", |
| "UMask": "0x1", |
| "Offcore": "1", |
| "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.LLC_HIT.ANY_RESPONSE", |
| "MSRIndex": "0x1a6,0x1a7", |
| "SampleAfterValue": "100003", |
| "BriefDescription": "Counts all demand code reads that hit in the LLC", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "EventCode": "0xB7, 0xBB", |
| "MSRValue": "0x1003c0004", |
| "Counter": "0,1,2,3", |
| "UMask": "0x1", |
| "Offcore": "1", |
| "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.LLC_HIT.NO_SNOOP_NEEDED", |
| "MSRIndex": "0x1a6,0x1a7", |
| "SampleAfterValue": "100003", |
| "BriefDescription": "Counts demand code reads that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "EventCode": "0xB7, 0xBB", |
| "MSRValue": "0x3f803c0001", |
| "Counter": "0,1,2,3", |
| "UMask": "0x1", |
| "Offcore": "1", |
| "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT.ANY_RESPONSE", |
| "MSRIndex": "0x1a6,0x1a7", |
| "SampleAfterValue": "100003", |
| "BriefDescription": "Counts all demand data reads that hit in the LLC", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "EventCode": "0xB7, 0xBB", |
| "MSRValue": "0x4003c0001", |
| "Counter": "0,1,2,3", |
| "UMask": "0x1", |
| "Offcore": "1", |
| "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT.HIT_OTHER_CORE_NO_FWD", |
| "MSRIndex": "0x1a6,0x1a7", |
| "SampleAfterValue": "100003", |
| "BriefDescription": "Counts demand data reads that hit in the LLC and the snoops to sibling cores hit in either E/S state and the line is not forwarded", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "EventCode": "0xB7, 0xBB", |
| "MSRValue": "0x10003c0001", |
| "Counter": "0,1,2,3", |
| "UMask": "0x1", |
| "Offcore": "1", |
| "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT.HITM_OTHER_CORE", |
| "MSRIndex": "0x1a6,0x1a7", |
| "SampleAfterValue": "100003", |
| "BriefDescription": "Counts demand data reads that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "EventCode": "0xB7, 0xBB", |
| "MSRValue": "0x1003c0001", |
| "Counter": "0,1,2,3", |
| "UMask": "0x1", |
| "Offcore": "1", |
| "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT.NO_SNOOP_NEEDED", |
| "MSRIndex": "0x1a6,0x1a7", |
| "SampleAfterValue": "100003", |
| "BriefDescription": "Counts demand data reads that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "EventCode": "0xB7, 0xBB", |
| "MSRValue": "0x3f803c0002", |
| "Counter": "0,1,2,3", |
| "UMask": "0x1", |
| "Offcore": "1", |
| "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_HIT.ANY_RESPONSE", |
| "MSRIndex": "0x1a6,0x1a7", |
| "SampleAfterValue": "100003", |
| "BriefDescription": "Counts all demand data writes (RFOs) that hit in the LLC", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "EventCode": "0xB7, 0xBB", |
| "MSRValue": "0x10003c0002", |
| "Counter": "0,1,2,3", |
| "UMask": "0x1", |
| "Offcore": "1", |
| "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_HIT.HITM_OTHER_CORE", |
| "MSRIndex": "0x1a6,0x1a7", |
| "SampleAfterValue": "100003", |
| "BriefDescription": "Counts demand data writes (RFOs) that hit in the LLC and the snoop to one of the sibling cores hits the line in M state and the line is forwarded", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "EventCode": "0xB7, 0xBB", |
| "MSRValue": "0x1003c0002", |
| "Counter": "0,1,2,3", |
| "UMask": "0x1", |
| "Offcore": "1", |
| "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_HIT.NO_SNOOP_NEEDED", |
| "MSRIndex": "0x1a6,0x1a7", |
| "SampleAfterValue": "100003", |
| "BriefDescription": "Counts demand data writes (RFOs) that hit in the LLC and sibling core snoops are not needed as either the core-valid bit is not set or the shared line is present in multiple cores", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "EventCode": "0xB7, 0xBB", |
| "MSRValue": "0x18000", |
| "Counter": "0,1,2,3", |
| "UMask": "0x1", |
| "Offcore": "1", |
| "EventName": "OFFCORE_RESPONSE.OTHER.ANY_RESPONSE", |
| "MSRIndex": "0x1a6,0x1a7", |
| "SampleAfterValue": "100003", |
| "BriefDescription": "Counts miscellaneous accesses that include port i/o, MMIO and uncacheable memory accesses. It also includes L2 hints sent to LLC to keep a line from being evicted out of the core caches", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "EventCode": "0xB7, 0xBB", |
| "MSRValue": "0x10400", |
| "Counter": "0,1,2,3", |
| "UMask": "0x1", |
| "Offcore": "1", |
| "EventName": "OFFCORE_RESPONSE.SPLIT_LOCK_UC_LOCK.ANY_RESPONSE", |
| "MSRIndex": "0x1a6,0x1a7", |
| "SampleAfterValue": "100003", |
| "BriefDescription": "Counts requests where the address of an atomic lock instruction spans a cache line boundary or the lock instruction is executed on uncacheable address ", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "EventCode": "0xB7, 0xBB", |
| "MSRValue": "0x10800", |
| "Counter": "0,1,2,3", |
| "UMask": "0x1", |
| "Offcore": "1", |
| "EventName": "OFFCORE_RESPONSE.STREAMING_STORES.ANY_RESPONSE", |
| "MSRIndex": "0x1a6,0x1a7", |
| "SampleAfterValue": "100003", |
| "BriefDescription": "Counts non-temporal stores", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "EventCode": "0xB7, 0xBB", |
| "MSRValue": "0x00010001", |
| "Counter": "0,1,2,3", |
| "UMask": "0x1", |
| "Offcore": "1", |
| "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.ANY_RESPONSE", |
| "MSRIndex": "0x1a6,0x1a7", |
| "SampleAfterValue": "100003", |
| "BriefDescription": "Counts all demand data reads ", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "EventCode": "0xB7, 0xBB", |
| "MSRValue": "0x00010002", |
| "Counter": "0,1,2,3", |
| "UMask": "0x1", |
| "Offcore": "1", |
| "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.ANY_RESPONSE", |
| "MSRIndex": "0x1a6,0x1a7", |
| "SampleAfterValue": "100003", |
| "BriefDescription": "Counts all demand rfo's ", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "EventCode": "0xB7, 0xBB", |
| "MSRValue": "0x00010004", |
| "Counter": "0,1,2,3", |
| "UMask": "0x1", |
| "Offcore": "1", |
| "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.ANY_RESPONSE", |
| "MSRIndex": "0x1a6,0x1a7", |
| "SampleAfterValue": "100003", |
| "BriefDescription": "Counts all demand code reads", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "EventCode": "0xB7, 0xBB", |
| "MSRValue": "0x000105B3", |
| "Counter": "0,1,2,3", |
| "UMask": "0x1", |
| "Offcore": "1", |
| "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.ANY_RESPONSE", |
| "MSRIndex": "0x1a6,0x1a7", |
| "SampleAfterValue": "100003", |
| "BriefDescription": "Counts all demand & prefetch data reads", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "EventCode": "0xB7, 0xBB", |
| "MSRValue": "0x00010122", |
| "Counter": "0,1,2,3", |
| "UMask": "0x1", |
| "Offcore": "1", |
| "EventName": "OFFCORE_RESPONSE.ALL_RFO.ANY_RESPONSE", |
| "MSRIndex": "0x1a6,0x1a7", |
| "SampleAfterValue": "100003", |
| "BriefDescription": "Counts all demand & prefetch prefetch RFOs ", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "EventCode": "0xB7, 0xBB", |
| "MSRValue": "0x000107F7", |
| "Counter": "0,1,2,3", |
| "UMask": "0x1", |
| "Offcore": "1", |
| "EventName": "OFFCORE_RESPONSE.ALL_READS.ANY_RESPONSE", |
| "MSRIndex": "0x1a6,0x1a7", |
| "SampleAfterValue": "100003", |
| "BriefDescription": "Counts all data/code/rfo references (demand & prefetch) ", |
| "CounterHTOff": "0,1,2,3" |
| } |
| ] |
