| // SPDX-License-Identifier: (GPL-2.0+ OR MIT) |
| /* |
| * Copyright 2019 NXP |
| */ |
| |
| /dts-v1/; |
| |
| #include "imx8mn.dtsi" |
| |
| / { |
| model = "NXP i.MX8MNano DDR4 EVK board"; |
| compatible = "fsl,imx8mn-ddr4-evk", "fsl,imx8mn"; |
| |
| chosen { |
| stdout-path = &uart2; |
| }; |
| |
| reg_usdhc2_vmmc: regulator-usdhc2 { |
| compatible = "regulator-fixed"; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>; |
| regulator-name = "VSD_3V3"; |
| regulator-min-microvolt = <3300000>; |
| regulator-max-microvolt = <3300000>; |
| gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>; |
| enable-active-high; |
| }; |
| }; |
| |
| &A53_0 { |
| cpu-supply = <&buck2_reg>; |
| }; |
| |
| &iomuxc { |
| pinctrl-names = "default"; |
| |
| pinctrl_fec1: fec1grp { |
| fsl,pins = < |
| MX8MN_IOMUXC_ENET_MDC_ENET1_MDC 0x3 |
| MX8MN_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3 |
| MX8MN_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f |
| MX8MN_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f |
| MX8MN_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f |
| MX8MN_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f |
| MX8MN_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91 |
| MX8MN_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91 |
| MX8MN_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91 |
| MX8MN_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91 |
| MX8MN_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f |
| MX8MN_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91 |
| MX8MN_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91 |
| MX8MN_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f |
| MX8MN_IOMUXC_SAI2_RXC_GPIO4_IO22 0x19 |
| >; |
| }; |
| |
| pinctrl_i2c1: i2c1grp { |
| fsl,pins = < |
| MX8MN_IOMUXC_I2C1_SCL_I2C1_SCL 0x400001c3 |
| MX8MN_IOMUXC_I2C1_SDA_I2C1_SDA 0x400001c3 |
| >; |
| }; |
| |
| pinctrl_pmic: pmicirq { |
| fsl,pins = < |
| MX8MN_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x41 |
| >; |
| }; |
| |
| pinctrl_reg_usdhc2_vmmc: regusdhc2vmmc { |
| fsl,pins = < |
| MX8MN_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x41 |
| >; |
| }; |
| |
| pinctrl_uart2: uart2grp { |
| fsl,pins = < |
| MX8MN_IOMUXC_UART2_RXD_UART2_DCE_RX 0x140 |
| MX8MN_IOMUXC_UART2_TXD_UART2_DCE_TX 0x140 |
| >; |
| }; |
| |
| pinctrl_usdhc2_gpio: usdhc2grpgpio { |
| fsl,pins = < |
| MX8MN_IOMUXC_GPIO1_IO15_GPIO1_IO15 0x1c4 |
| >; |
| }; |
| |
| pinctrl_usdhc2: usdhc2grp { |
| fsl,pins = < |
| MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK 0x190 |
| MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d0 |
| MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d0 |
| MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0 |
| MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0 |
| MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0 |
| MX8MN_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 |
| >; |
| }; |
| |
| pinctrl_usdhc2_100mhz: usdhc2grp100mhz { |
| fsl,pins = < |
| MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK 0x194 |
| MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4 |
| MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4 |
| MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4 |
| MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4 |
| MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4 |
| MX8MN_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 |
| >; |
| }; |
| |
| pinctrl_usdhc2_200mhz: usdhc2grp200mhz { |
| fsl,pins = < |
| MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK 0x196 |
| MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6 |
| MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6 |
| MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6 |
| MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6 |
| MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6 |
| MX8MN_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 |
| >; |
| }; |
| |
| pinctrl_usdhc3: usdhc3grp { |
| fsl,pins = < |
| MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK 0x40000190 |
| MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d0 |
| MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d0 |
| MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d0 |
| MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d0 |
| MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d0 |
| MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d0 |
| MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d0 |
| MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d0 |
| MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d0 |
| MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x190 |
| >; |
| }; |
| |
| pinctrl_usdhc3_100mhz: usdhc3grp100mhz { |
| fsl,pins = < |
| MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK 0x40000194 |
| MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d4 |
| MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d4 |
| MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d4 |
| MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d4 |
| MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d4 |
| MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d4 |
| MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d4 |
| MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d4 |
| MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d4 |
| MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x194 |
| >; |
| }; |
| |
| pinctrl_usdhc3_200mhz: usdhc3grp200mhz { |
| fsl,pins = < |
| MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK 0x40000196 |
| MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d6 |
| MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d6 |
| MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d6 |
| MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d6 |
| MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d6 |
| MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d6 |
| MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d6 |
| MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d6 |
| MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d6 |
| MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x196 |
| >; |
| }; |
| |
| pinctrl_wdog: wdoggrp { |
| fsl,pins = < |
| MX8MN_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6 |
| >; |
| }; |
| }; |
| |
| &fec1 { |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_fec1>; |
| phy-mode = "rgmii-id"; |
| phy-handle = <ðphy0>; |
| fsl,magic-packet; |
| status = "okay"; |
| |
| mdio { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| |
| ethphy0: ethernet-phy@0 { |
| compatible = "ethernet-phy-ieee802.3-c22"; |
| reg = <0>; |
| at803x,led-act-blind-workaround; |
| at803x,eee-disabled; |
| at803x,vddio-1p8v; |
| }; |
| }; |
| }; |
| |
| &i2c1 { |
| clock-frequency = <400000>; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_i2c1>; |
| status = "okay"; |
| |
| pmic@4b { |
| compatible = "rohm,bd71847"; |
| reg = <0x4b>; |
| pinctrl-0 = <&pinctrl_pmic>; |
| interrupt-parent = <&gpio1>; |
| interrupts = <3 GPIO_ACTIVE_LOW>; |
| rohm,reset-snvs-powered; |
| |
| regulators { |
| buck1_reg: BUCK1 { |
| regulator-name = "BUCK1"; |
| regulator-min-microvolt = <700000>; |
| regulator-max-microvolt = <1300000>; |
| regulator-boot-on; |
| regulator-always-on; |
| regulator-ramp-delay = <1250>; |
| }; |
| |
| buck2_reg: BUCK2 { |
| regulator-name = "BUCK2"; |
| regulator-min-microvolt = <700000>; |
| regulator-max-microvolt = <1300000>; |
| regulator-boot-on; |
| regulator-always-on; |
| regulator-ramp-delay = <1250>; |
| }; |
| |
| buck3_reg: BUCK3 { |
| // BUCK5 in datasheet |
| regulator-name = "BUCK3"; |
| regulator-min-microvolt = <700000>; |
| regulator-max-microvolt = <1350000>; |
| }; |
| |
| buck4_reg: BUCK4 { |
| // BUCK6 in datasheet |
| regulator-name = "BUCK4"; |
| regulator-min-microvolt = <3000000>; |
| regulator-max-microvolt = <3300000>; |
| regulator-boot-on; |
| regulator-always-on; |
| }; |
| |
| buck5_reg: BUCK5 { |
| // BUCK7 in datasheet |
| regulator-name = "BUCK5"; |
| regulator-min-microvolt = <1605000>; |
| regulator-max-microvolt = <1995000>; |
| regulator-boot-on; |
| regulator-always-on; |
| }; |
| |
| buck6_reg: BUCK6 { |
| // BUCK8 in datasheet |
| regulator-name = "BUCK6"; |
| regulator-min-microvolt = <800000>; |
| regulator-max-microvolt = <1400000>; |
| regulator-boot-on; |
| regulator-always-on; |
| }; |
| |
| ldo1_reg: LDO1 { |
| regulator-name = "LDO1"; |
| regulator-min-microvolt = <3000000>; |
| regulator-max-microvolt = <3300000>; |
| regulator-boot-on; |
| regulator-always-on; |
| }; |
| |
| ldo2_reg: LDO2 { |
| regulator-name = "LDO2"; |
| regulator-min-microvolt = <900000>; |
| regulator-max-microvolt = <900000>; |
| regulator-boot-on; |
| regulator-always-on; |
| }; |
| |
| ldo3_reg: LDO3 { |
| regulator-name = "LDO3"; |
| regulator-min-microvolt = <1800000>; |
| regulator-max-microvolt = <3300000>; |
| regulator-boot-on; |
| regulator-always-on; |
| }; |
| |
| ldo4_reg: LDO4 { |
| regulator-name = "LDO4"; |
| regulator-min-microvolt = <900000>; |
| regulator-max-microvolt = <1800000>; |
| regulator-boot-on; |
| regulator-always-on; |
| }; |
| |
| ldo6_reg: LDO6 { |
| regulator-name = "LDO6"; |
| regulator-min-microvolt = <900000>; |
| regulator-max-microvolt = <1800000>; |
| regulator-boot-on; |
| regulator-always-on; |
| }; |
| }; |
| }; |
| }; |
| |
| &snvs_pwrkey { |
| status = "okay"; |
| }; |
| |
| &uart2 { /* console */ |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_uart2>; |
| status = "okay"; |
| }; |
| |
| &usdhc2 { |
| pinctrl-names = "default", "state_100mhz", "state_200mhz"; |
| pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; |
| pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; |
| pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; |
| cd-gpios = <&gpio1 15 GPIO_ACTIVE_LOW>; |
| bus-width = <4>; |
| vmmc-supply = <®_usdhc2_vmmc>; |
| status = "okay"; |
| }; |
| |
| &usdhc3 { |
| pinctrl-names = "default", "state_100mhz", "state_200mhz"; |
| pinctrl-0 = <&pinctrl_usdhc3>; |
| pinctrl-1 = <&pinctrl_usdhc3_100mhz>; |
| pinctrl-2 = <&pinctrl_usdhc3_200mhz>; |
| bus-width = <8>; |
| non-removable; |
| status = "okay"; |
| }; |
| |
| &wdog1 { |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_wdog>; |
| fsl,ext-reset-output; |
| status = "okay"; |
| }; |
