| /* SPDX-License-Identifier: GPL-2.0 |
| * |
| * Copyright 2016-2018 HabanaLabs, Ltd. |
| * All Rights Reserved. |
| * |
| */ |
| |
| /************************************ |
| ** This is an auto-generated file ** |
| ** DO NOT EDIT BELOW ** |
| ************************************/ |
| |
| #ifndef ASIC_REG_TPC4_CFG_REGS_H_ |
| #define ASIC_REG_TPC4_CFG_REGS_H_ |
| |
| /* |
| ***************************************** |
| * TPC4_CFG (Prototype: TPC) |
| ***************************************** |
| */ |
| |
| #define mmTPC4_CFG_KERNEL_TENSOR_0_BASE_ADDR_LOW 0xF06400 |
| |
| #define mmTPC4_CFG_KERNEL_TENSOR_0_BASE_ADDR_HIGH 0xF06404 |
| |
| #define mmTPC4_CFG_KERNEL_TENSOR_0_PADDING_VALUE 0xF06408 |
| |
| #define mmTPC4_CFG_KERNEL_TENSOR_0_TENSOR_CONFIG 0xF0640C |
| |
| #define mmTPC4_CFG_KERNEL_TENSOR_0_DIM_0_SIZE 0xF06410 |
| |
| #define mmTPC4_CFG_KERNEL_TENSOR_0_DIM_0_STRIDE 0xF06414 |
| |
| #define mmTPC4_CFG_KERNEL_TENSOR_0_DIM_0_BASE_OFFSET 0xF06418 |
| |
| #define mmTPC4_CFG_KERNEL_TENSOR_0_DIM_1_SIZE 0xF0641C |
| |
| #define mmTPC4_CFG_KERNEL_TENSOR_0_DIM_1_STRIDE 0xF06420 |
| |
| #define mmTPC4_CFG_KERNEL_TENSOR_0_DIM_1_BASE_OFFSET 0xF06424 |
| |
| #define mmTPC4_CFG_KERNEL_TENSOR_0_DIM_2_SIZE 0xF06428 |
| |
| #define mmTPC4_CFG_KERNEL_TENSOR_0_DIM_2_STRIDE 0xF0642C |
| |
| #define mmTPC4_CFG_KERNEL_TENSOR_0_DIM_2_BASE_OFFSET 0xF06430 |
| |
| #define mmTPC4_CFG_KERNEL_TENSOR_0_DIM_3_SIZE 0xF06434 |
| |
| #define mmTPC4_CFG_KERNEL_TENSOR_0_DIM_3_STRIDE 0xF06438 |
| |
| #define mmTPC4_CFG_KERNEL_TENSOR_0_DIM_3_BASE_OFFSET 0xF0643C |
| |
| #define mmTPC4_CFG_KERNEL_TENSOR_0_DIM_4_SIZE 0xF06440 |
| |
| #define mmTPC4_CFG_KERNEL_TENSOR_0_DIM_4_STRIDE 0xF06444 |
| |
| #define mmTPC4_CFG_KERNEL_TENSOR_0_DIM_4_BASE_OFFSET 0xF06448 |
| |
| #define mmTPC4_CFG_KERNEL_TENSOR_1_BASE_ADDR_LOW 0xF0644C |
| |
| #define mmTPC4_CFG_KERNEL_TENSOR_1_BASE_ADDR_HIGH 0xF06450 |
| |
| #define mmTPC4_CFG_KERNEL_TENSOR_1_PADDING_VALUE 0xF06454 |
| |
| #define mmTPC4_CFG_KERNEL_TENSOR_1_TENSOR_CONFIG 0xF06458 |
| |
| #define mmTPC4_CFG_KERNEL_TENSOR_1_DIM_0_SIZE 0xF0645C |
| |
| #define mmTPC4_CFG_KERNEL_TENSOR_1_DIM_0_STRIDE 0xF06460 |
| |
| #define mmTPC4_CFG_KERNEL_TENSOR_1_DIM_0_BASE_OFFSET 0xF06464 |
| |
| #define mmTPC4_CFG_KERNEL_TENSOR_1_DIM_1_SIZE 0xF06468 |
| |
| #define mmTPC4_CFG_KERNEL_TENSOR_1_DIM_1_STRIDE 0xF0646C |
| |
| #define mmTPC4_CFG_KERNEL_TENSOR_1_DIM_1_BASE_OFFSET 0xF06470 |
| |
| #define mmTPC4_CFG_KERNEL_TENSOR_1_DIM_2_SIZE 0xF06474 |
| |
| #define mmTPC4_CFG_KERNEL_TENSOR_1_DIM_2_STRIDE 0xF06478 |
| |
| #define mmTPC4_CFG_KERNEL_TENSOR_1_DIM_2_BASE_OFFSET 0xF0647C |
| |
| #define mmTPC4_CFG_KERNEL_TENSOR_1_DIM_3_SIZE 0xF06480 |
| |
| #define mmTPC4_CFG_KERNEL_TENSOR_1_DIM_3_STRIDE 0xF06484 |
| |
| #define mmTPC4_CFG_KERNEL_TENSOR_1_DIM_3_BASE_OFFSET 0xF06488 |
| |
| #define mmTPC4_CFG_KERNEL_TENSOR_1_DIM_4_SIZE 0xF0648C |
| |
| #define mmTPC4_CFG_KERNEL_TENSOR_1_DIM_4_STRIDE 0xF06490 |
| |
| #define mmTPC4_CFG_KERNEL_TENSOR_1_DIM_4_BASE_OFFSET 0xF06494 |
| |
| #define mmTPC4_CFG_KERNEL_TENSOR_2_BASE_ADDR_LOW 0xF06498 |
| |
| #define mmTPC4_CFG_KERNEL_TENSOR_2_BASE_ADDR_HIGH 0xF0649C |
| |
| #define mmTPC4_CFG_KERNEL_TENSOR_2_PADDING_VALUE 0xF064A0 |
| |
| #define mmTPC4_CFG_KERNEL_TENSOR_2_TENSOR_CONFIG 0xF064A4 |
| |
| #define mmTPC4_CFG_KERNEL_TENSOR_2_DIM_0_SIZE 0xF064A8 |
| |
| #define mmTPC4_CFG_KERNEL_TENSOR_2_DIM_0_STRIDE 0xF064AC |
| |
| #define mmTPC4_CFG_KERNEL_TENSOR_2_DIM_0_BASE_OFFSET 0xF064B0 |
| |
| #define mmTPC4_CFG_KERNEL_TENSOR_2_DIM_1_SIZE 0xF064B4 |
| |
| #define mmTPC4_CFG_KERNEL_TENSOR_2_DIM_1_STRIDE 0xF064B8 |
| |
| #define mmTPC4_CFG_KERNEL_TENSOR_2_DIM_1_BASE_OFFSET 0xF064BC |
| |
| #define mmTPC4_CFG_KERNEL_TENSOR_2_DIM_2_SIZE 0xF064C0 |
| |
| #define mmTPC4_CFG_KERNEL_TENSOR_2_DIM_2_STRIDE 0xF064C4 |
| |
| #define mmTPC4_CFG_KERNEL_TENSOR_2_DIM_2_BASE_OFFSET 0xF064C8 |
| |
| #define mmTPC4_CFG_KERNEL_TENSOR_2_DIM_3_SIZE 0xF064CC |
| |
| #define mmTPC4_CFG_KERNEL_TENSOR_2_DIM_3_STRIDE 0xF064D0 |
| |
| #define mmTPC4_CFG_KERNEL_TENSOR_2_DIM_3_BASE_OFFSET 0xF064D4 |
| |
| #define mmTPC4_CFG_KERNEL_TENSOR_2_DIM_4_SIZE 0xF064D8 |
| |
| #define mmTPC4_CFG_KERNEL_TENSOR_2_DIM_4_STRIDE 0xF064DC |
| |
| #define mmTPC4_CFG_KERNEL_TENSOR_2_DIM_4_BASE_OFFSET 0xF064E0 |
| |
| #define mmTPC4_CFG_KERNEL_TENSOR_3_BASE_ADDR_LOW 0xF064E4 |
| |
| #define mmTPC4_CFG_KERNEL_TENSOR_3_BASE_ADDR_HIGH 0xF064E8 |
| |
| #define mmTPC4_CFG_KERNEL_TENSOR_3_PADDING_VALUE 0xF064EC |
| |
| #define mmTPC4_CFG_KERNEL_TENSOR_3_TENSOR_CONFIG 0xF064F0 |
| |
| #define mmTPC4_CFG_KERNEL_TENSOR_3_DIM_0_SIZE 0xF064F4 |
| |
| #define mmTPC4_CFG_KERNEL_TENSOR_3_DIM_0_STRIDE 0xF064F8 |
| |
| #define mmTPC4_CFG_KERNEL_TENSOR_3_DIM_0_BASE_OFFSET 0xF064FC |
| |
| #define mmTPC4_CFG_KERNEL_TENSOR_3_DIM_1_SIZE 0xF06500 |
| |
| #define mmTPC4_CFG_KERNEL_TENSOR_3_DIM_1_STRIDE 0xF06504 |
| |
| #define mmTPC4_CFG_KERNEL_TENSOR_3_DIM_1_BASE_OFFSET 0xF06508 |
| |
| #define mmTPC4_CFG_KERNEL_TENSOR_3_DIM_2_SIZE 0xF0650C |
| |
| #define mmTPC4_CFG_KERNEL_TENSOR_3_DIM_2_STRIDE 0xF06510 |
| |
| #define mmTPC4_CFG_KERNEL_TENSOR_3_DIM_2_BASE_OFFSET 0xF06514 |
| |
| #define mmTPC4_CFG_KERNEL_TENSOR_3_DIM_3_SIZE 0xF06518 |
| |
| #define mmTPC4_CFG_KERNEL_TENSOR_3_DIM_3_STRIDE 0xF0651C |
| |
| #define mmTPC4_CFG_KERNEL_TENSOR_3_DIM_3_BASE_OFFSET 0xF06520 |
| |
| #define mmTPC4_CFG_KERNEL_TENSOR_3_DIM_4_SIZE 0xF06524 |
| |
| #define mmTPC4_CFG_KERNEL_TENSOR_3_DIM_4_STRIDE 0xF06528 |
| |
| #define mmTPC4_CFG_KERNEL_TENSOR_3_DIM_4_BASE_OFFSET 0xF0652C |
| |
| #define mmTPC4_CFG_KERNEL_TENSOR_4_BASE_ADDR_LOW 0xF06530 |
| |
| #define mmTPC4_CFG_KERNEL_TENSOR_4_BASE_ADDR_HIGH 0xF06534 |
| |
| #define mmTPC4_CFG_KERNEL_TENSOR_4_PADDING_VALUE 0xF06538 |
| |
| #define mmTPC4_CFG_KERNEL_TENSOR_4_TENSOR_CONFIG 0xF0653C |
| |
| #define mmTPC4_CFG_KERNEL_TENSOR_4_DIM_0_SIZE 0xF06540 |
| |
| #define mmTPC4_CFG_KERNEL_TENSOR_4_DIM_0_STRIDE 0xF06544 |
| |
| #define mmTPC4_CFG_KERNEL_TENSOR_4_DIM_0_BASE_OFFSET 0xF06548 |
| |
| #define mmTPC4_CFG_KERNEL_TENSOR_4_DIM_1_SIZE 0xF0654C |
| |
| #define mmTPC4_CFG_KERNEL_TENSOR_4_DIM_1_STRIDE 0xF06550 |
| |
| #define mmTPC4_CFG_KERNEL_TENSOR_4_DIM_1_BASE_OFFSET 0xF06554 |
| |
| #define mmTPC4_CFG_KERNEL_TENSOR_4_DIM_2_SIZE 0xF06558 |
| |
| #define mmTPC4_CFG_KERNEL_TENSOR_4_DIM_2_STRIDE 0xF0655C |
| |
| #define mmTPC4_CFG_KERNEL_TENSOR_4_DIM_2_BASE_OFFSET 0xF06560 |
| |
| #define mmTPC4_CFG_KERNEL_TENSOR_4_DIM_3_SIZE 0xF06564 |
| |
| #define mmTPC4_CFG_KERNEL_TENSOR_4_DIM_3_STRIDE 0xF06568 |
| |
| #define mmTPC4_CFG_KERNEL_TENSOR_4_DIM_3_BASE_OFFSET 0xF0656C |
| |
| #define mmTPC4_CFG_KERNEL_TENSOR_4_DIM_4_SIZE 0xF06570 |
| |
| #define mmTPC4_CFG_KERNEL_TENSOR_4_DIM_4_STRIDE 0xF06574 |
| |
| #define mmTPC4_CFG_KERNEL_TENSOR_4_DIM_4_BASE_OFFSET 0xF06578 |
| |
| #define mmTPC4_CFG_KERNEL_TENSOR_5_BASE_ADDR_LOW 0xF0657C |
| |
| #define mmTPC4_CFG_KERNEL_TENSOR_5_BASE_ADDR_HIGH 0xF06580 |
| |
| #define mmTPC4_CFG_KERNEL_TENSOR_5_PADDING_VALUE 0xF06584 |
| |
| #define mmTPC4_CFG_KERNEL_TENSOR_5_TENSOR_CONFIG 0xF06588 |
| |
| #define mmTPC4_CFG_KERNEL_TENSOR_5_DIM_0_SIZE 0xF0658C |
| |
| #define mmTPC4_CFG_KERNEL_TENSOR_5_DIM_0_STRIDE 0xF06590 |
| |
| #define mmTPC4_CFG_KERNEL_TENSOR_5_DIM_0_BASE_OFFSET 0xF06594 |
| |
| #define mmTPC4_CFG_KERNEL_TENSOR_5_DIM_1_SIZE 0xF06598 |
| |
| #define mmTPC4_CFG_KERNEL_TENSOR_5_DIM_1_STRIDE 0xF0659C |
| |
| #define mmTPC4_CFG_KERNEL_TENSOR_5_DIM_1_BASE_OFFSET 0xF065A0 |
| |
| #define mmTPC4_CFG_KERNEL_TENSOR_5_DIM_2_SIZE 0xF065A4 |
| |
| #define mmTPC4_CFG_KERNEL_TENSOR_5_DIM_2_STRIDE 0xF065A8 |
| |
| #define mmTPC4_CFG_KERNEL_TENSOR_5_DIM_2_BASE_OFFSET 0xF065AC |
| |
| #define mmTPC4_CFG_KERNEL_TENSOR_5_DIM_3_SIZE 0xF065B0 |
| |
| #define mmTPC4_CFG_KERNEL_TENSOR_5_DIM_3_STRIDE 0xF065B4 |
| |
| #define mmTPC4_CFG_KERNEL_TENSOR_5_DIM_3_BASE_OFFSET 0xF065B8 |
| |
| #define mmTPC4_CFG_KERNEL_TENSOR_5_DIM_4_SIZE 0xF065BC |
| |
| #define mmTPC4_CFG_KERNEL_TENSOR_5_DIM_4_STRIDE 0xF065C0 |
| |
| #define mmTPC4_CFG_KERNEL_TENSOR_5_DIM_4_BASE_OFFSET 0xF065C4 |
| |
| #define mmTPC4_CFG_KERNEL_TENSOR_6_BASE_ADDR_LOW 0xF065C8 |
| |
| #define mmTPC4_CFG_KERNEL_TENSOR_6_BASE_ADDR_HIGH 0xF065CC |
| |
| #define mmTPC4_CFG_KERNEL_TENSOR_6_PADDING_VALUE 0xF065D0 |
| |
| #define mmTPC4_CFG_KERNEL_TENSOR_6_TENSOR_CONFIG 0xF065D4 |
| |
| #define mmTPC4_CFG_KERNEL_TENSOR_6_DIM_0_SIZE 0xF065D8 |
| |
| #define mmTPC4_CFG_KERNEL_TENSOR_6_DIM_0_STRIDE 0xF065DC |
| |
| #define mmTPC4_CFG_KERNEL_TENSOR_6_DIM_0_BASE_OFFSET 0xF065E0 |
| |
| #define mmTPC4_CFG_KERNEL_TENSOR_6_DIM_1_SIZE 0xF065E4 |
| |
| #define mmTPC4_CFG_KERNEL_TENSOR_6_DIM_1_STRIDE 0xF065E8 |
| |
| #define mmTPC4_CFG_KERNEL_TENSOR_6_DIM_1_BASE_OFFSET 0xF065EC |
| |
| #define mmTPC4_CFG_KERNEL_TENSOR_6_DIM_2_SIZE 0xF065F0 |
| |
| #define mmTPC4_CFG_KERNEL_TENSOR_6_DIM_2_STRIDE 0xF065F4 |
| |
| #define mmTPC4_CFG_KERNEL_TENSOR_6_DIM_2_BASE_OFFSET 0xF065F8 |
| |
| #define mmTPC4_CFG_KERNEL_TENSOR_6_DIM_3_SIZE 0xF065FC |
| |
| #define mmTPC4_CFG_KERNEL_TENSOR_6_DIM_3_STRIDE 0xF06600 |
| |
| #define mmTPC4_CFG_KERNEL_TENSOR_6_DIM_3_BASE_OFFSET 0xF06604 |
| |
| #define mmTPC4_CFG_KERNEL_TENSOR_6_DIM_4_SIZE 0xF06608 |
| |
| #define mmTPC4_CFG_KERNEL_TENSOR_6_DIM_4_STRIDE 0xF0660C |
| |
| #define mmTPC4_CFG_KERNEL_TENSOR_6_DIM_4_BASE_OFFSET 0xF06610 |
| |
| #define mmTPC4_CFG_KERNEL_TENSOR_7_BASE_ADDR_LOW 0xF06614 |
| |
| #define mmTPC4_CFG_KERNEL_TENSOR_7_BASE_ADDR_HIGH 0xF06618 |
| |
| #define mmTPC4_CFG_KERNEL_TENSOR_7_PADDING_VALUE 0xF0661C |
| |
| #define mmTPC4_CFG_KERNEL_TENSOR_7_TENSOR_CONFIG 0xF06620 |
| |
| #define mmTPC4_CFG_KERNEL_TENSOR_7_DIM_0_SIZE 0xF06624 |
| |
| #define mmTPC4_CFG_KERNEL_TENSOR_7_DIM_0_STRIDE 0xF06628 |
| |
| #define mmTPC4_CFG_KERNEL_TENSOR_7_DIM_0_BASE_OFFSET 0xF0662C |
| |
| #define mmTPC4_CFG_KERNEL_TENSOR_7_DIM_1_SIZE 0xF06630 |
| |
| #define mmTPC4_CFG_KERNEL_TENSOR_7_DIM_1_STRIDE 0xF06634 |
| |
| #define mmTPC4_CFG_KERNEL_TENSOR_7_DIM_1_BASE_OFFSET 0xF06638 |
| |
| #define mmTPC4_CFG_KERNEL_TENSOR_7_DIM_2_SIZE 0xF0663C |
| |
| #define mmTPC4_CFG_KERNEL_TENSOR_7_DIM_2_STRIDE 0xF06640 |
| |
| #define mmTPC4_CFG_KERNEL_TENSOR_7_DIM_2_BASE_OFFSET 0xF06644 |
| |
| #define mmTPC4_CFG_KERNEL_TENSOR_7_DIM_3_SIZE 0xF06648 |
| |
| #define mmTPC4_CFG_KERNEL_TENSOR_7_DIM_3_STRIDE 0xF0664C |
| |
| #define mmTPC4_CFG_KERNEL_TENSOR_7_DIM_3_BASE_OFFSET 0xF06650 |
| |
| #define mmTPC4_CFG_KERNEL_TENSOR_7_DIM_4_SIZE 0xF06654 |
| |
| #define mmTPC4_CFG_KERNEL_TENSOR_7_DIM_4_STRIDE 0xF06658 |
| |
| #define mmTPC4_CFG_KERNEL_TENSOR_7_DIM_4_BASE_OFFSET 0xF0665C |
| |
| #define mmTPC4_CFG_KERNEL_KERNEL_BASE_ADDRESS_LOW 0xF06660 |
| |
| #define mmTPC4_CFG_KERNEL_KERNEL_BASE_ADDRESS_HIGH 0xF06664 |
| |
| #define mmTPC4_CFG_KERNEL_TID_BASE_DIM_0 0xF06668 |
| |
| #define mmTPC4_CFG_KERNEL_TID_SIZE_DIM_0 0xF0666C |
| |
| #define mmTPC4_CFG_KERNEL_TID_BASE_DIM_1 0xF06670 |
| |
| #define mmTPC4_CFG_KERNEL_TID_SIZE_DIM_1 0xF06674 |
| |
| #define mmTPC4_CFG_KERNEL_TID_BASE_DIM_2 0xF06678 |
| |
| #define mmTPC4_CFG_KERNEL_TID_SIZE_DIM_2 0xF0667C |
| |
| #define mmTPC4_CFG_KERNEL_TID_BASE_DIM_3 0xF06680 |
| |
| #define mmTPC4_CFG_KERNEL_TID_SIZE_DIM_3 0xF06684 |
| |
| #define mmTPC4_CFG_KERNEL_TID_BASE_DIM_4 0xF06688 |
| |
| #define mmTPC4_CFG_KERNEL_TID_SIZE_DIM_4 0xF0668C |
| |
| #define mmTPC4_CFG_KERNEL_SRF_0 0xF06690 |
| |
| #define mmTPC4_CFG_KERNEL_SRF_1 0xF06694 |
| |
| #define mmTPC4_CFG_KERNEL_SRF_2 0xF06698 |
| |
| #define mmTPC4_CFG_KERNEL_SRF_3 0xF0669C |
| |
| #define mmTPC4_CFG_KERNEL_SRF_4 0xF066A0 |
| |
| #define mmTPC4_CFG_KERNEL_SRF_5 0xF066A4 |
| |
| #define mmTPC4_CFG_KERNEL_SRF_6 0xF066A8 |
| |
| #define mmTPC4_CFG_KERNEL_SRF_7 0xF066AC |
| |
| #define mmTPC4_CFG_KERNEL_SRF_8 0xF066B0 |
| |
| #define mmTPC4_CFG_KERNEL_SRF_9 0xF066B4 |
| |
| #define mmTPC4_CFG_KERNEL_SRF_10 0xF066B8 |
| |
| #define mmTPC4_CFG_KERNEL_SRF_11 0xF066BC |
| |
| #define mmTPC4_CFG_KERNEL_SRF_12 0xF066C0 |
| |
| #define mmTPC4_CFG_KERNEL_SRF_13 0xF066C4 |
| |
| #define mmTPC4_CFG_KERNEL_SRF_14 0xF066C8 |
| |
| #define mmTPC4_CFG_KERNEL_SRF_15 0xF066CC |
| |
| #define mmTPC4_CFG_KERNEL_SRF_16 0xF066D0 |
| |
| #define mmTPC4_CFG_KERNEL_SRF_17 0xF066D4 |
| |
| #define mmTPC4_CFG_KERNEL_SRF_18 0xF066D8 |
| |
| #define mmTPC4_CFG_KERNEL_SRF_19 0xF066DC |
| |
| #define mmTPC4_CFG_KERNEL_SRF_20 0xF066E0 |
| |
| #define mmTPC4_CFG_KERNEL_SRF_21 0xF066E4 |
| |
| #define mmTPC4_CFG_KERNEL_SRF_22 0xF066E8 |
| |
| #define mmTPC4_CFG_KERNEL_SRF_23 0xF066EC |
| |
| #define mmTPC4_CFG_KERNEL_SRF_24 0xF066F0 |
| |
| #define mmTPC4_CFG_KERNEL_SRF_25 0xF066F4 |
| |
| #define mmTPC4_CFG_KERNEL_SRF_26 0xF066F8 |
| |
| #define mmTPC4_CFG_KERNEL_SRF_27 0xF066FC |
| |
| #define mmTPC4_CFG_KERNEL_SRF_28 0xF06700 |
| |
| #define mmTPC4_CFG_KERNEL_SRF_29 0xF06704 |
| |
| #define mmTPC4_CFG_KERNEL_SRF_30 0xF06708 |
| |
| #define mmTPC4_CFG_KERNEL_SRF_31 0xF0670C |
| |
| #define mmTPC4_CFG_KERNEL_KERNEL_CONFIG 0xF06710 |
| |
| #define mmTPC4_CFG_KERNEL_SYNC_OBJECT_MESSAGE 0xF06714 |
| |
| #define mmTPC4_CFG_RESERVED_DESC_END 0xF06738 |
| |
| #define mmTPC4_CFG_ROUND_CSR 0xF067FC |
| |
| #define mmTPC4_CFG_TBUF_BASE_ADDR_LOW 0xF06800 |
| |
| #define mmTPC4_CFG_TBUF_BASE_ADDR_HIGH 0xF06804 |
| |
| #define mmTPC4_CFG_SEMAPHORE 0xF06808 |
| |
| #define mmTPC4_CFG_VFLAGS 0xF0680C |
| |
| #define mmTPC4_CFG_SFLAGS 0xF06810 |
| |
| #define mmTPC4_CFG_LFSR_POLYNOM 0xF06818 |
| |
| #define mmTPC4_CFG_STATUS 0xF0681C |
| |
| #define mmTPC4_CFG_CFG_BASE_ADDRESS_HIGH 0xF06820 |
| |
| #define mmTPC4_CFG_CFG_SUBTRACT_VALUE 0xF06824 |
| |
| #define mmTPC4_CFG_SM_BASE_ADDRESS_LOW 0xF06828 |
| |
| #define mmTPC4_CFG_SM_BASE_ADDRESS_HIGH 0xF0682C |
| |
| #define mmTPC4_CFG_TPC_CMD 0xF06830 |
| |
| #define mmTPC4_CFG_TPC_EXECUTE 0xF06838 |
| |
| #define mmTPC4_CFG_TPC_STALL 0xF0683C |
| |
| #define mmTPC4_CFG_ICACHE_BASE_ADDERESS_LOW 0xF06840 |
| |
| #define mmTPC4_CFG_ICACHE_BASE_ADDERESS_HIGH 0xF06844 |
| |
| #define mmTPC4_CFG_MSS_CONFIG 0xF06854 |
| |
| #define mmTPC4_CFG_TPC_INTR_CAUSE 0xF06858 |
| |
| #define mmTPC4_CFG_TPC_INTR_MASK 0xF0685C |
| |
| #define mmTPC4_CFG_TSB_CONFIG 0xF06860 |
| |
| #define mmTPC4_CFG_QM_TENSOR_0_BASE_ADDR_LOW 0xF06A00 |
| |
| #define mmTPC4_CFG_QM_TENSOR_0_BASE_ADDR_HIGH 0xF06A04 |
| |
| #define mmTPC4_CFG_QM_TENSOR_0_PADDING_VALUE 0xF06A08 |
| |
| #define mmTPC4_CFG_QM_TENSOR_0_TENSOR_CONFIG 0xF06A0C |
| |
| #define mmTPC4_CFG_QM_TENSOR_0_DIM_0_SIZE 0xF06A10 |
| |
| #define mmTPC4_CFG_QM_TENSOR_0_DIM_0_STRIDE 0xF06A14 |
| |
| #define mmTPC4_CFG_QM_TENSOR_0_DIM_0_BASE_OFFSET 0xF06A18 |
| |
| #define mmTPC4_CFG_QM_TENSOR_0_DIM_1_SIZE 0xF06A1C |
| |
| #define mmTPC4_CFG_QM_TENSOR_0_DIM_1_STRIDE 0xF06A20 |
| |
| #define mmTPC4_CFG_QM_TENSOR_0_DIM_1_BASE_OFFSET 0xF06A24 |
| |
| #define mmTPC4_CFG_QM_TENSOR_0_DIM_2_SIZE 0xF06A28 |
| |
| #define mmTPC4_CFG_QM_TENSOR_0_DIM_2_STRIDE 0xF06A2C |
| |
| #define mmTPC4_CFG_QM_TENSOR_0_DIM_2_BASE_OFFSET 0xF06A30 |
| |
| #define mmTPC4_CFG_QM_TENSOR_0_DIM_3_SIZE 0xF06A34 |
| |
| #define mmTPC4_CFG_QM_TENSOR_0_DIM_3_STRIDE 0xF06A38 |
| |
| #define mmTPC4_CFG_QM_TENSOR_0_DIM_3_BASE_OFFSET 0xF06A3C |
| |
| #define mmTPC4_CFG_QM_TENSOR_0_DIM_4_SIZE 0xF06A40 |
| |
| #define mmTPC4_CFG_QM_TENSOR_0_DIM_4_STRIDE 0xF06A44 |
| |
| #define mmTPC4_CFG_QM_TENSOR_0_DIM_4_BASE_OFFSET 0xF06A48 |
| |
| #define mmTPC4_CFG_QM_TENSOR_1_BASE_ADDR_LOW 0xF06A4C |
| |
| #define mmTPC4_CFG_QM_TENSOR_1_BASE_ADDR_HIGH 0xF06A50 |
| |
| #define mmTPC4_CFG_QM_TENSOR_1_PADDING_VALUE 0xF06A54 |
| |
| #define mmTPC4_CFG_QM_TENSOR_1_TENSOR_CONFIG 0xF06A58 |
| |
| #define mmTPC4_CFG_QM_TENSOR_1_DIM_0_SIZE 0xF06A5C |
| |
| #define mmTPC4_CFG_QM_TENSOR_1_DIM_0_STRIDE 0xF06A60 |
| |
| #define mmTPC4_CFG_QM_TENSOR_1_DIM_0_BASE_OFFSET 0xF06A64 |
| |
| #define mmTPC4_CFG_QM_TENSOR_1_DIM_1_SIZE 0xF06A68 |
| |
| #define mmTPC4_CFG_QM_TENSOR_1_DIM_1_STRIDE 0xF06A6C |
| |
| #define mmTPC4_CFG_QM_TENSOR_1_DIM_1_BASE_OFFSET 0xF06A70 |
| |
| #define mmTPC4_CFG_QM_TENSOR_1_DIM_2_SIZE 0xF06A74 |
| |
| #define mmTPC4_CFG_QM_TENSOR_1_DIM_2_STRIDE 0xF06A78 |
| |
| #define mmTPC4_CFG_QM_TENSOR_1_DIM_2_BASE_OFFSET 0xF06A7C |
| |
| #define mmTPC4_CFG_QM_TENSOR_1_DIM_3_SIZE 0xF06A80 |
| |
| #define mmTPC4_CFG_QM_TENSOR_1_DIM_3_STRIDE 0xF06A84 |
| |
| #define mmTPC4_CFG_QM_TENSOR_1_DIM_3_BASE_OFFSET 0xF06A88 |
| |
| #define mmTPC4_CFG_QM_TENSOR_1_DIM_4_SIZE 0xF06A8C |
| |
| #define mmTPC4_CFG_QM_TENSOR_1_DIM_4_STRIDE 0xF06A90 |
| |
| #define mmTPC4_CFG_QM_TENSOR_1_DIM_4_BASE_OFFSET 0xF06A94 |
| |
| #define mmTPC4_CFG_QM_TENSOR_2_BASE_ADDR_LOW 0xF06A98 |
| |
| #define mmTPC4_CFG_QM_TENSOR_2_BASE_ADDR_HIGH 0xF06A9C |
| |
| #define mmTPC4_CFG_QM_TENSOR_2_PADDING_VALUE 0xF06AA0 |
| |
| #define mmTPC4_CFG_QM_TENSOR_2_TENSOR_CONFIG 0xF06AA4 |
| |
| #define mmTPC4_CFG_QM_TENSOR_2_DIM_0_SIZE 0xF06AA8 |
| |
| #define mmTPC4_CFG_QM_TENSOR_2_DIM_0_STRIDE 0xF06AAC |
| |
| #define mmTPC4_CFG_QM_TENSOR_2_DIM_0_BASE_OFFSET 0xF06AB0 |
| |
| #define mmTPC4_CFG_QM_TENSOR_2_DIM_1_SIZE 0xF06AB4 |
| |
| #define mmTPC4_CFG_QM_TENSOR_2_DIM_1_STRIDE 0xF06AB8 |
| |
| #define mmTPC4_CFG_QM_TENSOR_2_DIM_1_BASE_OFFSET 0xF06ABC |
| |
| #define mmTPC4_CFG_QM_TENSOR_2_DIM_2_SIZE 0xF06AC0 |
| |
| #define mmTPC4_CFG_QM_TENSOR_2_DIM_2_STRIDE 0xF06AC4 |
| |
| #define mmTPC4_CFG_QM_TENSOR_2_DIM_2_BASE_OFFSET 0xF06AC8 |
| |
| #define mmTPC4_CFG_QM_TENSOR_2_DIM_3_SIZE 0xF06ACC |
| |
| #define mmTPC4_CFG_QM_TENSOR_2_DIM_3_STRIDE 0xF06AD0 |
| |
| #define mmTPC4_CFG_QM_TENSOR_2_DIM_3_BASE_OFFSET 0xF06AD4 |
| |
| #define mmTPC4_CFG_QM_TENSOR_2_DIM_4_SIZE 0xF06AD8 |
| |
| #define mmTPC4_CFG_QM_TENSOR_2_DIM_4_STRIDE 0xF06ADC |
| |
| #define mmTPC4_CFG_QM_TENSOR_2_DIM_4_BASE_OFFSET 0xF06AE0 |
| |
| #define mmTPC4_CFG_QM_TENSOR_3_BASE_ADDR_LOW 0xF06AE4 |
| |
| #define mmTPC4_CFG_QM_TENSOR_3_BASE_ADDR_HIGH 0xF06AE8 |
| |
| #define mmTPC4_CFG_QM_TENSOR_3_PADDING_VALUE 0xF06AEC |
| |
| #define mmTPC4_CFG_QM_TENSOR_3_TENSOR_CONFIG 0xF06AF0 |
| |
| #define mmTPC4_CFG_QM_TENSOR_3_DIM_0_SIZE 0xF06AF4 |
| |
| #define mmTPC4_CFG_QM_TENSOR_3_DIM_0_STRIDE 0xF06AF8 |
| |
| #define mmTPC4_CFG_QM_TENSOR_3_DIM_0_BASE_OFFSET 0xF06AFC |
| |
| #define mmTPC4_CFG_QM_TENSOR_3_DIM_1_SIZE 0xF06B00 |
| |
| #define mmTPC4_CFG_QM_TENSOR_3_DIM_1_STRIDE 0xF06B04 |
| |
| #define mmTPC4_CFG_QM_TENSOR_3_DIM_1_BASE_OFFSET 0xF06B08 |
| |
| #define mmTPC4_CFG_QM_TENSOR_3_DIM_2_SIZE 0xF06B0C |
| |
| #define mmTPC4_CFG_QM_TENSOR_3_DIM_2_STRIDE 0xF06B10 |
| |
| #define mmTPC4_CFG_QM_TENSOR_3_DIM_2_BASE_OFFSET 0xF06B14 |
| |
| #define mmTPC4_CFG_QM_TENSOR_3_DIM_3_SIZE 0xF06B18 |
| |
| #define mmTPC4_CFG_QM_TENSOR_3_DIM_3_STRIDE 0xF06B1C |
| |
| #define mmTPC4_CFG_QM_TENSOR_3_DIM_3_BASE_OFFSET 0xF06B20 |
| |
| #define mmTPC4_CFG_QM_TENSOR_3_DIM_4_SIZE 0xF06B24 |
| |
| #define mmTPC4_CFG_QM_TENSOR_3_DIM_4_STRIDE 0xF06B28 |
| |
| #define mmTPC4_CFG_QM_TENSOR_3_DIM_4_BASE_OFFSET 0xF06B2C |
| |
| #define mmTPC4_CFG_QM_TENSOR_4_BASE_ADDR_LOW 0xF06B30 |
| |
| #define mmTPC4_CFG_QM_TENSOR_4_BASE_ADDR_HIGH 0xF06B34 |
| |
| #define mmTPC4_CFG_QM_TENSOR_4_PADDING_VALUE 0xF06B38 |
| |
| #define mmTPC4_CFG_QM_TENSOR_4_TENSOR_CONFIG 0xF06B3C |
| |
| #define mmTPC4_CFG_QM_TENSOR_4_DIM_0_SIZE 0xF06B40 |
| |
| #define mmTPC4_CFG_QM_TENSOR_4_DIM_0_STRIDE 0xF06B44 |
| |
| #define mmTPC4_CFG_QM_TENSOR_4_DIM_0_BASE_OFFSET 0xF06B48 |
| |
| #define mmTPC4_CFG_QM_TENSOR_4_DIM_1_SIZE 0xF06B4C |
| |
| #define mmTPC4_CFG_QM_TENSOR_4_DIM_1_STRIDE 0xF06B50 |
| |
| #define mmTPC4_CFG_QM_TENSOR_4_DIM_1_BASE_OFFSET 0xF06B54 |
| |
| #define mmTPC4_CFG_QM_TENSOR_4_DIM_2_SIZE 0xF06B58 |
| |
| #define mmTPC4_CFG_QM_TENSOR_4_DIM_2_STRIDE 0xF06B5C |
| |
| #define mmTPC4_CFG_QM_TENSOR_4_DIM_2_BASE_OFFSET 0xF06B60 |
| |
| #define mmTPC4_CFG_QM_TENSOR_4_DIM_3_SIZE 0xF06B64 |
| |
| #define mmTPC4_CFG_QM_TENSOR_4_DIM_3_STRIDE 0xF06B68 |
| |
| #define mmTPC4_CFG_QM_TENSOR_4_DIM_3_BASE_OFFSET 0xF06B6C |
| |
| #define mmTPC4_CFG_QM_TENSOR_4_DIM_4_SIZE 0xF06B70 |
| |
| #define mmTPC4_CFG_QM_TENSOR_4_DIM_4_STRIDE 0xF06B74 |
| |
| #define mmTPC4_CFG_QM_TENSOR_4_DIM_4_BASE_OFFSET 0xF06B78 |
| |
| #define mmTPC4_CFG_QM_TENSOR_5_BASE_ADDR_LOW 0xF06B7C |
| |
| #define mmTPC4_CFG_QM_TENSOR_5_BASE_ADDR_HIGH 0xF06B80 |
| |
| #define mmTPC4_CFG_QM_TENSOR_5_PADDING_VALUE 0xF06B84 |
| |
| #define mmTPC4_CFG_QM_TENSOR_5_TENSOR_CONFIG 0xF06B88 |
| |
| #define mmTPC4_CFG_QM_TENSOR_5_DIM_0_SIZE 0xF06B8C |
| |
| #define mmTPC4_CFG_QM_TENSOR_5_DIM_0_STRIDE 0xF06B90 |
| |
| #define mmTPC4_CFG_QM_TENSOR_5_DIM_0_BASE_OFFSET 0xF06B94 |
| |
| #define mmTPC4_CFG_QM_TENSOR_5_DIM_1_SIZE 0xF06B98 |
| |
| #define mmTPC4_CFG_QM_TENSOR_5_DIM_1_STRIDE 0xF06B9C |
| |
| #define mmTPC4_CFG_QM_TENSOR_5_DIM_1_BASE_OFFSET 0xF06BA0 |
| |
| #define mmTPC4_CFG_QM_TENSOR_5_DIM_2_SIZE 0xF06BA4 |
| |
| #define mmTPC4_CFG_QM_TENSOR_5_DIM_2_STRIDE 0xF06BA8 |
| |
| #define mmTPC4_CFG_QM_TENSOR_5_DIM_2_BASE_OFFSET 0xF06BAC |
| |
| #define mmTPC4_CFG_QM_TENSOR_5_DIM_3_SIZE 0xF06BB0 |
| |
| #define mmTPC4_CFG_QM_TENSOR_5_DIM_3_STRIDE 0xF06BB4 |
| |
| #define mmTPC4_CFG_QM_TENSOR_5_DIM_3_BASE_OFFSET 0xF06BB8 |
| |
| #define mmTPC4_CFG_QM_TENSOR_5_DIM_4_SIZE 0xF06BBC |
| |
| #define mmTPC4_CFG_QM_TENSOR_5_DIM_4_STRIDE 0xF06BC0 |
| |
| #define mmTPC4_CFG_QM_TENSOR_5_DIM_4_BASE_OFFSET 0xF06BC4 |
| |
| #define mmTPC4_CFG_QM_TENSOR_6_BASE_ADDR_LOW 0xF06BC8 |
| |
| #define mmTPC4_CFG_QM_TENSOR_6_BASE_ADDR_HIGH 0xF06BCC |
| |
| #define mmTPC4_CFG_QM_TENSOR_6_PADDING_VALUE 0xF06BD0 |
| |
| #define mmTPC4_CFG_QM_TENSOR_6_TENSOR_CONFIG 0xF06BD4 |
| |
| #define mmTPC4_CFG_QM_TENSOR_6_DIM_0_SIZE 0xF06BD8 |
| |
| #define mmTPC4_CFG_QM_TENSOR_6_DIM_0_STRIDE 0xF06BDC |
| |
| #define mmTPC4_CFG_QM_TENSOR_6_DIM_0_BASE_OFFSET 0xF06BE0 |
| |
| #define mmTPC4_CFG_QM_TENSOR_6_DIM_1_SIZE 0xF06BE4 |
| |
| #define mmTPC4_CFG_QM_TENSOR_6_DIM_1_STRIDE 0xF06BE8 |
| |
| #define mmTPC4_CFG_QM_TENSOR_6_DIM_1_BASE_OFFSET 0xF06BEC |
| |
| #define mmTPC4_CFG_QM_TENSOR_6_DIM_2_SIZE 0xF06BF0 |
| |
| #define mmTPC4_CFG_QM_TENSOR_6_DIM_2_STRIDE 0xF06BF4 |
| |
| #define mmTPC4_CFG_QM_TENSOR_6_DIM_2_BASE_OFFSET 0xF06BF8 |
| |
| #define mmTPC4_CFG_QM_TENSOR_6_DIM_3_SIZE 0xF06BFC |
| |
| #define mmTPC4_CFG_QM_TENSOR_6_DIM_3_STRIDE 0xF06C00 |
| |
| #define mmTPC4_CFG_QM_TENSOR_6_DIM_3_BASE_OFFSET 0xF06C04 |
| |
| #define mmTPC4_CFG_QM_TENSOR_6_DIM_4_SIZE 0xF06C08 |
| |
| #define mmTPC4_CFG_QM_TENSOR_6_DIM_4_STRIDE 0xF06C0C |
| |
| #define mmTPC4_CFG_QM_TENSOR_6_DIM_4_BASE_OFFSET 0xF06C10 |
| |
| #define mmTPC4_CFG_QM_TENSOR_7_BASE_ADDR_LOW 0xF06C14 |
| |
| #define mmTPC4_CFG_QM_TENSOR_7_BASE_ADDR_HIGH 0xF06C18 |
| |
| #define mmTPC4_CFG_QM_TENSOR_7_PADDING_VALUE 0xF06C1C |
| |
| #define mmTPC4_CFG_QM_TENSOR_7_TENSOR_CONFIG 0xF06C20 |
| |
| #define mmTPC4_CFG_QM_TENSOR_7_DIM_0_SIZE 0xF06C24 |
| |
| #define mmTPC4_CFG_QM_TENSOR_7_DIM_0_STRIDE 0xF06C28 |
| |
| #define mmTPC4_CFG_QM_TENSOR_7_DIM_0_BASE_OFFSET 0xF06C2C |
| |
| #define mmTPC4_CFG_QM_TENSOR_7_DIM_1_SIZE 0xF06C30 |
| |
| #define mmTPC4_CFG_QM_TENSOR_7_DIM_1_STRIDE 0xF06C34 |
| |
| #define mmTPC4_CFG_QM_TENSOR_7_DIM_1_BASE_OFFSET 0xF06C38 |
| |
| #define mmTPC4_CFG_QM_TENSOR_7_DIM_2_SIZE 0xF06C3C |
| |
| #define mmTPC4_CFG_QM_TENSOR_7_DIM_2_STRIDE 0xF06C40 |
| |
| #define mmTPC4_CFG_QM_TENSOR_7_DIM_2_BASE_OFFSET 0xF06C44 |
| |
| #define mmTPC4_CFG_QM_TENSOR_7_DIM_3_SIZE 0xF06C48 |
| |
| #define mmTPC4_CFG_QM_TENSOR_7_DIM_3_STRIDE 0xF06C4C |
| |
| #define mmTPC4_CFG_QM_TENSOR_7_DIM_3_BASE_OFFSET 0xF06C50 |
| |
| #define mmTPC4_CFG_QM_TENSOR_7_DIM_4_SIZE 0xF06C54 |
| |
| #define mmTPC4_CFG_QM_TENSOR_7_DIM_4_STRIDE 0xF06C58 |
| |
| #define mmTPC4_CFG_QM_TENSOR_7_DIM_4_BASE_OFFSET 0xF06C5C |
| |
| #define mmTPC4_CFG_QM_KERNEL_BASE_ADDRESS_LOW 0xF06C60 |
| |
| #define mmTPC4_CFG_QM_KERNEL_BASE_ADDRESS_HIGH 0xF06C64 |
| |
| #define mmTPC4_CFG_QM_TID_BASE_DIM_0 0xF06C68 |
| |
| #define mmTPC4_CFG_QM_TID_SIZE_DIM_0 0xF06C6C |
| |
| #define mmTPC4_CFG_QM_TID_BASE_DIM_1 0xF06C70 |
| |
| #define mmTPC4_CFG_QM_TID_SIZE_DIM_1 0xF06C74 |
| |
| #define mmTPC4_CFG_QM_TID_BASE_DIM_2 0xF06C78 |
| |
| #define mmTPC4_CFG_QM_TID_SIZE_DIM_2 0xF06C7C |
| |
| #define mmTPC4_CFG_QM_TID_BASE_DIM_3 0xF06C80 |
| |
| #define mmTPC4_CFG_QM_TID_SIZE_DIM_3 0xF06C84 |
| |
| #define mmTPC4_CFG_QM_TID_BASE_DIM_4 0xF06C88 |
| |
| #define mmTPC4_CFG_QM_TID_SIZE_DIM_4 0xF06C8C |
| |
| #define mmTPC4_CFG_QM_SRF_0 0xF06C90 |
| |
| #define mmTPC4_CFG_QM_SRF_1 0xF06C94 |
| |
| #define mmTPC4_CFG_QM_SRF_2 0xF06C98 |
| |
| #define mmTPC4_CFG_QM_SRF_3 0xF06C9C |
| |
| #define mmTPC4_CFG_QM_SRF_4 0xF06CA0 |
| |
| #define mmTPC4_CFG_QM_SRF_5 0xF06CA4 |
| |
| #define mmTPC4_CFG_QM_SRF_6 0xF06CA8 |
| |
| #define mmTPC4_CFG_QM_SRF_7 0xF06CAC |
| |
| #define mmTPC4_CFG_QM_SRF_8 0xF06CB0 |
| |
| #define mmTPC4_CFG_QM_SRF_9 0xF06CB4 |
| |
| #define mmTPC4_CFG_QM_SRF_10 0xF06CB8 |
| |
| #define mmTPC4_CFG_QM_SRF_11 0xF06CBC |
| |
| #define mmTPC4_CFG_QM_SRF_12 0xF06CC0 |
| |
| #define mmTPC4_CFG_QM_SRF_13 0xF06CC4 |
| |
| #define mmTPC4_CFG_QM_SRF_14 0xF06CC8 |
| |
| #define mmTPC4_CFG_QM_SRF_15 0xF06CCC |
| |
| #define mmTPC4_CFG_QM_SRF_16 0xF06CD0 |
| |
| #define mmTPC4_CFG_QM_SRF_17 0xF06CD4 |
| |
| #define mmTPC4_CFG_QM_SRF_18 0xF06CD8 |
| |
| #define mmTPC4_CFG_QM_SRF_19 0xF06CDC |
| |
| #define mmTPC4_CFG_QM_SRF_20 0xF06CE0 |
| |
| #define mmTPC4_CFG_QM_SRF_21 0xF06CE4 |
| |
| #define mmTPC4_CFG_QM_SRF_22 0xF06CE8 |
| |
| #define mmTPC4_CFG_QM_SRF_23 0xF06CEC |
| |
| #define mmTPC4_CFG_QM_SRF_24 0xF06CF0 |
| |
| #define mmTPC4_CFG_QM_SRF_25 0xF06CF4 |
| |
| #define mmTPC4_CFG_QM_SRF_26 0xF06CF8 |
| |
| #define mmTPC4_CFG_QM_SRF_27 0xF06CFC |
| |
| #define mmTPC4_CFG_QM_SRF_28 0xF06D00 |
| |
| #define mmTPC4_CFG_QM_SRF_29 0xF06D04 |
| |
| #define mmTPC4_CFG_QM_SRF_30 0xF06D08 |
| |
| #define mmTPC4_CFG_QM_SRF_31 0xF06D0C |
| |
| #define mmTPC4_CFG_QM_KERNEL_CONFIG 0xF06D10 |
| |
| #define mmTPC4_CFG_QM_SYNC_OBJECT_MESSAGE 0xF06D14 |
| |
| #define mmTPC4_CFG_ARUSER 0xF06D18 |
| |
| #define mmTPC4_CFG_AWUSER 0xF06D1C |
| |
| #define mmTPC4_CFG_FUNC_MBIST_CNTRL 0xF06E00 |
| |
| #define mmTPC4_CFG_FUNC_MBIST_PAT 0xF06E04 |
| |
| #define mmTPC4_CFG_FUNC_MBIST_MEM_0 0xF06E08 |
| |
| #define mmTPC4_CFG_FUNC_MBIST_MEM_1 0xF06E0C |
| |
| #define mmTPC4_CFG_FUNC_MBIST_MEM_2 0xF06E10 |
| |
| #define mmTPC4_CFG_FUNC_MBIST_MEM_3 0xF06E14 |
| |
| #define mmTPC4_CFG_FUNC_MBIST_MEM_4 0xF06E18 |
| |
| #define mmTPC4_CFG_FUNC_MBIST_MEM_5 0xF06E1C |
| |
| #define mmTPC4_CFG_FUNC_MBIST_MEM_6 0xF06E20 |
| |
| #define mmTPC4_CFG_FUNC_MBIST_MEM_7 0xF06E24 |
| |
| #define mmTPC4_CFG_FUNC_MBIST_MEM_8 0xF06E28 |
| |
| #define mmTPC4_CFG_FUNC_MBIST_MEM_9 0xF06E2C |
| |
| #endif /* ASIC_REG_TPC4_CFG_REGS_H_ */ |
