| [ |
| { |
| "EventCode": "0xC7", |
| "UMask": "0x1", |
| "BriefDescription": "Number of SSE/AVX computational scalar double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 1 computation. Applies to SSE* and AVX* scalar double precision floating-point instructions: ADD SUB MUL DIV MIN MAX RCP14 RSQRT14 SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.", |
| "Counter": "0,1,2,3", |
| "EventName": "FP_ARITH_INST_RETIRED.SCALAR_DOUBLE", |
| "SampleAfterValue": "2000003", |
| "CounterHTOff": "0,1,2,3,4,5,6,7" |
| }, |
| { |
| "EventCode": "0xC7", |
| "UMask": "0x2", |
| "BriefDescription": "Number of SSE/AVX computational scalar single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 1 computation. Applies to SSE* and AVX* scalar single precision floating-point instructions: ADD SUB MUL DIV MIN MAX RCP14 RSQRT14 SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.", |
| "Counter": "0,1,2,3", |
| "EventName": "FP_ARITH_INST_RETIRED.SCALAR_SINGLE", |
| "SampleAfterValue": "2000003", |
| "CounterHTOff": "0,1,2,3,4,5,6,7" |
| }, |
| { |
| "EventCode": "0xC7", |
| "UMask": "0x4", |
| "BriefDescription": "Number of SSE/AVX computational 128-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 2 computation operations, one for each element. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT14 RCP14 DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.", |
| "Counter": "0,1,2,3", |
| "EventName": "FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE", |
| "SampleAfterValue": "2000003", |
| "CounterHTOff": "0,1,2,3,4,5,6,7" |
| }, |
| { |
| "EventCode": "0xC7", |
| "UMask": "0x8", |
| "BriefDescription": "Number of SSE/AVX computational 128-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 4 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB MUL DIV MIN MAX RCP14 RSQRT14 SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 4 calculations per element.", |
| "Counter": "0,1,2,3", |
| "EventName": "FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE", |
| "SampleAfterValue": "2000003", |
| "CounterHTOff": "0,1,2,3,4,5,6,7" |
| }, |
| { |
| "EventCode": "0xC7", |
| "UMask": "0x10", |
| "BriefDescription": "Number of SSE/AVX computational 256-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 4 computation operations, one for each element. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB MUL DIV MIN MAX RCP14 RSQRT14 SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 4 calculations per element.", |
| "Counter": "0,1,2,3", |
| "EventName": "FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE", |
| "SampleAfterValue": "2000003", |
| "CounterHTOff": "0,1,2,3,4,5,6,7" |
| }, |
| { |
| "EventCode": "0xC7", |
| "UMask": "0x20", |
| "BriefDescription": "Number of SSE/AVX computational 256-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 8 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB MUL DIV MIN MAX RCP14 RSQRT14 SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 8 calculations per element.", |
| "Counter": "0,1,2,3", |
| "EventName": "FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE", |
| "SampleAfterValue": "2000003", |
| "CounterHTOff": "0,1,2,3,4,5,6,7" |
| }, |
| { |
| "EventCode": "0xC7", |
| "UMask": "0x40", |
| "BriefDescription": "Number of SSE/AVX computational 512-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 8 computation operations, one for each element. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB MUL DIV MIN MAX RCP14 RSQRT14 SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 8 calculations per element.", |
| "Counter": "0,1,2,3", |
| "EventName": "FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE", |
| "SampleAfterValue": "2000003", |
| "CounterHTOff": "0,1,2,3,4,5,6,7" |
| }, |
| { |
| "EventCode": "0xC7", |
| "UMask": "0x80", |
| "BriefDescription": "Number of SSE/AVX computational 512-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 16 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB MUL DIV MIN MAX RCP14 RSQRT14 SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 16 calculations per element.", |
| "Counter": "0,1,2,3", |
| "EventName": "FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE", |
| "SampleAfterValue": "2000003", |
| "CounterHTOff": "0,1,2,3,4,5,6,7" |
| }, |
| { |
| "EventCode": "0xCA", |
| "UMask": "0x1e", |
| "BriefDescription": "Cycles with any input/output SSE or FP assist", |
| "Counter": "0,1,2,3", |
| "EventName": "FP_ASSIST.ANY", |
| "CounterMask": "1", |
| "PublicDescription": "Counts cycles with any input and output SSE or x87 FP assist. If an input and output assist are detected on the same cycle the event increments by 1.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3,4,5,6,7" |
| } |
| ] |
