| [ |
| { |
| "CollectPEBSRecord": "2", |
| "PublicDescription": "Counts all microcode Floating Point assists.", |
| "EventCode": "0xC1", |
| "Counter": "0,1,2,3,4,5,6,7", |
| "UMask": "0x2", |
| "PEBScounters": "0,1,2,3,4,5,6,7", |
| "EventName": "ASSISTS.FP", |
| "SampleAfterValue": "100003", |
| "BriefDescription": "Counts all microcode FP assists.", |
| "CounterMask": "1" |
| }, |
| { |
| "CollectPEBSRecord": "2", |
| "PublicDescription": "Counts number of SSE/AVX computational scalar double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 1 computational operation. Applies to SSE* and AVX* scalar double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.", |
| "EventCode": "0xc7", |
| "Counter": "0,1,2,3,4,5,6,7", |
| "UMask": "0x1", |
| "PEBScounters": "0,1,2,3,4,5,6,7", |
| "EventName": "FP_ARITH_INST_RETIRED.SCALAR_DOUBLE", |
| "SampleAfterValue": "2000003", |
| "BriefDescription": "Number of SSE/AVX computational scalar double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 1 computation. Applies to SSE* and AVX* scalar double precision floating-point instructions: ADD SUB MUL DIV MIN MAX RCP14 RSQRT14 RANGE SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element." |
| }, |
| { |
| "CollectPEBSRecord": "2", |
| "PublicDescription": "Counts number of SSE/AVX computational scalar single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 1 computational operation. Applies to SSE* and AVX* scalar single precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT RCP FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.", |
| "EventCode": "0xc7", |
| "Counter": "0,1,2,3,4,5,6,7", |
| "UMask": "0x2", |
| "PEBScounters": "0,1,2,3,4,5,6,7", |
| "EventName": "FP_ARITH_INST_RETIRED.SCALAR_SINGLE", |
| "SampleAfterValue": "2000003", |
| "BriefDescription": "Number of SSE/AVX computational scalar single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 1 computation. Applies to SSE* and AVX* scalar single precision floating-point instructions: ADD SUB MUL DIV MIN MAX RCP14 RSQRT14 RANGE SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element." |
| }, |
| { |
| "CollectPEBSRecord": "2", |
| "PublicDescription": "Counts number of SSE/AVX computational 128-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 2 computation operations, one for each element. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.", |
| "EventCode": "0xc7", |
| "Counter": "0,1,2,3,4,5,6,7", |
| "UMask": "0x4", |
| "PEBScounters": "0,1,2,3,4,5,6,7", |
| "EventName": "FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE", |
| "SampleAfterValue": "2000003", |
| "BriefDescription": "Number of SSE/AVX computational 128-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 2 computation operations, one for each element. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT14 RCP14 RANGE DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element." |
| }, |
| { |
| "CollectPEBSRecord": "2", |
| "PublicDescription": "Counts number of SSE/AVX computational 128-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 4 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RCP DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.", |
| "EventCode": "0xc7", |
| "Counter": "0,1,2,3,4,5,6,7", |
| "UMask": "0x8", |
| "PEBScounters": "0,1,2,3,4,5,6,7", |
| "EventName": "FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE", |
| "SampleAfterValue": "2000003", |
| "BriefDescription": "Number of SSE/AVX computational 128-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 4 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB MUL DIV MIN MAX RCP14 RSQRT14 SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element." |
| }, |
| { |
| "CollectPEBSRecord": "2", |
| "PublicDescription": "Counts number of SSE/AVX computational 256-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 4 computation operations, one for each element. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.", |
| "EventCode": "0xc7", |
| "Counter": "0,1,2,3,4,5,6,7", |
| "UMask": "0x10", |
| "PEBScounters": "0,1,2,3,4,5,6,7", |
| "EventName": "FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE", |
| "SampleAfterValue": "2000003", |
| "BriefDescription": "Number of SSE/AVX computational 256-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 4 computation operations, one for each element. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB MUL DIV MIN MAX RCP14 RSQRT14 RANGE SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element." |
| }, |
| { |
| "CollectPEBSRecord": "2", |
| "PublicDescription": "Counts number of SSE/AVX computational 256-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 8 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RCP DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.", |
| "EventCode": "0xc7", |
| "Counter": "0,1,2,3,4,5,6,7", |
| "UMask": "0x20", |
| "PEBScounters": "0,1,2,3,4,5,6,7", |
| "EventName": "FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE", |
| "SampleAfterValue": "2000003", |
| "BriefDescription": "Number of SSE/AVX computational 256-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 8 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB MUL DIV MIN MAX RCP14 RSQRT14 RANGE SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element." |
| }, |
| { |
| "CollectPEBSRecord": "2", |
| "PublicDescription": "Counts number of SSE/AVX computational 512-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 8 computation operations, one for each element. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT14 RCP14 RANGE FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.", |
| "EventCode": "0xc7", |
| "Counter": "0,1,2,3,4,5,6,7", |
| "UMask": "0x40", |
| "PEBScounters": "0,1,2,3,4,5,6,7", |
| "EventName": "FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE", |
| "SampleAfterValue": "2000003", |
| "BriefDescription": "Number of SSE/AVX computational 512-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 16 computation operations, one for each element. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT14 RCP14 RANGE FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element." |
| }, |
| { |
| "CollectPEBSRecord": "2", |
| "PublicDescription": "Counts number of SSE/AVX computational 512-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 16 computation operations, one for each element. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT14 RCP14 RANGE FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.", |
| "EventCode": "0xc7", |
| "Counter": "0,1,2,3,4,5,6,7", |
| "UMask": "0x80", |
| "PEBScounters": "0,1,2,3,4,5,6,7", |
| "EventName": "FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE", |
| "SampleAfterValue": "2000003", |
| "BriefDescription": "Number of SSE/AVX computational 512-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 8 computation operations, one for each element. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT14 RCP14 RANGE FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element." |
| } |
| ] |
